488 lines
13 KiB
C
488 lines
13 KiB
C
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/*-
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)isa.c 7.2 (Berkeley) 5/13/91
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* from: isa_dma.c,v 1.3 1999/05/09 23:56:00 peter Exp $
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* $Id$
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*/
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/*
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* code to manage AT bus
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*
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* 92/08/18 Frank P. MacLachlan (fpm@crash.cts.com):
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* Fixed uninitialized variable problem and added code to deal
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* with DMA page boundaries in isa_dmarangecheck(). Fixed word
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* mode DMA count compution and reorganized DMA setup code in
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* isa_dmastart()
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/buf.h> /* B_READ and B_RAW */
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#include <sys/malloc.h>
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#include <sys/bus.h>
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#include <vm/vm.h>
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#include <vm/vm_param.h>
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#include <vm/pmap.h>
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#include <isa/isareg.h>
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#include <isa/isavar.h>
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#include <i386/isa/ic/i8237.h>
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#include <machine/bus.h>
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/*
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** Register definitions for DMA controller 1 (channels 0..3):
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*/
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#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */
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#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */
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#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */
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#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */
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#define DMA1_RESET (IO_DMA1 + 1*13) /* reset */
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/*
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** Register definitions for DMA controller 2 (channels 4..7):
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*/
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#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */
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#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */
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#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */
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#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */
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#define DMA2_RESET (IO_DMA2 + 2*13) /* reset */
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static bus_dma_tag_t dma_tag[8];
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static bus_dmamap_t dma_map[8];
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static u_int8_t dma_busy = 0; /* Used in isa_dmastart() */
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static u_int8_t dma_inuse = 0; /* User for acquire/release */
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static u_int8_t dma_auto_mode = 0;
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#define VALID_DMA_MASK (7)
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/* high byte of address is stored in this port for i-th dma channel */
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static int dmapageport[8] = { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a };
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/*
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* Setup a DMA channel's bounce buffer.
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*/
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void
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isa_dmainit(chan, bouncebufsize)
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int chan;
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u_int bouncebufsize;
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{
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static int initted = 0;
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bus_addr_t boundary = chan >= 4 ? 0x20000 : 0x10000;
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if (!initted) {
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/*
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* Reset the DMA hardware.
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*/
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outb(DMA1_RESET, 0);
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outb(DMA2_RESET, 0);
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isa_dmacascade(4);
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initted = 1;
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}
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#ifdef DIAGNOSTIC
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if (chan & ~VALID_DMA_MASK)
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panic("isa_dmainit: channel out of range");
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if (dma_tag[chan] || dma_map[chan])
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panic("isa_dmainit: impossible request");
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#endif
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if (bus_dma_tag_create(/*parent*/NULL,
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/*alignment*/2,
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/*boundary*/boundary,
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/*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
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/*highaddr*/BUS_SPACE_MAXADDR,
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/*filter*/NULL, /*filterarg*/NULL,
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/*maxsize*/bouncebufsize,
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/*nsegments*/1, /*maxsegz*/0x3ffff,
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/*flags*/BUS_DMA_ISA,
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&dma_tag[chan]) != 0) {
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panic("isa_dmainit: unable to create dma tag\n");
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}
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if (bus_dmamap_create(dma_tag[chan], 0, &dma_map[chan])) {
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panic("isa_dmainit: unable to create dma map\n");
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}
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}
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/*
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* Register a DMA channel's usage. Usually called from a device driver
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* in open() or during its initialization.
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*/
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int
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isa_dma_acquire(chan)
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int chan;
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{
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#ifdef DIAGNOSTIC
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if (chan & ~VALID_DMA_MASK)
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panic("isa_dma_acquire: channel out of range");
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#endif
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if (dma_inuse & (1 << chan)) {
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printf("isa_dma_acquire: channel %d already in use\n", chan);
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return (EBUSY);
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}
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dma_inuse |= (1 << chan);
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dma_auto_mode &= ~(1 << chan);
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return (0);
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}
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/*
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* Unregister a DMA channel's usage. Usually called from a device driver
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* during close() or during its shutdown.
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*/
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void
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isa_dma_release(chan)
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int chan;
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{
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#ifdef DIAGNOSTIC
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if (chan & ~VALID_DMA_MASK)
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panic("isa_dma_release: channel out of range");
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if ((dma_inuse & (1 << chan)) == 0)
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printf("isa_dma_release: channel %d not in use\n", chan);
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#endif
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if (dma_busy & (1 << chan)) {
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dma_busy &= ~(1 << chan);
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/*
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* XXX We should also do "dma_bounced &= (1 << chan);"
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* because we are acting on behalf of isa_dmadone() which
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* was not called to end the last DMA operation. This does
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* not matter now, but it may in the future.
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*/
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}
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dma_inuse &= ~(1 << chan);
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dma_auto_mode &= ~(1 << chan);
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}
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/*
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* isa_dmacascade(): program 8237 DMA controller channel to accept
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* external dma control by a board.
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*/
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void
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isa_dmacascade(chan)
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int chan;
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{
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#ifdef DIAGNOSTIC
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if (chan & ~VALID_DMA_MASK)
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panic("isa_dmacascade: channel out of range");
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#endif
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/* set dma channel mode, and set dma channel mode */
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if ((chan & 4) == 0) {
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outb(DMA1_MODE, DMA37MD_CASCADE | chan);
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outb(DMA1_SMSK, chan);
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} else {
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outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3));
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outb(DMA2_SMSK, chan & 3);
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}
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}
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/*
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* isa_dmastart(): program 8237 DMA controller channel.
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*/
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struct isa_dmastart_arg {
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int chan;
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int flags;
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};
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static void isa_dmastart_cb(void *arg, bus_dma_segment_t *segs, int nseg,
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int error)
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{
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int chan = ((struct isa_dmastart_arg *) arg)->chan;
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int flags = ((struct isa_dmastart_arg *) arg)->flags;
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bus_addr_t phys = segs->ds_addr;
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int nbytes = segs->ds_len;
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int waport;
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if (nseg != 1)
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panic("isa_dmastart: transfer mapping not contiguous");
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if ((chan & 4) == 0) {
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/*
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* Program one of DMA channels 0..3. These are
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* byte mode channels.
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*/
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/* set dma channel mode, and reset address ff */
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/* If B_RAW flag is set, then use autoinitialise mode */
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if (flags & B_RAW) {
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if (flags & B_READ)
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outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan);
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else
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outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan);
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}
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else
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if (flags & B_READ)
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outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan);
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else
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outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan);
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outb(DMA1_FFC, 0);
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/* send start address */
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waport = DMA1_CHN(chan);
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outb(waport, phys);
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outb(waport, phys>>8);
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outb(dmapageport[chan], phys>>16);
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/* send count */
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outb(waport + 1, --nbytes);
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outb(waport + 1, nbytes>>8);
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/* unmask channel */
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outb(DMA1_SMSK, chan);
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} else {
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/*
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* Program one of DMA channels 4..7. These are
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* word mode channels.
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*/
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/* set dma channel mode, and reset address ff */
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/* If B_RAW flag is set, then use autoinitialise mode */
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if (flags & B_RAW) {
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if (flags & B_READ)
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outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_WRITE|(chan&3));
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else
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outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_READ|(chan&3));
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}
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else
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if (flags & B_READ)
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outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3));
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else
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outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3));
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outb(DMA2_FFC, 0);
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/* send start address */
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waport = DMA2_CHN(chan - 4);
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outb(waport, phys>>1);
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outb(waport, phys>>9);
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outb(dmapageport[chan], phys>>16);
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/* send count */
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nbytes >>= 1;
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outb(waport + 2, --nbytes);
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outb(waport + 2, nbytes>>8);
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/* unmask channel */
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outb(DMA2_SMSK, chan & 3);
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}
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}
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void
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isa_dmastart(int flags, caddr_t addr, u_int nbytes, int chan)
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{
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struct isa_dmastart_arg args;
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#ifdef DIAGNOSTIC
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if (chan & ~VALID_DMA_MASK)
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panic("isa_dmastart: channel out of range");
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if ((chan < 4 && nbytes > (1<<16))
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|| (chan >= 4 && (nbytes > (1<<17) || (uintptr_t)addr & 1)))
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panic("isa_dmastart: impossible request");
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if ((dma_inuse & (1 << chan)) == 0)
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printf("isa_dmastart: channel %d not acquired\n", chan);
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#endif
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#if 0
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/*
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* XXX This should be checked, but drivers like ad1848 only call
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* isa_dmastart() once because they use Auto DMA mode. If we
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* leave this in, drivers that do this will print this continuously.
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*/
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if (dma_busy & (1 << chan))
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printf("isa_dmastart: channel %d busy\n", chan);
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#endif
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if (!dma_tag || !dma_map[chan])
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panic("isa_dmastart: called without isa_dmainit");
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dma_busy |= (1 << chan);
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if (flags & B_RAW) {
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dma_auto_mode |= (1 << chan);
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} else {
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dma_auto_mode &= ~(1 << chan);
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}
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/*
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* Freeze dma while updating registers.
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*/
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outb(chan & 4 ? DMA2_SMSK : DMA1_SMSK, (chan & 3) | 4);
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args.chan = chan;
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args.flags = flags;
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bus_dmamap_load(dma_tag[chan], dma_map[chan], addr, nbytes,
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isa_dmastart_cb, &args, 0);
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}
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void
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isa_dmadone(int flags, caddr_t addr, int nbytes, int chan)
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{
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#ifdef DIAGNOSTIC
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if (chan & ~VALID_DMA_MASK)
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panic("isa_dmadone: channel out of range");
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if ((dma_inuse & (1 << chan)) == 0)
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||
|
|
printf("isa_dmadone: channel %d not acquired\n", chan);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
if (((dma_busy & (1 << chan)) == 0) &&
|
||
|
|
(dma_auto_mode & (1 << chan)) == 0 )
|
||
|
|
printf("isa_dmadone: channel %d not busy\n", chan);
|
||
|
|
|
||
|
|
if ((dma_auto_mode & (1 << chan)) == 0) {
|
||
|
|
outb(chan & 4 ? DMA2_SMSK : DMA1_SMSK, (chan & 3) | 4);
|
||
|
|
bus_dmamap_unload(dma_tag[chan], dma_map[chan]);
|
||
|
|
}
|
||
|
|
|
||
|
|
dma_busy &= ~(1 << chan);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Query the progress of a transfer on a DMA channel.
|
||
|
|
*
|
||
|
|
* To avoid having to interrupt a transfer in progress, we sample
|
||
|
|
* each of the high and low databytes twice, and apply the following
|
||
|
|
* logic to determine the correct count.
|
||
|
|
*
|
||
|
|
* Reads are performed with interrupts disabled, thus it is to be
|
||
|
|
* expected that the time between reads is very small. At most
|
||
|
|
* one rollover in the low count byte can be expected within the
|
||
|
|
* four reads that are performed.
|
||
|
|
*
|
||
|
|
* There are three gaps in which a rollover can occur :
|
||
|
|
*
|
||
|
|
* - read low1
|
||
|
|
* gap1
|
||
|
|
* - read high1
|
||
|
|
* gap2
|
||
|
|
* - read low2
|
||
|
|
* gap3
|
||
|
|
* - read high2
|
||
|
|
*
|
||
|
|
* If a rollover occurs in gap1 or gap2, the low2 value will be
|
||
|
|
* greater than the low1 value. In this case, low2 and high2 are a
|
||
|
|
* corresponding pair.
|
||
|
|
*
|
||
|
|
* In any other case, low1 and high1 can be considered to be correct.
|
||
|
|
*
|
||
|
|
* The function returns the number of bytes remaining in the transfer,
|
||
|
|
* or -1 if the channel requested is not active.
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
int
|
||
|
|
isa_dmastatus(int chan)
|
||
|
|
{
|
||
|
|
u_long cnt = 0;
|
||
|
|
int ffport, waport;
|
||
|
|
u_long low1, high1, low2, high2;
|
||
|
|
int s;
|
||
|
|
|
||
|
|
/* channel active? */
|
||
|
|
if ((dma_inuse & (1 << chan)) == 0) {
|
||
|
|
printf("isa_dmastatus: channel %d not active\n", chan);
|
||
|
|
return(-1);
|
||
|
|
}
|
||
|
|
/* channel busy? */
|
||
|
|
|
||
|
|
if (((dma_busy & (1 << chan)) == 0) &&
|
||
|
|
(dma_auto_mode & (1 << chan)) == 0 ) {
|
||
|
|
printf("chan %d not busy\n", chan);
|
||
|
|
return -2 ;
|
||
|
|
}
|
||
|
|
if (chan < 4) { /* low DMA controller */
|
||
|
|
ffport = DMA1_FFC;
|
||
|
|
waport = DMA1_CHN(chan) + 1;
|
||
|
|
} else { /* high DMA controller */
|
||
|
|
ffport = DMA2_FFC;
|
||
|
|
waport = DMA2_CHN(chan - 4) + 2;
|
||
|
|
}
|
||
|
|
|
||
|
|
s = splhigh(); /* no interrupts Mr Jones! */
|
||
|
|
outb(ffport, 0); /* clear register LSB flipflop */
|
||
|
|
low1 = inb(waport);
|
||
|
|
high1 = inb(waport);
|
||
|
|
outb(ffport, 0); /* clear again */
|
||
|
|
low2 = inb(waport);
|
||
|
|
high2 = inb(waport);
|
||
|
|
splx(s); /* enable interrupts again */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Now decide if a wrap has tried to skew our results.
|
||
|
|
* Note that after TC, the count will read 0xffff, while we want
|
||
|
|
* to return zero, so we add and then mask to compensate.
|
||
|
|
*/
|
||
|
|
if (low1 >= low2) {
|
||
|
|
cnt = (low1 + (high1 << 8) + 1) & 0xffff;
|
||
|
|
} else {
|
||
|
|
cnt = (low2 + (high2 << 8) + 1) & 0xffff;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (chan >= 4) /* high channels move words */
|
||
|
|
cnt *= 2;
|
||
|
|
return(cnt);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Stop a DMA transfer currently in progress.
|
||
|
|
*/
|
||
|
|
int
|
||
|
|
isa_dmastop(int chan)
|
||
|
|
{
|
||
|
|
if ((dma_inuse & (1 << chan)) == 0)
|
||
|
|
printf("isa_dmastop: channel %d not acquired\n", chan);
|
||
|
|
|
||
|
|
if (((dma_busy & (1 << chan)) == 0) &&
|
||
|
|
((dma_auto_mode & (1 << chan)) == 0)) {
|
||
|
|
printf("chan %d not busy\n", chan);
|
||
|
|
return -2 ;
|
||
|
|
}
|
||
|
|
|
||
|
|
if ((chan & 4) == 0) {
|
||
|
|
outb(DMA1_SMSK, (chan & 3) | 4 /* disable mask */);
|
||
|
|
} else {
|
||
|
|
outb(DMA2_SMSK, (chan & 3) | 4 /* disable mask */);
|
||
|
|
}
|
||
|
|
return(isa_dmastatus(chan));
|
||
|
|
}
|