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freebsd-dev/sys/arm/at91/uart_dev_at91usart.c

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Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
/*-
* Copyright (c) 2005 M. Warner Losh
Resurrect Skyeye support : Add a new option, SKYEYE_WORKAROUNDS, which as the name suggests adds workarounds for things skyeye doesn't simulate. Specifically : - Use USART0 instead of DBGU as the console, make it not use DMA, and manually provoke an interrupt when we're done in the transmit function. - Skyeye maintains an internal counter for clock, but apparently there's no way to access it, so hack the timecounter code to return a value which is increased at every clock interrupts. This is gross, but I didn't find a better way to implement timecounters without hacking Skyeye to get the counter value. - Force the write-back of PTEs once we're done writing them, even if they are supposed to be write-through. I don't know why I have to do that.
2006-05-13 23:41:16 +00:00
* Copyright (c) 2005 Olivier Houchard
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/conf.h>
#include <sys/cons.h>
#include <sys/tty.h>
#include <machine/bus.h>
#include <dev/uart/uart.h>
#include <dev/uart/uart_cpu.h>
#include <dev/uart/uart_bus.h>
#include <arm/at91/at91rm92reg.h>
#include <arm/at91/at91_usartreg.h>
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
#include <arm/at91/at91_pdcreg.h>
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
#include "uart_if.h"
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
#define DEFAULT_RCLK AT91C_MASTER_CLOCK
#define USART_BUFFER_SIZE 128
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
/*
* High-level UART interface.
*/
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
struct at91_usart_rx {
bus_addr_t pa;
uint8_t buffer[USART_BUFFER_SIZE];
bus_dmamap_t map;
};
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
struct at91_usart_softc {
struct uart_softc base;
bus_dma_tag_t dmatag; /* bus dma tag for mbufs */
bus_dmamap_t tx_map;
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
uint32_t flags;
#define HAS_TIMEOUT 1
struct at91_usart_rx ping_pong[2];
struct at91_usart_rx *ping;
struct at91_usart_rx *pong;
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
};
#define RD4(bas, reg) \
bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
#define WR4(bas, reg, value) \
bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
#define SIGCHG(c, i, s, d) \
do { \
if (c) { \
i |= (i & s) ? s : s | d; \
} else { \
i = (i & s) ? (i & ~s) | d : i; \
} \
} while (0);
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
#define BAUD2DIVISOR(b) \
((((DEFAULT_RCLK * 10) / ((b) * 16)) + 5) / 10)
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
/*
* Low-level UART interface.
*/
static int at91_usart_probe(struct uart_bas *bas);
static void at91_usart_init(struct uart_bas *bas, int, int, int, int);
static void at91_usart_term(struct uart_bas *bas);
static void at91_usart_putc(struct uart_bas *bas, int);
static int at91_usart_poll(struct uart_bas *bas);
MFp4: Catchup with recent UART changes.
2006-04-06 20:47:54 +00:00
static int at91_usart_getc(struct uart_bas *bas, struct mtx *mtx);
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
static int
at91_usart_param(struct uart_bas *bas, int baudrate, int databits,
int stopbits, int parity)
{
uint32_t mr;
/*
* Assume 3-write RS-232 configuration.
* XXX Not sure how uart will present the other modes to us, so
* XXX they are unimplemented. maybe ioctl?
*/
mr = USART_MR_MODE_NORMAL;
mr |= USART_MR_USCLKS_MCK; /* Assume MCK */
/*
* Or in the databits requested
*/
if (databits < 9)
mr &= ~USART_MR_MODE9;
switch (databits) {
case 5:
mr |= USART_MR_CHRL_5BITS;
break;
case 6:
mr |= USART_MR_CHRL_6BITS;
break;
case 7:
mr |= USART_MR_CHRL_7BITS;
break;
case 8:
mr |= USART_MR_CHRL_8BITS;
break;
case 9:
mr |= USART_MR_CHRL_8BITS | USART_MR_MODE9;
break;
default:
return (EINVAL);
}
/*
* Or in the parity
*/
switch (parity) {
case UART_PARITY_NONE:
mr |= USART_MR_PAR_NONE;
break;
case UART_PARITY_ODD:
mr |= USART_MR_PAR_ODD;
break;
case UART_PARITY_EVEN:
mr |= USART_MR_PAR_EVEN;
break;
case UART_PARITY_MARK:
mr |= USART_MR_PAR_MARK;
break;
case UART_PARITY_SPACE:
mr |= USART_MR_PAR_SPACE;
break;
default:
return (EINVAL);
}
/*
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
* Or in the stop bits. Note: The hardware supports 1.5 stop
* bits in async mode, but there's no way to specify that
* AFAICT. Instead, rely on the convention documented at
* http://www.lammertbies.nl/comm/info/RS-232_specs.html which
* states that 1.5 stop bits are used for 5 bit bytes and
* 2 stop bits only for longer bytes.
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
*/
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
if (stopbits == 1)
mr |= USART_MR_NBSTOP_1;
else if (databits > 5)
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
mr |= USART_MR_NBSTOP_2;
else
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
mr |= USART_MR_NBSTOP_1_5;
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
/*
* We want normal plumbing mode too, none of this fancy
* loopback or echo mode.
*/
mr |= USART_MR_CHMODE_NORMAL;
mr &= ~USART_MR_MSBF; /* lsb first */
mr &= ~USART_MR_CKLO_SCK; /* Don't drive SCK */
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
WR4(bas, USART_MR, mr);
/*
* Set the baud rate
*/
WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate));
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
/* XXX Need to take possible synchronous mode into account */
return (0);
}
struct uart_ops at91_usart_ops = {
.probe = at91_usart_probe,
.init = at91_usart_init,
.term = at91_usart_term,
.putc = at91_usart_putc,
.poll = at91_usart_poll,
.getc = at91_usart_getc,
};
static int
at91_usart_probe(struct uart_bas *bas)
{
/* We know that this is always here */
return (0);
}
/*
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
* Initialize this device for use as a console.
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
*/
static void
at91_usart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
int parity)
{
MFp4: Handle break interrupts (it seems to only work for USART, not DBGU).
2006-03-22 21:16:09 +00:00
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
at91_usart_param(bas, baudrate, databits, stopbits, parity);
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
/* Reset the rx and tx buffers and turn on rx and tx */
WR4(bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX);
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
WR4(bas, USART_IDR, 0xffffffff);
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
}
/*
* Free resources now that we're no longer the console. This appears to
* be never called, and I'm unsure quite what to do if I am called.
*/
static void
at91_usart_term(struct uart_bas *bas)
{
/* XXX */
}
/*
* Put a character of console output (so we do it here polling rather than
* interrutp driven).
*/
static void
at91_usart_putc(struct uart_bas *bas, int c)
{
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
while (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY))
continue;
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
WR4(bas, USART_THR, c);
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
}
/*
* Poll for a character available
*/
static int
at91_usart_poll(struct uart_bas *bas)
{
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
if (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY))
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
return (-1);
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
return (RD4(bas, USART_RHR) & 0xff);
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
}
/*
* Block waiting for a character.
*/
static int
MFp4: Catchup with recent UART changes.
2006-04-06 20:47:54 +00:00
at91_usart_getc(struct uart_bas *bas, struct mtx *mtx)
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
{
int c;
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
while (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY))
continue;
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
c = RD4(bas, USART_RHR);
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
c &= 0xff;
return (c);
}
static int at91_usart_bus_probe(struct uart_softc *sc);
static int at91_usart_bus_attach(struct uart_softc *sc);
static int at91_usart_bus_flush(struct uart_softc *, int);
static int at91_usart_bus_getsig(struct uart_softc *);
static int at91_usart_bus_ioctl(struct uart_softc *, int, intptr_t);
static int at91_usart_bus_ipend(struct uart_softc *);
static int at91_usart_bus_param(struct uart_softc *, int, int, int, int);
static int at91_usart_bus_receive(struct uart_softc *);
static int at91_usart_bus_setsig(struct uart_softc *, int);
static int at91_usart_bus_transmit(struct uart_softc *);
static kobj_method_t at91_usart_methods[] = {
KOBJMETHOD(uart_probe, at91_usart_bus_probe),
KOBJMETHOD(uart_attach, at91_usart_bus_attach),
KOBJMETHOD(uart_flush, at91_usart_bus_flush),
KOBJMETHOD(uart_getsig, at91_usart_bus_getsig),
KOBJMETHOD(uart_ioctl, at91_usart_bus_ioctl),
KOBJMETHOD(uart_ipend, at91_usart_bus_ipend),
KOBJMETHOD(uart_param, at91_usart_bus_param),
KOBJMETHOD(uart_receive, at91_usart_bus_receive),
KOBJMETHOD(uart_setsig, at91_usart_bus_setsig),
KOBJMETHOD(uart_transmit, at91_usart_bus_transmit),
{ 0, 0 }
};
int
at91_usart_bus_probe(struct uart_softc *sc)
{
return (0);
}
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
#ifndef SKYEYE_WORKAROUNDS
static void
at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
{
if (error != 0)
return;
*(bus_addr_t *)arg = segs[0].ds_addr;
}
#endif
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
static int
at91_usart_bus_attach(struct uart_softc *sc)
{
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
int err, i;
uint32_t cr;
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
struct at91_usart_softc *atsc;
atsc = (struct at91_usart_softc *)sc;
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
/*
* See if we have a TIMEOUT bit. We disable all interrupts to
* minimize interference.
*/
WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT);
if (RD4(&sc->sc_bas, USART_IMR) & USART_CSR_TIMEOUT)
atsc->flags |= HAS_TIMEOUT;
WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
sc->sc_txfifosz = USART_BUFFER_SIZE;
sc->sc_rxfifosz = USART_BUFFER_SIZE;
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
sc->sc_hwiflow = 0;
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
/*
* Allocate DMA tags and maps
*/
err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
BUS_SPACE_MAXADDR, NULL, NULL, USART_BUFFER_SIZE, 1,
USART_BUFFER_SIZE, BUS_DMA_ALLOCNOW, NULL, NULL, &atsc->dmatag);
if (err != 0)
goto errout;
err = bus_dmamap_create(atsc->dmatag, 0, &atsc->tx_map);
if (err != 0)
goto errout;
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
if (atsc->flags & HAS_TIMEOUT) {
for (i = 0; i < 2; i++) {
err = bus_dmamap_create(atsc->dmatag, 0,
&atsc->ping_pong[i].map);
if (err != 0)
goto errout;
err = bus_dmamap_load(atsc->dmatag,
atsc->ping_pong[i].map,
atsc->ping_pong[i].buffer, sc->sc_rxfifosz,
at91_getaddr, &atsc->ping_pong[i].pa, 0);
if (err != 0)
goto errout;
bus_dmamap_sync(atsc->dmatag, atsc->ping_pong[i].map,
BUS_DMASYNC_PREREAD);
}
atsc->ping = &atsc->ping_pong[0];
atsc->pong = &atsc->ping_pong[1];
}
/*
* Prime the pump with the RX buffer. We use two 64 byte bounce
* buffers here to avoid data overflow.
*/
/* Turn on rx and tx */
cr = USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX;
WR4(&sc->sc_bas, USART_CR, cr);
WR4(&sc->sc_bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
/*
* Setup the PDC to receive data. We use the ping-pong buffers
* so that we can more easily bounce between the two and so that
* we get an interrupt 1/2 way through the software 'fifo' we have
* to avoid overruns.
*/
if (atsc->flags & HAS_TIMEOUT) {
WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
/* Set the receive timeout to be 1.5 character times. */
WR4(&sc->sc_bas, USART_RTOR, 12);
WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT |
USART_CSR_RXBUFF | USART_CSR_ENDRX);
} else {
WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY);
}
WR4(&sc->sc_bas, USART_IER, USART_CSR_RXBRK);
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
errout:;
// XXX bad
return (err);
}
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
static int
at91_usart_bus_transmit(struct uart_softc *sc)
{
Resurrect Skyeye support : Add a new option, SKYEYE_WORKAROUNDS, which as the name suggests adds workarounds for things skyeye doesn't simulate. Specifically : - Use USART0 instead of DBGU as the console, make it not use DMA, and manually provoke an interrupt when we're done in the transmit function. - Skyeye maintains an internal counter for clock, but apparently there's no way to access it, so hack the timecounter code to return a value which is increased at every clock interrupts. This is gross, but I didn't find a better way to implement timecounters without hacking Skyeye to get the counter value. - Force the write-back of PTEs once we're done writing them, even if they are supposed to be write-through. I don't know why I have to do that.
2006-05-13 23:41:16 +00:00
#ifndef SKYEYE_WORKAROUNDS
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
bus_addr_t addr;
Resurrect Skyeye support : Add a new option, SKYEYE_WORKAROUNDS, which as the name suggests adds workarounds for things skyeye doesn't simulate. Specifically : - Use USART0 instead of DBGU as the console, make it not use DMA, and manually provoke an interrupt when we're done in the transmit function. - Skyeye maintains an internal counter for clock, but apparently there's no way to access it, so hack the timecounter code to return a value which is increased at every clock interrupts. This is gross, but I didn't find a better way to implement timecounters without hacking Skyeye to get the counter value. - Force the write-back of PTEs once we're done writing them, even if they are supposed to be write-through. I don't know why I have to do that.
2006-05-13 23:41:16 +00:00
#endif
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
struct at91_usart_softc *atsc;
atsc = (struct at91_usart_softc *)sc;
Resurrect Skyeye support : Add a new option, SKYEYE_WORKAROUNDS, which as the name suggests adds workarounds for things skyeye doesn't simulate. Specifically : - Use USART0 instead of DBGU as the console, make it not use DMA, and manually provoke an interrupt when we're done in the transmit function. - Skyeye maintains an internal counter for clock, but apparently there's no way to access it, so hack the timecounter code to return a value which is increased at every clock interrupts. This is gross, but I didn't find a better way to implement timecounters without hacking Skyeye to get the counter value. - Force the write-back of PTEs once we're done writing them, even if they are supposed to be write-through. I don't know why I have to do that.
2006-05-13 23:41:16 +00:00
#ifndef SKYEYE_WORKAROUNDS
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
if (bus_dmamap_load(atsc->dmatag, atsc->tx_map, sc->sc_txbuf,
sc->sc_txdatasz, at91_getaddr, &addr, 0) != 0)
return (EAGAIN);
bus_dmamap_sync(atsc->dmatag, atsc->tx_map, BUS_DMASYNC_PREWRITE);
Resurrect Skyeye support : Add a new option, SKYEYE_WORKAROUNDS, which as the name suggests adds workarounds for things skyeye doesn't simulate. Specifically : - Use USART0 instead of DBGU as the console, make it not use DMA, and manually provoke an interrupt when we're done in the transmit function. - Skyeye maintains an internal counter for clock, but apparently there's no way to access it, so hack the timecounter code to return a value which is increased at every clock interrupts. This is gross, but I didn't find a better way to implement timecounters without hacking Skyeye to get the counter value. - Force the write-back of PTEs once we're done writing them, even if they are supposed to be write-through. I don't know why I have to do that.
2006-05-13 23:41:16 +00:00
#endif
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
MFp4: Catchup with recent UART changes.
2006-04-06 20:47:54 +00:00
uart_lock(sc->sc_hwmtx);
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
sc->sc_txbusy = 1;
Resurrect Skyeye support : Add a new option, SKYEYE_WORKAROUNDS, which as the name suggests adds workarounds for things skyeye doesn't simulate. Specifically : - Use USART0 instead of DBGU as the console, make it not use DMA, and manually provoke an interrupt when we're done in the transmit function. - Skyeye maintains an internal counter for clock, but apparently there's no way to access it, so hack the timecounter code to return a value which is increased at every clock interrupts. This is gross, but I didn't find a better way to implement timecounters without hacking Skyeye to get the counter value. - Force the write-back of PTEs once we're done writing them, even if they are supposed to be write-through. I don't know why I have to do that.
2006-05-13 23:41:16 +00:00
#ifndef SKYEYE_WORKAROUNDS
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
/*
* Setup the PDC to transfer the data and interrupt us when it
* is done. We've already requested the interrupt.
*/
WR4(&sc->sc_bas, PDC_TPR, addr);
WR4(&sc->sc_bas, PDC_TCR, sc->sc_txdatasz);
WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_TXTEN);
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
WR4(&sc->sc_bas, USART_IER, USART_CSR_ENDTX);
MFp4: Catchup with recent UART changes.
2006-04-06 20:47:54 +00:00
uart_unlock(sc->sc_hwmtx);
Resurrect Skyeye support : Add a new option, SKYEYE_WORKAROUNDS, which as the name suggests adds workarounds for things skyeye doesn't simulate. Specifically : - Use USART0 instead of DBGU as the console, make it not use DMA, and manually provoke an interrupt when we're done in the transmit function. - Skyeye maintains an internal counter for clock, but apparently there's no way to access it, so hack the timecounter code to return a value which is increased at every clock interrupts. This is gross, but I didn't find a better way to implement timecounters without hacking Skyeye to get the counter value. - Force the write-back of PTEs once we're done writing them, even if they are supposed to be write-through. I don't know why I have to do that.
2006-05-13 23:41:16 +00:00
#else
for (int i = 0; i < sc->sc_txdatasz; i++)
at91_usart_putc(&sc->sc_bas, sc->sc_txbuf[i]);
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
/*
* XXX: Gross hack : Skyeye doesn't raise an interrupt once the
* transfer is done, so simulate it.
*/
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
WR4(&sc->sc_bas, USART_IER, USART_CSR_TXRDY);
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
#endif
return (0);
}
static int
at91_usart_bus_setsig(struct uart_softc *sc, int sig)
{
uint32_t new, old, cr;
struct uart_bas *bas;
do {
old = sc->sc_hwsig;
new = old;
if (sig & SER_DDTR)
SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR);
if (sig & SER_DRTS)
SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS);
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
bas = &sc->sc_bas;
MFp4: Catchup with recent UART changes.
2006-04-06 20:47:54 +00:00
uart_lock(sc->sc_hwmtx);
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
cr = 0;
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
if (new & SER_DTR)
cr |= USART_CR_DTREN;
else
cr |= USART_CR_DTRDIS;
if (new & SER_RTS)
cr |= USART_CR_RTSEN;
else
cr |= USART_CR_RTSDIS;
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
WR4(bas, USART_CR, cr);
MFp4: Catchup with recent UART changes.
2006-04-06 20:47:54 +00:00
uart_unlock(sc->sc_hwmtx);
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
return (0);
}
static int
at91_usart_bus_receive(struct uart_softc *sc)
{
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
return (0);
}
static int
at91_usart_bus_param(struct uart_softc *sc, int baudrate, int databits,
int stopbits, int parity)
{
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
return (at91_usart_param(&sc->sc_bas, baudrate, databits, stopbits,
parity));
}
static int
at91_usart_bus_ipend(struct uart_softc *sc)
{
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
int csr = RD4(&sc->sc_bas, USART_CSR);
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
int ipend = 0, i, len;
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
struct at91_usart_softc *atsc;
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
struct at91_usart_rx *p;
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
Resurrect Skyeye support : Add a new option, SKYEYE_WORKAROUNDS, which as the name suggests adds workarounds for things skyeye doesn't simulate. Specifically : - Use USART0 instead of DBGU as the console, make it not use DMA, and manually provoke an interrupt when we're done in the transmit function. - Skyeye maintains an internal counter for clock, but apparently there's no way to access it, so hack the timecounter code to return a value which is increased at every clock interrupts. This is gross, but I didn't find a better way to implement timecounters without hacking Skyeye to get the counter value. - Force the write-back of PTEs once we're done writing them, even if they are supposed to be write-through. I don't know why I have to do that.
2006-05-13 23:41:16 +00:00
atsc = (struct at91_usart_softc *)sc;
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
if (csr & USART_CSR_ENDTX) {
bus_dmamap_sync(atsc->dmatag, atsc->tx_map,
BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(atsc->dmatag, atsc->tx_map);
}
MFp4: Catchup with recent UART changes.
2006-04-06 20:47:54 +00:00
uart_lock(sc->sc_hwmtx);
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
if (csr & USART_CSR_TXRDY) {
if (sc->sc_txbusy)
ipend |= SER_INT_TXIDLE;
WR4(&sc->sc_bas, USART_IDR, USART_CSR_TXRDY);
}
if (csr & USART_CSR_ENDTX) {
if (sc->sc_txbusy)
ipend |= SER_INT_TXIDLE;
WR4(&sc->sc_bas, USART_IDR, USART_CSR_ENDTX);
}
/*
* Due to the contraints of the DMA engine present in the
* atmel chip, I can't just say I have a rx interrupt pending
* and do all the work elsewhere. I need to look at the CSR
* bits right now and do things based on them to avoid races.
*/
if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXBUFF)) {
// Have a buffer overflow. Copy all data from both
// ping and pong. Insert overflow character. Reset
// ping and pong and re-enable the PDC to receive
// characters again.
bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
BUS_DMASYNC_POSTREAD);
bus_dmamap_sync(atsc->dmatag, atsc->pong->map,
BUS_DMASYNC_POSTREAD);
for (i = 0; i < sc->sc_rxfifosz; i++)
uart_rx_put(sc, atsc->ping->buffer[i]);
for (i = 0; i < sc->sc_rxfifosz; i++)
uart_rx_put(sc, atsc->pong->buffer[i]);
uart_rx_put(sc, UART_STAT_OVERRUN);
csr &= ~(USART_CSR_ENDRX | USART_CSR_TIMEOUT);
WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
ipend |= SER_INT_RXREADY;
}
if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_ENDRX)) {
// Shuffle data from 'ping' of ping pong buffer, but
// leave current 'pong' in place, as it has become the
// new 'ping'. We need to copy data and setup the old
// 'ping' as the new 'pong' when we're done.
bus_dmamap_sync(atsc->dmatag, atsc->ping->map,
BUS_DMASYNC_POSTREAD);
for (i = 0; i < sc->sc_rxfifosz; i++)
uart_rx_put(sc, atsc->ping->buffer[i]);
p = atsc->ping;
atsc->ping = atsc->pong;
atsc->pong = p;
WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
ipend |= SER_INT_RXREADY;
}
if ((atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_TIMEOUT)) {
// We have one partial buffer. We need to stop the
// PDC, get the number of characters left and from
// that compute number of valid characters. We then
// need to reset ping and pong and reenable the PDC.
// Not sure if there's a race here at fast baud rates
// we need to worry about.
WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS);
len = sc->sc_rxfifosz - RD4(&sc->sc_bas, PDC_RCR);
for (i = 0; i < len; i++)
uart_rx_put(sc, atsc->ping->buffer[i]);
WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
ipend |= SER_INT_RXREADY;
}
if (!(atsc->flags & HAS_TIMEOUT) && (csr & USART_CSR_RXRDY)) {
// We have another charater in a device that doesn't support
// timeouts, so we do it one character at a time.
uart_rx_put(sc, RD4(&sc->sc_bas, USART_RHR) & 0xff);
Get this to compile with the recent UART changes.
2006-02-27 23:19:13 +00:00
ipend |= SER_INT_RXREADY;
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
}
MFp4: Handle break interrupts (it seems to only work for USART, not DBGU).
2006-03-22 21:16:09 +00:00
if (csr & USART_CSR_RXBRK) {
unsigned int cr = USART_CR_RSTSTA;
ipend |= SER_INT_BREAK;
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
WR4(&sc->sc_bas, USART_CR, cr);
MFp4: Handle break interrupts (it seems to only work for USART, not DBGU).
2006-03-22 21:16:09 +00:00
}
MFp4: Catchup with recent UART changes.
2006-04-06 20:47:54 +00:00
uart_unlock(sc->sc_hwmtx);
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
return (ipend);
}
static int
at91_usart_bus_flush(struct uart_softc *sc, int what)
{
return (0);
}
static int
at91_usart_bus_getsig(struct uart_softc *sc)
{
uint32_t new, sig;
uint8_t csr;
MFp4: Catchup with recent UART changes.
2006-04-06 20:47:54 +00:00
uart_lock(sc->sc_hwmtx);
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
csr = RD4(&sc->sc_bas, USART_CSR);
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
sig = 0;
if (csr & USART_CSR_CTS)
sig |= SER_CTS;
if (csr & USART_CSR_DCD)
sig |= SER_DCD;
if (csr & USART_CSR_DSR)
sig |= SER_DSR;
if (csr & USART_CSR_RI)
sig |= SER_RI;
Get this to compile with the recent UART changes.
2006-02-27 23:19:13 +00:00
new = sig & ~SER_MASK_DELTA;
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
sc->sc_hwsig = new;
MFp4: Catchup with recent UART changes.
2006-04-06 20:47:54 +00:00
uart_unlock(sc->sc_hwmtx);
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
return (sig);
}
static int
at91_usart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
{
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
switch (request) {
case UART_IOCTL_BREAK:
case UART_IOCTL_IFLOW:
case UART_IOCTL_OFLOW:
break;
case UART_IOCTL_BAUD:
WR4(&sc->sc_bas, USART_BRGR, BAUD2DIVISOR(*(int *)data));
return (0);
}
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
return (EINVAL);
}
struct uart_class at91_usart_class = {
"at91_usart class",
at91_usart_methods,
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
sizeof(struct at91_usart_softc),
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
.uc_range = 8,
.uc_rclk = DEFAULT_RCLK
};
Reference in New Issue Copy Permalink