2016-03-16 13:01:48 +00:00
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/*-
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* Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Nvidia Integrated PCI/PCI-Express controller driver.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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2016-08-19 10:53:17 +00:00
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#include <sys/bus.h>
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#include <sys/devmap.h>
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#include <sys/proc.h>
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2016-03-16 13:01:48 +00:00
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <machine/intr.h>
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#include <vm/vm.h>
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2016-08-19 10:53:17 +00:00
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#include <vm/vm_extern.h>
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#include <vm/vm_kern.h>
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2016-03-16 13:01:48 +00:00
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#include <vm/pmap.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <dev/extres/phy/phy.h>
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#include <dev/extres/regulator/regulator.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/ofw_pci.h>
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2016-07-17 14:45:15 +00:00
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#include <dev/ofw/ofwpci.h>
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2016-03-16 13:01:48 +00:00
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcib_private.h>
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include <arm/nvidia/tegra_pmc.h>
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2016-07-17 14:45:15 +00:00
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#include "ofw_bus_if.h"
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2016-08-19 10:53:17 +00:00
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#include "msi_if.h"
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2016-07-17 14:45:15 +00:00
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#include "pcib_if.h"
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2016-08-19 10:53:17 +00:00
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#include "pic_if.h"
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2016-03-16 13:01:48 +00:00
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#define AFI_AXI_BAR0_SZ 0x000
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#define AFI_AXI_BAR1_SZ 0x004
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#define AFI_AXI_BAR2_SZ 0x008
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#define AFI_AXI_BAR3_SZ 0x00c
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#define AFI_AXI_BAR4_SZ 0x010
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#define AFI_AXI_BAR5_SZ 0x014
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#define AFI_AXI_BAR0_START 0x018
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#define AFI_AXI_BAR1_START 0x01c
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#define AFI_AXI_BAR2_START 0x020
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#define AFI_AXI_BAR3_START 0x024
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#define AFI_AXI_BAR4_START 0x028
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#define AFI_AXI_BAR5_START 0x02c
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#define AFI_FPCI_BAR0 0x030
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#define AFI_FPCI_BAR1 0x034
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#define AFI_FPCI_BAR2 0x038
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#define AFI_FPCI_BAR3 0x03c
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#define AFI_FPCI_BAR4 0x040
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#define AFI_FPCI_BAR5 0x044
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#define AFI_MSI_BAR_SZ 0x060
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#define AFI_MSI_FPCI_BAR_ST 0x064
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#define AFI_MSI_AXI_BAR_ST 0x068
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2016-08-19 10:53:17 +00:00
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#define AFI_MSI_VEC(x) (0x06c + 4 * (x))
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#define AFI_MSI_EN_VEC(x) (0x08c + 4 * (x))
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#define AFI_MSI_INTR_IN_REG 32
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#define AFI_MSI_REGS 8
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2016-03-16 13:01:48 +00:00
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#define AFI_CONFIGURATION 0x0ac
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#define AFI_CONFIGURATION_EN_FPCI (1 << 0)
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#define AFI_FPCI_ERROR_MASKS 0x0b0
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#define AFI_INTR_MASK 0x0b4
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#define AFI_INTR_MASK_MSI_MASK (1 << 8)
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#define AFI_INTR_MASK_INT_MASK (1 << 0)
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#define AFI_INTR_CODE 0x0b8
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#define AFI_INTR_CODE_MASK 0xf
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#define AFI_INTR_CODE_INT_CODE_INI_SLVERR 1
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#define AFI_INTR_CODE_INT_CODE_INI_DECERR 2
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#define AFI_INTR_CODE_INT_CODE_TGT_SLVERR 3
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#define AFI_INTR_CODE_INT_CODE_TGT_DECERR 4
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#define AFI_INTR_CODE_INT_CODE_TGT_WRERR 5
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#define AFI_INTR_CODE_INT_CODE_SM_MSG 6
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#define AFI_INTR_CODE_INT_CODE_DFPCI_DECERR 7
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#define AFI_INTR_CODE_INT_CODE_AXI_DECERR 8
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#define AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT 9
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#define AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE 10
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#define AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE 11
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#define AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE 12
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#define AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE 13
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#define AFI_INTR_CODE_INT_CODE_P2P_ERROR 14
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#define AFI_INTR_SIGNATURE 0x0bc
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#define AFI_UPPER_FPCI_ADDRESS 0x0c0
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#define AFI_SM_INTR_ENABLE 0x0c4
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#define AFI_SM_INTR_RP_DEASSERT (1 << 14)
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#define AFI_SM_INTR_RP_ASSERT (1 << 13)
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#define AFI_SM_INTR_HOTPLUG (1 << 12)
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#define AFI_SM_INTR_PME (1 << 11)
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#define AFI_SM_INTR_FATAL_ERROR (1 << 10)
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#define AFI_SM_INTR_UNCORR_ERROR (1 << 9)
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#define AFI_SM_INTR_CORR_ERROR (1 << 8)
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#define AFI_SM_INTR_INTD_DEASSERT (1 << 7)
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#define AFI_SM_INTR_INTC_DEASSERT (1 << 6)
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#define AFI_SM_INTR_INTB_DEASSERT (1 << 5)
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#define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
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#define AFI_SM_INTR_INTD_ASSERT (1 << 3)
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#define AFI_SM_INTR_INTC_ASSERT (1 << 2)
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#define AFI_SM_INTR_INTB_ASSERT (1 << 1)
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#define AFI_SM_INTR_INTA_ASSERT (1 << 0)
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#define AFI_AFI_INTR_ENABLE 0x0c8
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#define AFI_AFI_INTR_ENABLE_CODE(code) (1 << (code))
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#define AFI_PCIE_CONFIG 0x0f8
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#define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
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#define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0x6
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#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
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#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1 (0x0 << 20)
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#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1 (0x1 << 20)
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#define AFI_FUSE 0x104
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#define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
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#define AFI_PEX0_CTRL 0x110
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#define AFI_PEX1_CTRL 0x118
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#define AFI_PEX2_CTRL 0x128
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#define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4)
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#define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
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#define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
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#define AFI_PEX_CTRL_RST_L (1 << 0)
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#define AFI_AXI_BAR6_SZ 0x134
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#define AFI_AXI_BAR7_SZ 0x138
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#define AFI_AXI_BAR8_SZ 0x13c
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#define AFI_AXI_BAR6_START 0x140
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#define AFI_AXI_BAR7_START 0x144
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#define AFI_AXI_BAR8_START 0x148
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#define AFI_FPCI_BAR6 0x14c
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#define AFI_FPCI_BAR7 0x150
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#define AFI_FPCI_BAR8 0x154
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#define AFI_PLLE_CONTROL 0x160
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#define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9)
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#define AFI_PLLE_CONTROL_BYPASS_PCIE2PLLE_CONTROL (1 << 8)
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#define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1)
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#define AFI_PLLE_CONTROL_PCIE2PLLE_CONTROL_EN (1 << 0)
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#define AFI_PEXBIAS_CTRL 0x168
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/* FPCI Address space */
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#define FPCI_MAP_IO 0xfdfc000000ULL
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#define FPCI_MAP_TYPE0_CONFIG 0xfdfc000000ULL
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#define FPCI_MAP_TYPE1_CONFIG 0xfdff000000ULL
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#define FPCI_MAP_EXT_TYPE0_CONFIG 0xfe00000000ULL
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#define FPCI_MAP_EXT_TYPE1_CONFIG 0xfe10000000ULL
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/* Configuration space */
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#define RP_VEND_XP 0x00000F00
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#define RP_VEND_XP_DL_UP (1 << 30)
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#define RP_PRIV_MISC 0x00000FE0
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#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0)
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#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0)
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#define RP_LINK_CONTROL_STATUS 0x00000090
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#define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
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#define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
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2016-10-04 09:14:48 +00:00
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/* Wait 50 ms (per port) for link. */
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#define TEGRA_PCIE_LINKUP_TIMEOUT 50000
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2016-08-19 10:53:17 +00:00
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#define TEGRA_PCIB_MSI_ENABLE
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2016-03-16 13:01:48 +00:00
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#define DEBUG
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#ifdef DEBUG
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#define debugf(fmt, args...) do { printf(fmt,##args); } while (0)
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#else
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#define debugf(fmt, args...)
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#endif
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/*
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* Configuration space format:
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* [27:24] extended register
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* [23:16] bus
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* [15:11] slot (device)
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* [10: 8] function
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* [ 7: 0] register
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*/
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#define PCI_CFG_EXT_REG(reg) ((((reg) >> 8) & 0x0f) << 24)
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#define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16)
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#define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11)
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#define PCI_CFG_FUN(fun) (((fun) & 0x07) << 8)
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#define PCI_CFG_BASE_REG(reg) ((reg) & 0xff)
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#define PADS_WR4(_sc, _r, _v) bus_write_4((_sc)-pads_mem_res, (_r), (_v))
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#define PADS_RD4(_sc, _r) bus_read_4((_sc)->pads_mem_res, (_r))
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#define AFI_WR4(_sc, _r, _v) bus_write_4((_sc)->afi_mem_res, (_r), (_v))
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#define AFI_RD4(_sc, _r) bus_read_4((_sc)->afi_mem_res, (_r))
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static struct {
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bus_size_t axi_start;
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bus_size_t fpci_start;
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bus_size_t size;
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} bars[] = {
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{AFI_AXI_BAR0_START, AFI_FPCI_BAR0, AFI_AXI_BAR0_SZ}, /* BAR 0 */
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{AFI_AXI_BAR1_START, AFI_FPCI_BAR1, AFI_AXI_BAR1_SZ}, /* BAR 1 */
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{AFI_AXI_BAR2_START, AFI_FPCI_BAR2, AFI_AXI_BAR2_SZ}, /* BAR 2 */
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{AFI_AXI_BAR3_START, AFI_FPCI_BAR3, AFI_AXI_BAR3_SZ}, /* BAR 3 */
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{AFI_AXI_BAR4_START, AFI_FPCI_BAR4, AFI_AXI_BAR4_SZ}, /* BAR 4 */
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{AFI_AXI_BAR5_START, AFI_FPCI_BAR5, AFI_AXI_BAR5_SZ}, /* BAR 5 */
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{AFI_AXI_BAR6_START, AFI_FPCI_BAR6, AFI_AXI_BAR6_SZ}, /* BAR 6 */
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{AFI_AXI_BAR7_START, AFI_FPCI_BAR7, AFI_AXI_BAR7_SZ}, /* BAR 7 */
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{AFI_AXI_BAR8_START, AFI_FPCI_BAR8, AFI_AXI_BAR8_SZ}, /* BAR 8 */
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{AFI_MSI_AXI_BAR_ST, AFI_MSI_FPCI_BAR_ST, AFI_MSI_BAR_SZ}, /* MSI 9 */
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};
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/* Compatible devices. */
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static struct ofw_compat_data compat_data[] = {
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{"nvidia,tegra124-pcie", 1},
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{NULL, 0},
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};
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2016-08-19 10:53:17 +00:00
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#define TEGRA_FLAG_MSI_USED 0x0001
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struct tegra_pcib_irqsrc {
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struct intr_irqsrc isrc;
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u_int irq;
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u_int flags;
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};
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2016-03-16 13:01:48 +00:00
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struct tegra_pcib_port {
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int enabled;
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int port_idx; /* chip port index */
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int num_lanes; /* number of lanes */
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bus_size_t afi_pex_ctrl; /* offset of afi_pex_ctrl */
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2016-09-25 23:48:15 +00:00
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phy_t phy; /* port phy */
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2016-03-16 13:01:48 +00:00
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/* Config space properties. */
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bus_addr_t rp_base_addr; /* PA of config window */
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bus_size_t rp_size; /* size of config window */
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bus_space_handle_t cfg_handle; /* handle of config window */
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};
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#define TEGRA_PCIB_MAX_PORTS 3
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2016-08-19 10:53:17 +00:00
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#define TEGRA_PCIB_MAX_MSI AFI_MSI_INTR_IN_REG * AFI_MSI_REGS
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2016-03-16 13:01:48 +00:00
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struct tegra_pcib_softc {
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struct ofw_pci_softc ofw_pci;
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2016-03-16 13:01:48 +00:00
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device_t dev;
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struct mtx mtx;
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struct resource *pads_mem_res;
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struct resource *afi_mem_res;
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struct resource *cfg_mem_res;
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struct resource *irq_res;
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struct resource *msi_irq_res;
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void *intr_cookie;
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void *msi_intr_cookie;
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2016-07-17 14:45:15 +00:00
|
|
|
struct ofw_pci_range mem_range;
|
|
|
|
struct ofw_pci_range pref_mem_range;
|
|
|
|
struct ofw_pci_range io_range;
|
2016-03-16 13:01:48 +00:00
|
|
|
|
|
|
|
clk_t clk_pex;
|
|
|
|
clk_t clk_afi;
|
|
|
|
clk_t clk_pll_e;
|
|
|
|
clk_t clk_cml;
|
2016-07-17 14:45:15 +00:00
|
|
|
hwreset_t hwreset_pex;
|
|
|
|
hwreset_t hwreset_afi;
|
|
|
|
hwreset_t hwreset_pcie_x;
|
2016-03-16 13:01:48 +00:00
|
|
|
regulator_t supply_avddio_pex;
|
|
|
|
regulator_t supply_dvddio_pex;
|
|
|
|
regulator_t supply_avdd_pex_pll;
|
|
|
|
regulator_t supply_hvdd_pex;
|
|
|
|
regulator_t supply_hvdd_pex_pll_e;
|
|
|
|
regulator_t supply_vddio_pex_ctl;
|
|
|
|
regulator_t supply_avdd_pll_erefe;
|
|
|
|
|
2016-08-19 10:53:17 +00:00
|
|
|
vm_offset_t msi_page; /* VA of MSI page */
|
2016-03-16 13:01:48 +00:00
|
|
|
bus_addr_t cfg_base_addr; /* base address of config */
|
|
|
|
bus_size_t cfg_cur_offs; /* currently mapped window */
|
|
|
|
bus_space_handle_t cfg_handle; /* handle of config window */
|
|
|
|
bus_space_tag_t bus_tag; /* tag of config window */
|
|
|
|
int lanes_cfg;
|
|
|
|
int num_ports;
|
|
|
|
struct tegra_pcib_port *ports[TEGRA_PCIB_MAX_PORTS];
|
2016-08-19 10:53:17 +00:00
|
|
|
struct tegra_pcib_irqsrc *isrcs;
|
2016-03-16 13:01:48 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static int
|
|
|
|
tegra_pcib_maxslots(device_t dev)
|
|
|
|
{
|
|
|
|
return (16);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
tegra_pcib_route_interrupt(device_t bus, device_t dev, int pin)
|
|
|
|
{
|
|
|
|
struct tegra_pcib_softc *sc;
|
2016-08-19 10:53:17 +00:00
|
|
|
u_int irq;
|
2016-03-16 13:01:48 +00:00
|
|
|
|
|
|
|
sc = device_get_softc(bus);
|
2016-08-19 10:53:17 +00:00
|
|
|
irq = intr_map_clone_irq(rman_get_start(sc->irq_res));
|
|
|
|
device_printf(bus, "route pin %d for device %d.%d to %u\n",
|
2016-03-16 13:01:48 +00:00
|
|
|
pin, pci_get_slot(dev), pci_get_function(dev),
|
2016-08-19 10:53:17 +00:00
|
|
|
irq);
|
2016-03-16 13:01:48 +00:00
|
|
|
|
2016-08-19 10:53:17 +00:00
|
|
|
return (irq);
|
2016-03-16 13:01:48 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
tegra_pcbib_map_cfg(struct tegra_pcib_softc *sc, u_int bus, u_int slot,
|
|
|
|
u_int func, u_int reg)
|
|
|
|
{
|
|
|
|
bus_size_t offs;
|
|
|
|
int rv;
|
|
|
|
|
|
|
|
offs = sc->cfg_base_addr;
|
|
|
|
offs |= PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | PCI_CFG_FUN(func) |
|
|
|
|
PCI_CFG_EXT_REG(reg);
|
|
|
|
if ((sc->cfg_handle != 0) && (sc->cfg_cur_offs == offs))
|
|
|
|
return (0);
|
|
|
|
if (sc->cfg_handle != 0)
|
|
|
|
bus_space_unmap(sc->bus_tag, sc->cfg_handle, 0x800);
|
|
|
|
|
|
|
|
rv = bus_space_map(sc->bus_tag, offs, 0x800, 0, &sc->cfg_handle);
|
|
|
|
if (rv != 0)
|
|
|
|
device_printf(sc->dev, "Cannot map config space\n");
|
|
|
|
else
|
|
|
|
sc->cfg_cur_offs = offs;
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t
|
|
|
|
tegra_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
|
|
|
|
u_int reg, int bytes)
|
|
|
|
{
|
|
|
|
struct tegra_pcib_softc *sc;
|
|
|
|
bus_space_handle_t hndl;
|
|
|
|
uint32_t off;
|
|
|
|
uint32_t val;
|
|
|
|
int rv, i;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (bus == 0) {
|
|
|
|
if (func != 0)
|
|
|
|
return (0xFFFFFFFF);
|
|
|
|
for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) {
|
|
|
|
if ((sc->ports[i] != NULL) &&
|
|
|
|
(sc->ports[i]->port_idx == slot)) {
|
|
|
|
hndl = sc->ports[i]->cfg_handle;
|
|
|
|
off = reg & 0xFFF;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (i >= TEGRA_PCIB_MAX_PORTS)
|
|
|
|
return (0xFFFFFFFF);
|
|
|
|
} else {
|
|
|
|
rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg);
|
|
|
|
if (rv != 0)
|
|
|
|
return (0xFFFFFFFF);
|
|
|
|
hndl = sc->cfg_handle;
|
|
|
|
off = PCI_CFG_BASE_REG(reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
val = bus_space_read_4(sc->bus_tag, hndl, off & ~3);
|
|
|
|
switch (bytes) {
|
|
|
|
case 4:
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
if (off & 3)
|
|
|
|
val >>= 16;
|
|
|
|
val &= 0xffff;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
val >>= ((off & 3) << 3);
|
|
|
|
val &= 0xff;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
tegra_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
|
|
|
|
u_int reg, uint32_t val, int bytes)
|
|
|
|
{
|
|
|
|
struct tegra_pcib_softc *sc;
|
|
|
|
bus_space_handle_t hndl;
|
|
|
|
uint32_t off;
|
|
|
|
uint32_t val2;
|
|
|
|
int rv, i;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (bus == 0) {
|
|
|
|
if (func != 0)
|
|
|
|
return;
|
|
|
|
for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) {
|
|
|
|
if ((sc->ports[i] != NULL) &&
|
|
|
|
(sc->ports[i]->port_idx == slot)) {
|
|
|
|
hndl = sc->ports[i]->cfg_handle;
|
|
|
|
off = reg & 0xFFF;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (i >= TEGRA_PCIB_MAX_PORTS)
|
|
|
|
return;
|
|
|
|
} else {
|
|
|
|
rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg);
|
|
|
|
if (rv != 0)
|
|
|
|
return;
|
|
|
|
hndl = sc->cfg_handle;
|
|
|
|
off = PCI_CFG_BASE_REG(reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (bytes) {
|
|
|
|
case 4:
|
|
|
|
bus_space_write_4(sc->bus_tag, hndl, off, val);
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3);
|
|
|
|
val2 &= ~(0xffff << ((off & 3) << 3));
|
|
|
|
val2 |= ((val & 0xffff) << ((off & 3) << 3));
|
|
|
|
bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2);
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3);
|
|
|
|
val2 &= ~(0xff << ((off & 3) << 3));
|
|
|
|
val2 |= ((val & 0xff) << ((off & 3) << 3));
|
|
|
|
bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tegra_pci_intr(void *arg)
|
|
|
|
{
|
|
|
|
struct tegra_pcib_softc *sc = arg;
|
|
|
|
uint32_t code, signature;
|
|
|
|
|
|
|
|
code = bus_read_4(sc->afi_mem_res, AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
|
|
|
|
signature = bus_read_4(sc->afi_mem_res, AFI_INTR_SIGNATURE);
|
|
|
|
bus_write_4(sc->afi_mem_res, AFI_INTR_CODE, 0);
|
|
|
|
if (code == AFI_INTR_CODE_INT_CODE_SM_MSG)
|
|
|
|
return(FILTER_STRAY);
|
|
|
|
|
|
|
|
printf("tegra_pci_intr: code %x sig %x\n", code, signature);
|
|
|
|
return (FILTER_HANDLED);
|
|
|
|
}
|
|
|
|
|
2016-08-19 10:53:17 +00:00
|
|
|
/* -----------------------------------------------------------------------
|
|
|
|
*
|
|
|
|
* PCI MSI interface
|
|
|
|
*/
|
|
|
|
static int
|
|
|
|
tegra_pcib_alloc_msi(device_t pci, device_t child, int count, int maxcount,
|
|
|
|
int *irqs)
|
|
|
|
{
|
|
|
|
phandle_t msi_parent;
|
|
|
|
|
|
|
|
/* XXXX ofw_bus_msimap() don't works for Tegra DT.
|
|
|
|
ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent,
|
|
|
|
NULL);
|
|
|
|
*/
|
|
|
|
msi_parent = OF_xref_from_node(ofw_bus_get_node(pci));
|
|
|
|
return (intr_alloc_msi(pci, child, msi_parent, count, maxcount,
|
|
|
|
irqs));
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
tegra_pcib_release_msi(device_t pci, device_t child, int count, int *irqs)
|
|
|
|
{
|
|
|
|
phandle_t msi_parent;
|
|
|
|
|
|
|
|
/* XXXX ofw_bus_msimap() don't works for Tegra DT.
|
|
|
|
ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent,
|
|
|
|
NULL);
|
|
|
|
*/
|
|
|
|
msi_parent = OF_xref_from_node(ofw_bus_get_node(pci));
|
|
|
|
return (intr_release_msi(pci, child, msi_parent, count, irqs));
|
|
|
|
}
|
|
|
|
|
2016-03-16 13:01:48 +00:00
|
|
|
static int
|
2016-08-19 10:53:17 +00:00
|
|
|
tegra_pcib_map_msi(device_t pci, device_t child, int irq, uint64_t *addr,
|
2016-03-16 13:01:48 +00:00
|
|
|
uint32_t *data)
|
|
|
|
{
|
2016-08-19 10:53:17 +00:00
|
|
|
phandle_t msi_parent;
|
|
|
|
|
|
|
|
/* XXXX ofw_bus_msimap() don't works for Tegra DT.
|
|
|
|
ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent,
|
|
|
|
NULL);
|
|
|
|
*/
|
|
|
|
msi_parent = OF_xref_from_node(ofw_bus_get_node(pci));
|
|
|
|
return (intr_map_msi(pci, child, msi_parent, irq, addr, data));
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef TEGRA_PCIB_MSI_ENABLE
|
|
|
|
|
|
|
|
/* --------------------------------------------------------------------------
|
|
|
|
*
|
|
|
|
* Interrupts
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
|
|
|
|
static inline void
|
|
|
|
tegra_pcib_isrc_mask(struct tegra_pcib_softc *sc,
|
|
|
|
struct tegra_pcib_irqsrc *tgi, uint32_t val)
|
|
|
|
{
|
|
|
|
uint32_t reg;
|
|
|
|
int offs, bit;
|
|
|
|
|
|
|
|
offs = tgi->irq / AFI_MSI_INTR_IN_REG;
|
|
|
|
bit = 1 << (tgi->irq % AFI_MSI_INTR_IN_REG);
|
|
|
|
|
|
|
|
if (val != 0)
|
|
|
|
AFI_WR4(sc, AFI_MSI_VEC(offs), bit);
|
|
|
|
reg = AFI_RD4(sc, AFI_MSI_EN_VEC(offs));
|
|
|
|
if (val != 0)
|
|
|
|
reg |= bit;
|
|
|
|
else
|
|
|
|
reg &= ~bit;
|
|
|
|
AFI_WR4(sc, AFI_MSI_EN_VEC(offs), reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
tegra_pcib_msi_intr(void *arg)
|
|
|
|
{
|
|
|
|
u_int irq, i, bit, reg;
|
2016-03-16 13:01:48 +00:00
|
|
|
struct tegra_pcib_softc *sc;
|
2016-08-19 10:53:17 +00:00
|
|
|
struct trapframe *tf;
|
|
|
|
struct tegra_pcib_irqsrc *tgi;
|
|
|
|
|
|
|
|
sc = (struct tegra_pcib_softc *)arg;
|
|
|
|
tf = curthread->td_intr_frame;
|
|
|
|
|
|
|
|
for (i = 0; i < AFI_MSI_REGS; i++) {
|
|
|
|
reg = AFI_RD4(sc, AFI_MSI_VEC(i));
|
|
|
|
/* Handle one vector. */
|
|
|
|
while (reg != 0) {
|
|
|
|
bit = ffs(reg) - 1;
|
|
|
|
/* Send EOI */
|
|
|
|
AFI_WR4(sc, AFI_MSI_VEC(i), 1 << bit);
|
|
|
|
irq = i * AFI_MSI_INTR_IN_REG + bit;
|
|
|
|
tgi = &sc->isrcs[irq];
|
|
|
|
if (intr_isrc_dispatch(&tgi->isrc, tf) != 0) {
|
|
|
|
/* Disable stray. */
|
|
|
|
tegra_pcib_isrc_mask(sc, tgi, 0);
|
|
|
|
device_printf(sc->dev,
|
|
|
|
"Stray irq %u disabled\n", irq);
|
|
|
|
}
|
|
|
|
reg = AFI_RD4(sc, AFI_MSI_VEC(i));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return (FILTER_HANDLED);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
tegra_pcib_msi_attach(struct tegra_pcib_softc *sc)
|
|
|
|
{
|
|
|
|
int error;
|
|
|
|
uint32_t irq;
|
|
|
|
const char *name;
|
|
|
|
|
|
|
|
sc->isrcs = malloc(sizeof(*sc->isrcs) * TEGRA_PCIB_MAX_MSI, M_DEVBUF,
|
|
|
|
M_WAITOK | M_ZERO);
|
|
|
|
|
|
|
|
name = device_get_nameunit(sc->dev);
|
|
|
|
for (irq = 0; irq < TEGRA_PCIB_MAX_MSI; irq++) {
|
|
|
|
sc->isrcs[irq].irq = irq;
|
|
|
|
error = intr_isrc_register(&sc->isrcs[irq].isrc,
|
|
|
|
sc->dev, 0, "%s,%u", name, irq);
|
|
|
|
if (error != 0)
|
|
|
|
return (error); /* XXX deregister ISRCs */
|
|
|
|
}
|
|
|
|
if (intr_msi_register(sc->dev,
|
|
|
|
OF_xref_from_node(ofw_bus_get_node(sc->dev))) != 0)
|
|
|
|
return (ENXIO);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
tegra_pcib_msi_detach(struct tegra_pcib_softc *sc)
|
|
|
|
{
|
|
|
|
|
|
|
|
/*
|
|
|
|
* There has not been established any procedure yet
|
|
|
|
* how to detach PIC from living system correctly.
|
|
|
|
*/
|
|
|
|
device_printf(sc->dev, "%s: not implemented yet\n", __func__);
|
|
|
|
return (EBUSY);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
tegra_pcib_msi_disable_intr(device_t dev, struct intr_irqsrc *isrc)
|
|
|
|
{
|
|
|
|
struct tegra_pcib_softc *sc;
|
|
|
|
struct tegra_pcib_irqsrc *tgi;
|
2016-03-16 13:01:48 +00:00
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
2016-08-19 10:53:17 +00:00
|
|
|
tgi = (struct tegra_pcib_irqsrc *)isrc;
|
|
|
|
tegra_pcib_isrc_mask(sc, tgi, 0);
|
|
|
|
}
|
2016-03-16 13:01:48 +00:00
|
|
|
|
2016-08-19 10:53:17 +00:00
|
|
|
static void
|
|
|
|
tegra_pcib_msi_enable_intr(device_t dev, struct intr_irqsrc *isrc)
|
|
|
|
{
|
|
|
|
struct tegra_pcib_softc *sc;
|
|
|
|
struct tegra_pcib_irqsrc *tgi;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
tgi = (struct tegra_pcib_irqsrc *)isrc;
|
|
|
|
tegra_pcib_isrc_mask(sc, tgi, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* MSI interrupts are edge trigered -> do nothing */
|
|
|
|
static void
|
|
|
|
tegra_pcib_msi_post_filter(device_t dev, struct intr_irqsrc *isrc)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
tegra_pcib_msi_post_ithread(device_t dev, struct intr_irqsrc *isrc)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
tegra_pcib_msi_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
tegra_pcib_msi_setup_intr(device_t dev, struct intr_irqsrc *isrc,
|
|
|
|
struct resource *res, struct intr_map_data *data)
|
|
|
|
{
|
|
|
|
struct tegra_pcib_softc *sc;
|
|
|
|
struct tegra_pcib_irqsrc *tgi;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
tgi = (struct tegra_pcib_irqsrc *)isrc;
|
|
|
|
|
|
|
|
if (data == NULL || data->type != INTR_MAP_DATA_MSI)
|
|
|
|
return (ENOTSUP);
|
2016-03-16 13:01:48 +00:00
|
|
|
|
2016-08-19 10:53:17 +00:00
|
|
|
if (isrc->isrc_handlers == 0)
|
|
|
|
tegra_pcib_msi_enable_intr(dev, isrc);
|
2016-03-16 13:01:48 +00:00
|
|
|
|
2016-08-19 10:53:17 +00:00
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
tegra_pcib_msi_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
|
|
|
|
struct resource *res, struct intr_map_data *data)
|
|
|
|
{
|
|
|
|
struct tegra_pcib_softc *sc;
|
|
|
|
struct tegra_pcib_irqsrc *tgi;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
tgi = (struct tegra_pcib_irqsrc *)isrc;
|
2016-03-16 13:01:48 +00:00
|
|
|
|
2016-08-19 10:53:17 +00:00
|
|
|
if (isrc->isrc_handlers == 0)
|
|
|
|
tegra_pcib_isrc_mask(sc, tgi, 0);
|
2016-03-16 13:01:48 +00:00
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
2016-08-19 10:53:17 +00:00
|
|
|
|
2016-03-16 13:01:48 +00:00
|
|
|
static int
|
2016-08-19 10:53:17 +00:00
|
|
|
tegra_pcib_msi_alloc_msi(device_t dev, device_t child, int count, int maxcount,
|
|
|
|
device_t *pic, struct intr_irqsrc **srcs)
|
2016-03-16 13:01:48 +00:00
|
|
|
{
|
|
|
|
struct tegra_pcib_softc *sc;
|
2016-08-19 10:53:17 +00:00
|
|
|
int i, irq, end_irq;
|
|
|
|
bool found;
|
2016-03-16 13:01:48 +00:00
|
|
|
|
2016-08-19 10:53:17 +00:00
|
|
|
KASSERT(powerof2(count), ("%s: bad count", __func__));
|
|
|
|
KASSERT(powerof2(maxcount), ("%s: bad maxcount", __func__));
|
2016-03-16 13:01:48 +00:00
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
mtx_lock(&sc->mtx);
|
|
|
|
|
2016-08-19 10:53:17 +00:00
|
|
|
found = false;
|
2016-10-09 04:29:42 +00:00
|
|
|
for (irq = 0; (irq + count - 1) < TEGRA_PCIB_MAX_MSI; irq++) {
|
2016-08-19 10:53:17 +00:00
|
|
|
/* Start on an aligned interrupt */
|
|
|
|
if ((irq & (maxcount - 1)) != 0)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* Assume we found a valid range until shown otherwise */
|
|
|
|
found = true;
|
|
|
|
|
|
|
|
/* Check this range is valid */
|
2016-10-09 04:29:42 +00:00
|
|
|
for (end_irq = irq; end_irq < irq + count; end_irq++) {
|
2016-08-19 10:53:17 +00:00
|
|
|
/* This is already used */
|
2016-10-09 04:29:42 +00:00
|
|
|
if ((sc->isrcs[end_irq].flags & TEGRA_FLAG_MSI_USED) ==
|
2016-08-19 10:53:17 +00:00
|
|
|
TEGRA_FLAG_MSI_USED) {
|
|
|
|
found = false;
|
2016-03-16 13:01:48 +00:00
|
|
|
break;
|
2016-08-19 10:53:17 +00:00
|
|
|
}
|
2016-03-16 13:01:48 +00:00
|
|
|
}
|
2016-10-09 04:29:42 +00:00
|
|
|
|
|
|
|
if (found)
|
|
|
|
break;
|
2016-03-16 13:01:48 +00:00
|
|
|
}
|
|
|
|
|
2016-08-19 10:53:17 +00:00
|
|
|
/* Not enough interrupts were found */
|
|
|
|
if (!found || irq == (TEGRA_PCIB_MAX_MSI - 1)) {
|
2016-03-16 13:01:48 +00:00
|
|
|
mtx_unlock(&sc->mtx);
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
|
|
|
|
2016-08-19 10:53:17 +00:00
|
|
|
for (i = 0; i < count; i++) {
|
|
|
|
/* Mark the interrupt as used */
|
|
|
|
sc->isrcs[irq + i].flags |= TEGRA_FLAG_MSI_USED;
|
2016-03-16 13:01:48 +00:00
|
|
|
|
2016-08-19 10:53:17 +00:00
|
|
|
}
|
2016-03-16 13:01:48 +00:00
|
|
|
mtx_unlock(&sc->mtx);
|
2016-08-19 10:53:17 +00:00
|
|
|
|
|
|
|
for (i = 0; i < count; i++)
|
|
|
|
srcs[i] = (struct intr_irqsrc *)&sc->isrcs[irq + i];
|
|
|
|
*pic = device_get_parent(dev);
|
2016-03-16 13:01:48 +00:00
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2016-08-19 10:53:17 +00:00
|
|
|
tegra_pcib_msi_release_msi(device_t dev, device_t child, int count,
|
|
|
|
struct intr_irqsrc **isrc)
|
2016-03-16 13:01:48 +00:00
|
|
|
{
|
|
|
|
struct tegra_pcib_softc *sc;
|
2016-08-19 10:53:17 +00:00
|
|
|
struct tegra_pcib_irqsrc *ti;
|
|
|
|
int i;
|
2016-03-16 13:01:48 +00:00
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
mtx_lock(&sc->mtx);
|
2016-08-19 10:53:17 +00:00
|
|
|
for (i = 0; i < count; i++) {
|
2016-10-09 04:36:40 +00:00
|
|
|
ti = (struct tegra_pcib_irqsrc *)isrc[i];
|
2016-03-16 13:01:48 +00:00
|
|
|
|
2016-08-19 10:53:17 +00:00
|
|
|
KASSERT((ti->flags & TEGRA_FLAG_MSI_USED) == TEGRA_FLAG_MSI_USED,
|
|
|
|
("%s: Trying to release an unused MSI-X interrupt",
|
|
|
|
__func__));
|
2016-03-16 13:01:48 +00:00
|
|
|
|
2016-08-19 10:53:17 +00:00
|
|
|
ti->flags &= ~TEGRA_FLAG_MSI_USED;
|
|
|
|
}
|
2016-10-09 04:36:40 +00:00
|
|
|
mtx_unlock(&sc->mtx);
|
2016-08-19 10:53:17 +00:00
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
tegra_pcib_msi_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc,
|
|
|
|
uint64_t *addr, uint32_t *data)
|
|
|
|
{
|
|
|
|
struct tegra_pcib_softc *sc = device_get_softc(dev);
|
|
|
|
struct tegra_pcib_irqsrc *ti = (struct tegra_pcib_irqsrc *)isrc;
|
|
|
|
|
|
|
|
*addr = vtophys(sc->msi_page);
|
|
|
|
*data = ti->irq;
|
2016-03-16 13:01:48 +00:00
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2016-08-19 10:53:17 +00:00
|
|
|
/* ------------------------------------------------------------------- */
|
2016-03-16 13:01:48 +00:00
|
|
|
static bus_size_t
|
|
|
|
tegra_pcib_pex_ctrl(struct tegra_pcib_softc *sc, int port)
|
|
|
|
{
|
|
|
|
if (port >= TEGRA_PCIB_MAX_PORTS)
|
|
|
|
panic("invalid port number: %d\n", port);
|
|
|
|
|
|
|
|
if (port == 0)
|
|
|
|
return (AFI_PEX0_CTRL);
|
|
|
|
else if (port == 1)
|
|
|
|
return (AFI_PEX1_CTRL);
|
|
|
|
else if (port == 2)
|
|
|
|
return (AFI_PEX2_CTRL);
|
|
|
|
else
|
|
|
|
panic("invalid port number: %d\n", port);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
tegra_pcib_enable_fdt_resources(struct tegra_pcib_softc *sc)
|
|
|
|
{
|
|
|
|
int rv;
|
|
|
|
|
|
|
|
rv = hwreset_assert(sc->hwreset_pcie_x);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev, "Cannot assert 'pcie_x' reset\n");
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
rv = hwreset_assert(sc->hwreset_afi);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev, "Cannot assert 'afi' reset\n");
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
rv = hwreset_assert(sc->hwreset_pex);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev, "Cannot assert 'pex' reset\n");
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
|
|
|
|
tegra_powergate_power_off(TEGRA_POWERGATE_PCX);
|
|
|
|
|
|
|
|
/* Power supplies. */
|
|
|
|
rv = regulator_enable(sc->supply_avddio_pex);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev,
|
|
|
|
"Cannot enable 'avddio_pex' regulator\n");
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
rv = regulator_enable(sc->supply_dvddio_pex);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev,
|
|
|
|
"Cannot enable 'dvddio_pex' regulator\n");
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
rv = regulator_enable(sc->supply_avdd_pex_pll);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev,
|
|
|
|
"Cannot enable 'avdd-pex-pll' regulator\n");
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
rv = regulator_enable(sc->supply_hvdd_pex);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev,
|
|
|
|
"Cannot enable 'hvdd-pex-supply' regulator\n");
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
rv = regulator_enable(sc->supply_hvdd_pex_pll_e);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev,
|
|
|
|
"Cannot enable 'hvdd-pex-pll-e-supply' regulator\n");
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
rv = regulator_enable(sc->supply_vddio_pex_ctl);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev,
|
|
|
|
"Cannot enable 'vddio-pex-ctl' regulator\n");
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
rv = regulator_enable(sc->supply_avdd_pll_erefe);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev,
|
|
|
|
"Cannot enable 'avdd-pll-erefe-supply' regulator\n");
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
|
|
|
|
rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCX,
|
|
|
|
sc->clk_pex, sc->hwreset_pex);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev, "Cannot enable 'PCX' powergate\n");
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
|
|
|
|
rv = hwreset_deassert(sc->hwreset_afi);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev, "Cannot unreset 'afi' reset\n");
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
|
|
|
|
rv = clk_enable(sc->clk_afi);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev, "Cannot enable 'afi' clock\n");
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
rv = clk_enable(sc->clk_cml);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev, "Cannot enable 'cml' clock\n");
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
rv = clk_enable(sc->clk_pll_e);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev, "Cannot enable 'pll_e' clock\n");
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct tegra_pcib_port *
|
|
|
|
tegra_pcib_parse_port(struct tegra_pcib_softc *sc, phandle_t node)
|
|
|
|
{
|
|
|
|
struct tegra_pcib_port *port;
|
|
|
|
uint32_t tmp[5];
|
|
|
|
char tmpstr[6];
|
|
|
|
int rv;
|
|
|
|
|
|
|
|
port = malloc(sizeof(struct tegra_pcib_port), M_DEVBUF, M_WAITOK);
|
|
|
|
|
|
|
|
rv = OF_getprop(node, "status", tmpstr, sizeof(tmpstr));
|
|
|
|
if (rv <= 0 || strcmp(tmpstr, "okay") == 0 ||
|
|
|
|
strcmp(tmpstr, "ok") == 0)
|
|
|
|
port->enabled = 1;
|
|
|
|
else
|
|
|
|
port->enabled = 0;
|
|
|
|
|
|
|
|
rv = OF_getencprop(node, "assigned-addresses", tmp, sizeof(tmp));
|
|
|
|
if (rv != sizeof(tmp)) {
|
|
|
|
device_printf(sc->dev, "Cannot parse assigned-address: %d\n",
|
|
|
|
rv);
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
port->rp_base_addr = tmp[2];
|
|
|
|
port->rp_size = tmp[4];
|
|
|
|
port->port_idx = OFW_PCI_PHYS_HI_DEVICE(tmp[0]) - 1;
|
|
|
|
if (port->port_idx >= TEGRA_PCIB_MAX_PORTS) {
|
|
|
|
device_printf(sc->dev, "Invalid port index: %d\n",
|
|
|
|
port->port_idx);
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
/* XXX - TODO:
|
|
|
|
* Implement proper function for parsing pci "reg" property:
|
|
|
|
* - it have PCI bus format
|
|
|
|
* - its relative to matching "assigned-addresses"
|
|
|
|
*/
|
|
|
|
rv = OF_getencprop(node, "reg", tmp, sizeof(tmp));
|
|
|
|
if (rv != sizeof(tmp)) {
|
|
|
|
device_printf(sc->dev, "Cannot parse reg: %d\n", rv);
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
port->rp_base_addr += tmp[2];
|
|
|
|
|
|
|
|
rv = OF_getencprop(node, "nvidia,num-lanes", &port->num_lanes,
|
|
|
|
sizeof(port->num_lanes));
|
|
|
|
if (rv != sizeof(port->num_lanes)) {
|
|
|
|
device_printf(sc->dev, "Cannot parse nvidia,num-lanes: %d\n",
|
|
|
|
rv);
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
if (port->num_lanes > 4) {
|
|
|
|
device_printf(sc->dev, "Invalid nvidia,num-lanes: %d\n",
|
|
|
|
port->num_lanes);
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
port->afi_pex_ctrl = tegra_pcib_pex_ctrl(sc, port->port_idx);
|
|
|
|
sc->lanes_cfg |= port->num_lanes << (4 * port->port_idx);
|
|
|
|
|
2016-09-25 23:48:15 +00:00
|
|
|
/* Phy. */
|
|
|
|
rv = phy_get_by_ofw_name(sc->dev, node, "pcie-0", &port->phy);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev,
|
|
|
|
"Cannot get 'pcie-0' phy for port %d\n",
|
|
|
|
port->port_idx);
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
2016-03-16 13:01:48 +00:00
|
|
|
return (port);
|
|
|
|
fail:
|
|
|
|
free(port, M_DEVBUF);
|
|
|
|
return (NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
tegra_pcib_parse_fdt_resources(struct tegra_pcib_softc *sc, phandle_t node)
|
|
|
|
{
|
|
|
|
phandle_t child;
|
|
|
|
struct tegra_pcib_port *port;
|
|
|
|
int rv;
|
|
|
|
|
|
|
|
/* Power supplies. */
|
2016-07-10 18:28:15 +00:00
|
|
|
rv = regulator_get_by_ofw_property(sc->dev, 0, "avddio-pex-supply",
|
2016-03-16 13:01:48 +00:00
|
|
|
&sc->supply_avddio_pex);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev,
|
|
|
|
"Cannot get 'avddio-pex' regulator\n");
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
2016-07-10 18:28:15 +00:00
|
|
|
rv = regulator_get_by_ofw_property(sc->dev, 0, "dvddio-pex-supply",
|
2016-03-16 13:01:48 +00:00
|
|
|
&sc->supply_dvddio_pex);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev,
|
|
|
|
"Cannot get 'dvddio-pex' regulator\n");
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
2016-07-10 18:28:15 +00:00
|
|
|
rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pex-pll-supply",
|
2016-03-16 13:01:48 +00:00
|
|
|
&sc->supply_avdd_pex_pll);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev,
|
|
|
|
"Cannot get 'avdd-pex-pll' regulator\n");
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
2016-07-10 18:28:15 +00:00
|
|
|
rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-pex-supply",
|
2016-03-16 13:01:48 +00:00
|
|
|
&sc->supply_hvdd_pex);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev,
|
|
|
|
"Cannot get 'hvdd-pex' regulator\n");
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
2016-07-10 18:28:15 +00:00
|
|
|
rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-pex-pll-e-supply",
|
2016-03-16 13:01:48 +00:00
|
|
|
&sc->supply_hvdd_pex_pll_e);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev,
|
|
|
|
"Cannot get 'hvdd-pex-pll-e' regulator\n");
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
2016-07-10 18:28:15 +00:00
|
|
|
rv = regulator_get_by_ofw_property(sc->dev, 0, "vddio-pex-ctl-supply",
|
2016-03-16 13:01:48 +00:00
|
|
|
&sc->supply_vddio_pex_ctl);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev,
|
|
|
|
"Cannot get 'vddio-pex-ctl' regulator\n");
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
2016-07-10 18:28:15 +00:00
|
|
|
rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pll-erefe-supply",
|
2016-03-16 13:01:48 +00:00
|
|
|
&sc->supply_avdd_pll_erefe);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev,
|
|
|
|
"Cannot get 'avdd-pll-erefe' regulator\n");
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Resets. */
|
2016-07-10 18:28:15 +00:00
|
|
|
rv = hwreset_get_by_ofw_name(sc->dev, 0, "pex", &sc->hwreset_pex);
|
2016-03-16 13:01:48 +00:00
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev, "Cannot get 'pex' reset\n");
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
2016-07-10 18:28:15 +00:00
|
|
|
rv = hwreset_get_by_ofw_name(sc->dev, 0, "afi", &sc->hwreset_afi);
|
2016-03-16 13:01:48 +00:00
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev, "Cannot get 'afi' reset\n");
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
2016-07-10 18:28:15 +00:00
|
|
|
rv = hwreset_get_by_ofw_name(sc->dev, 0, "pcie_x", &sc->hwreset_pcie_x);
|
2016-03-16 13:01:48 +00:00
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev, "Cannot get 'pcie_x' reset\n");
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Clocks. */
|
2016-07-10 18:28:15 +00:00
|
|
|
rv = clk_get_by_ofw_name(sc->dev, 0, "pex", &sc->clk_pex);
|
2016-03-16 13:01:48 +00:00
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev, "Cannot get 'pex' clock\n");
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
2016-07-10 18:28:15 +00:00
|
|
|
rv = clk_get_by_ofw_name(sc->dev, 0, "afi", &sc->clk_afi);
|
2016-03-16 13:01:48 +00:00
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev, "Cannot get 'afi' clock\n");
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
2016-07-10 18:28:15 +00:00
|
|
|
rv = clk_get_by_ofw_name(sc->dev, 0, "pll_e", &sc->clk_pll_e);
|
2016-03-16 13:01:48 +00:00
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev, "Cannot get 'pll_e' clock\n");
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
2016-07-10 18:28:15 +00:00
|
|
|
rv = clk_get_by_ofw_name(sc->dev, 0, "cml", &sc->clk_cml);
|
2016-03-16 13:01:48 +00:00
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev, "Cannot get 'cml' clock\n");
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Ports */
|
|
|
|
sc->num_ports = 0;
|
|
|
|
for (child = OF_child(node); child != 0; child = OF_peer(child)) {
|
|
|
|
port = tegra_pcib_parse_port(sc, child);
|
|
|
|
if (port == NULL) {
|
|
|
|
device_printf(sc->dev, "Cannot parse PCIe port node\n");
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
|
|
|
sc->ports[sc->num_ports++] = port;
|
|
|
|
}
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
tegra_pcib_decode_ranges(struct tegra_pcib_softc *sc,
|
2016-07-17 14:45:15 +00:00
|
|
|
struct ofw_pci_range *ranges, int nranges)
|
2016-03-16 13:01:48 +00:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 2; i < nranges; i++) {
|
2016-07-17 14:45:15 +00:00
|
|
|
if ((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) ==
|
|
|
|
OFW_PCI_PHYS_HI_SPACE_IO) {
|
2016-03-16 13:01:48 +00:00
|
|
|
if (sc->io_range.size != 0) {
|
|
|
|
device_printf(sc->dev,
|
|
|
|
"Duplicated IO range found in DT\n");
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
|
|
|
sc->io_range = ranges[i];
|
|
|
|
}
|
2016-07-17 14:45:15 +00:00
|
|
|
if (((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) ==
|
|
|
|
OFW_PCI_PHYS_HI_SPACE_MEM32)) {
|
|
|
|
if (ranges[i].pci_hi & OFW_PCI_PHYS_HI_PREFETCHABLE) {
|
|
|
|
if (sc->pref_mem_range.size != 0) {
|
|
|
|
device_printf(sc->dev,
|
|
|
|
"Duplicated memory range found "
|
|
|
|
"in DT\n");
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
|
|
|
sc->pref_mem_range = ranges[i];
|
|
|
|
} else {
|
|
|
|
if (sc->mem_range.size != 0) {
|
|
|
|
device_printf(sc->dev,
|
|
|
|
"Duplicated memory range found "
|
|
|
|
"in DT\n");
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
|
|
|
sc->mem_range = ranges[i];
|
2016-03-16 13:01:48 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if ((sc->io_range.size == 0) || (sc->mem_range.size == 0)
|
|
|
|
|| (sc->pref_mem_range.size == 0)) {
|
|
|
|
device_printf(sc->dev,
|
|
|
|
" Not all required ranges are found in DT\n");
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Hardware config.
|
|
|
|
*/
|
|
|
|
static int
|
|
|
|
tegra_pcib_wait_for_link(struct tegra_pcib_softc *sc,
|
|
|
|
struct tegra_pcib_port *port)
|
|
|
|
{
|
|
|
|
uint32_t reg;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
|
|
/* Setup link detection. */
|
|
|
|
reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0,
|
|
|
|
RP_PRIV_MISC, 4);
|
|
|
|
reg &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;
|
|
|
|
reg |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
|
|
|
|
tegra_pcib_write_config(sc->dev, 0, port->port_idx, 0,
|
|
|
|
RP_PRIV_MISC, reg, 4);
|
|
|
|
|
|
|
|
for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) {
|
|
|
|
reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0,
|
|
|
|
RP_VEND_XP, 4);
|
|
|
|
if (reg & RP_VEND_XP_DL_UP)
|
|
|
|
break;
|
2016-10-04 09:14:48 +00:00
|
|
|
DELAY(1);
|
2016-03-16 13:01:48 +00:00
|
|
|
|
|
|
|
}
|
|
|
|
if (i <= 0)
|
|
|
|
return (ETIMEDOUT);
|
|
|
|
|
|
|
|
for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) {
|
|
|
|
reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0,
|
|
|
|
RP_LINK_CONTROL_STATUS, 4);
|
|
|
|
if (reg & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
|
|
|
|
break;
|
|
|
|
|
2016-10-04 09:14:48 +00:00
|
|
|
DELAY(1);
|
2016-03-16 13:01:48 +00:00
|
|
|
}
|
|
|
|
if (i <= 0)
|
|
|
|
return (ETIMEDOUT);
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
tegra_pcib_port_enable(struct tegra_pcib_softc *sc, int port_num)
|
|
|
|
{
|
|
|
|
struct tegra_pcib_port *port;
|
|
|
|
uint32_t reg;
|
|
|
|
int rv;
|
|
|
|
|
|
|
|
port = sc->ports[port_num];
|
|
|
|
|
|
|
|
/* Put port to reset. */
|
|
|
|
reg = AFI_RD4(sc, port->afi_pex_ctrl);
|
|
|
|
reg &= ~AFI_PEX_CTRL_RST_L;
|
|
|
|
AFI_WR4(sc, port->afi_pex_ctrl, reg);
|
|
|
|
AFI_RD4(sc, port->afi_pex_ctrl);
|
|
|
|
DELAY(10);
|
|
|
|
|
|
|
|
/* Enable clocks. */
|
|
|
|
reg |= AFI_PEX_CTRL_REFCLK_EN;
|
|
|
|
reg |= AFI_PEX_CTRL_CLKREQ_EN;
|
|
|
|
reg |= AFI_PEX_CTRL_OVERRIDE_EN;
|
|
|
|
AFI_WR4(sc, port->afi_pex_ctrl, reg);
|
|
|
|
AFI_RD4(sc, port->afi_pex_ctrl);
|
|
|
|
DELAY(100);
|
|
|
|
|
|
|
|
/* Release reset. */
|
|
|
|
reg |= AFI_PEX_CTRL_RST_L;
|
|
|
|
AFI_WR4(sc, port->afi_pex_ctrl, reg);
|
|
|
|
|
|
|
|
rv = tegra_pcib_wait_for_link(sc, port);
|
|
|
|
if (bootverbose)
|
|
|
|
device_printf(sc->dev, " port %d (%d lane%s): Link is %s\n",
|
|
|
|
port->port_idx, port->num_lanes,
|
|
|
|
port->num_lanes > 1 ? "s": "",
|
|
|
|
rv == 0 ? "up": "down");
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
tegra_pcib_port_disable(struct tegra_pcib_softc *sc, uint32_t port_num)
|
|
|
|
{
|
|
|
|
struct tegra_pcib_port *port;
|
|
|
|
uint32_t reg;
|
|
|
|
|
|
|
|
port = sc->ports[port_num];
|
|
|
|
|
|
|
|
/* Put port to reset. */
|
|
|
|
reg = AFI_RD4(sc, port->afi_pex_ctrl);
|
|
|
|
reg &= ~AFI_PEX_CTRL_RST_L;
|
|
|
|
AFI_WR4(sc, port->afi_pex_ctrl, reg);
|
|
|
|
AFI_RD4(sc, port->afi_pex_ctrl);
|
|
|
|
DELAY(10);
|
|
|
|
|
|
|
|
/* Disable clocks. */
|
|
|
|
reg &= ~AFI_PEX_CTRL_CLKREQ_EN;
|
|
|
|
reg &= ~AFI_PEX_CTRL_REFCLK_EN;
|
|
|
|
AFI_WR4(sc, port->afi_pex_ctrl, reg);
|
|
|
|
|
|
|
|
if (bootverbose)
|
|
|
|
device_printf(sc->dev, " port %d (%d lane%s): Disabled\n",
|
|
|
|
port->port_idx, port->num_lanes,
|
|
|
|
port->num_lanes > 1 ? "s": "");
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
tegra_pcib_set_bar(struct tegra_pcib_softc *sc, int bar, uint32_t axi,
|
|
|
|
uint64_t fpci, uint32_t size, int is_memory)
|
|
|
|
{
|
|
|
|
uint32_t fpci_reg;
|
|
|
|
uint32_t axi_reg;
|
|
|
|
uint32_t size_reg;
|
|
|
|
|
|
|
|
axi_reg = axi & ~0xFFF;
|
|
|
|
size_reg = size >> 12;
|
|
|
|
fpci_reg = (uint32_t)(fpci >> 8) & ~0xF;
|
|
|
|
fpci_reg |= is_memory ? 0x1 : 0x0;
|
|
|
|
AFI_WR4(sc, bars[bar].axi_start, axi_reg);
|
|
|
|
AFI_WR4(sc, bars[bar].size, size_reg);
|
|
|
|
AFI_WR4(sc, bars[bar].fpci_start, fpci_reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2016-07-09 13:27:14 +00:00
|
|
|
tegra_pcib_enable(struct tegra_pcib_softc *sc)
|
2016-03-16 13:01:48 +00:00
|
|
|
{
|
|
|
|
int rv;
|
|
|
|
int i;
|
|
|
|
uint32_t reg;
|
|
|
|
|
|
|
|
rv = tegra_pcib_enable_fdt_resources(sc);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev, "Cannot enable FDT resources\n");
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
/* Enable PLLE control. */
|
|
|
|
reg = AFI_RD4(sc, AFI_PLLE_CONTROL);
|
|
|
|
reg &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
|
|
|
|
reg |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
|
|
|
|
AFI_WR4(sc, AFI_PLLE_CONTROL, reg);
|
|
|
|
|
|
|
|
/* Set bias pad. */
|
|
|
|
AFI_WR4(sc, AFI_PEXBIAS_CTRL, 0);
|
|
|
|
|
|
|
|
/* Configure mode and ports. */
|
|
|
|
reg = AFI_RD4(sc, AFI_PCIE_CONFIG);
|
|
|
|
reg &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
|
|
|
|
if (sc->lanes_cfg == 0x14) {
|
|
|
|
if (bootverbose)
|
|
|
|
device_printf(sc->dev,
|
|
|
|
"Using x1,x4 configuration\n");
|
|
|
|
reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1;
|
|
|
|
} else if (sc->lanes_cfg == 0x12) {
|
|
|
|
if (bootverbose)
|
|
|
|
device_printf(sc->dev,
|
|
|
|
"Using x1,x2 configuration\n");
|
|
|
|
reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1;
|
|
|
|
} else {
|
|
|
|
device_printf(sc->dev,
|
|
|
|
"Unsupported lanes configuration: 0x%X\n", sc->lanes_cfg);
|
|
|
|
}
|
|
|
|
reg |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL;
|
|
|
|
for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) {
|
|
|
|
if ((sc->ports[i] != NULL))
|
|
|
|
reg &=
|
|
|
|
~AFI_PCIE_CONFIG_PCIE_DISABLE(sc->ports[i]->port_idx);
|
|
|
|
}
|
|
|
|
AFI_WR4(sc, AFI_PCIE_CONFIG, reg);
|
|
|
|
|
|
|
|
/* Enable Gen2 support. */
|
|
|
|
reg = AFI_RD4(sc, AFI_FUSE);
|
|
|
|
reg &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
|
|
|
|
AFI_WR4(sc, AFI_FUSE, reg);
|
|
|
|
|
2016-09-25 23:48:15 +00:00
|
|
|
for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) {
|
|
|
|
if (sc->ports[i] != NULL) {
|
2018-01-20 17:02:17 +00:00
|
|
|
rv = phy_enable(sc->ports[i]->phy);
|
2016-09-25 23:48:15 +00:00
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev,
|
|
|
|
"Cannot enable phy for port %d\n",
|
|
|
|
sc->ports[i]->port_idx);
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
}
|
2016-03-16 13:01:48 +00:00
|
|
|
}
|
|
|
|
|
2016-09-25 23:48:15 +00:00
|
|
|
|
2016-03-16 13:01:48 +00:00
|
|
|
rv = hwreset_deassert(sc->hwreset_pcie_x);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev, "Cannot unreset 'pci_x' reset\n");
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Enable config space. */
|
|
|
|
reg = AFI_RD4(sc, AFI_CONFIGURATION);
|
|
|
|
reg |= AFI_CONFIGURATION_EN_FPCI;
|
|
|
|
AFI_WR4(sc, AFI_CONFIGURATION, reg);
|
|
|
|
|
|
|
|
/* Enable AFI errors. */
|
|
|
|
reg = 0;
|
|
|
|
reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_SLVERR);
|
|
|
|
reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_DECERR);
|
|
|
|
reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_SLVERR);
|
|
|
|
reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_DECERR);
|
|
|
|
reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_WRERR);
|
|
|
|
reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_SM_MSG);
|
|
|
|
reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_DFPCI_DECERR);
|
|
|
|
reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_AXI_DECERR);
|
|
|
|
reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT);
|
|
|
|
reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE);
|
|
|
|
reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE);
|
|
|
|
reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE);
|
|
|
|
reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE);
|
|
|
|
reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_P2P_ERROR);
|
|
|
|
AFI_WR4(sc, AFI_AFI_INTR_ENABLE, reg);
|
|
|
|
AFI_WR4(sc, AFI_SM_INTR_ENABLE, 0xffffffff);
|
|
|
|
|
|
|
|
/* Enable INT, disable MSI. */
|
|
|
|
AFI_WR4(sc, AFI_INTR_MASK, AFI_INTR_MASK_INT_MASK);
|
|
|
|
|
|
|
|
/* Mask all FPCI errors. */
|
|
|
|
AFI_WR4(sc, AFI_FPCI_ERROR_MASKS, 0);
|
|
|
|
|
|
|
|
/* Setup AFI translation windows. */
|
|
|
|
/* BAR 0 - type 1 extended configuration. */
|
|
|
|
tegra_pcib_set_bar(sc, 0, rman_get_start(sc->cfg_mem_res),
|
|
|
|
FPCI_MAP_EXT_TYPE1_CONFIG, rman_get_size(sc->cfg_mem_res), 0);
|
|
|
|
|
|
|
|
/* BAR 1 - downstream I/O. */
|
2016-07-17 14:45:15 +00:00
|
|
|
tegra_pcib_set_bar(sc, 1, sc->io_range.host, FPCI_MAP_IO,
|
2016-03-16 13:01:48 +00:00
|
|
|
sc->io_range.size, 0);
|
|
|
|
|
|
|
|
/* BAR 2 - downstream prefetchable memory 1:1. */
|
2016-07-17 14:45:15 +00:00
|
|
|
tegra_pcib_set_bar(sc, 2, sc->pref_mem_range.host,
|
|
|
|
sc->pref_mem_range.host, sc->pref_mem_range.size, 1);
|
2016-03-16 13:01:48 +00:00
|
|
|
|
|
|
|
/* BAR 3 - downstream not prefetchable memory 1:1 .*/
|
2016-07-17 14:45:15 +00:00
|
|
|
tegra_pcib_set_bar(sc, 3, sc->mem_range.host,
|
|
|
|
sc->mem_range.host, sc->mem_range.size, 1);
|
2016-03-16 13:01:48 +00:00
|
|
|
|
|
|
|
/* BAR 3-8 clear. */
|
|
|
|
tegra_pcib_set_bar(sc, 4, 0, 0, 0, 0);
|
|
|
|
tegra_pcib_set_bar(sc, 5, 0, 0, 0, 0);
|
|
|
|
tegra_pcib_set_bar(sc, 6, 0, 0, 0, 0);
|
|
|
|
tegra_pcib_set_bar(sc, 7, 0, 0, 0, 0);
|
|
|
|
tegra_pcib_set_bar(sc, 8, 0, 0, 0, 0);
|
|
|
|
|
|
|
|
/* MSI BAR - clear. */
|
|
|
|
tegra_pcib_set_bar(sc, 9, 0, 0, 0, 0);
|
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
2016-08-19 10:53:17 +00:00
|
|
|
#ifdef TEGRA_PCIB_MSI_ENABLE
|
|
|
|
static int
|
|
|
|
tegra_pcib_attach_msi(device_t dev)
|
|
|
|
{
|
|
|
|
struct tegra_pcib_softc *sc;
|
|
|
|
uint32_t reg;
|
|
|
|
int i, rv;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
sc->msi_page = kmem_alloc_contig(kernel_arena, PAGE_SIZE, M_WAITOK,
|
|
|
|
0, BUS_SPACE_MAXADDR, PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
|
|
|
|
|
|
|
|
/* MSI BAR */
|
|
|
|
tegra_pcib_set_bar(sc, 9, vtophys(sc->msi_page), vtophys(sc->msi_page),
|
|
|
|
PAGE_SIZE, 0);
|
|
|
|
|
|
|
|
/* Disble and clear all interrupts. */
|
|
|
|
for (i = 0; i < AFI_MSI_REGS; i++) {
|
|
|
|
AFI_WR4(sc, AFI_MSI_EN_VEC(i), 0);
|
|
|
|
AFI_WR4(sc, AFI_MSI_VEC(i), 0xFFFFFFFF);
|
|
|
|
}
|
|
|
|
rv = bus_setup_intr(dev, sc->msi_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
|
|
|
|
tegra_pcib_msi_intr, NULL, sc, &sc->msi_intr_cookie);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(dev, "cannot setup MSI interrupt handler\n");
|
|
|
|
rv = ENXIO;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (tegra_pcib_msi_attach(sc) != 0) {
|
|
|
|
device_printf(dev, "WARNING: unable to attach PIC\n");
|
|
|
|
tegra_pcib_msi_detach(sc);
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Unmask MSI interrupt. */
|
|
|
|
reg = AFI_RD4(sc, AFI_INTR_MASK);
|
|
|
|
reg |= AFI_INTR_MASK_MSI_MASK;
|
|
|
|
AFI_WR4(sc, AFI_INTR_MASK, reg);
|
|
|
|
|
|
|
|
out:
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2016-03-16 13:01:48 +00:00
|
|
|
static int
|
|
|
|
tegra_pcib_probe(device_t dev)
|
|
|
|
{
|
|
|
|
if (!ofw_bus_status_okay(dev))
|
|
|
|
return (ENXIO);
|
|
|
|
|
|
|
|
if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
|
|
|
|
device_set_desc(dev, "Nvidia Integrated PCI/PCI-E Controller");
|
|
|
|
return (BUS_PROBE_DEFAULT);
|
|
|
|
}
|
|
|
|
return (ENXIO);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
tegra_pcib_attach(device_t dev)
|
|
|
|
{
|
|
|
|
struct tegra_pcib_softc *sc;
|
|
|
|
phandle_t node;
|
|
|
|
int rv;
|
|
|
|
int rid;
|
|
|
|
struct tegra_pcib_port *port;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
sc->dev = dev;
|
|
|
|
mtx_init(&sc->mtx, "msi_mtx", NULL, MTX_DEF);
|
|
|
|
|
|
|
|
node = ofw_bus_get_node(dev);
|
|
|
|
|
|
|
|
rv = tegra_pcib_parse_fdt_resources(sc, node);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(dev, "Cannot get FDT resources\n");
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Allocate bus_space resources. */
|
|
|
|
rid = 0;
|
|
|
|
sc->pads_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
|
|
|
|
RF_ACTIVE);
|
|
|
|
if (sc->pads_mem_res == NULL) {
|
|
|
|
device_printf(dev, "Cannot allocate PADS register\n");
|
|
|
|
rv = ENXIO;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* XXX - FIXME
|
|
|
|
* tag for config space is not filled when RF_ALLOCATED flag is used.
|
|
|
|
*/
|
|
|
|
sc->bus_tag = rman_get_bustag(sc->pads_mem_res);
|
|
|
|
|
|
|
|
rid = 1;
|
|
|
|
sc->afi_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
|
|
|
|
RF_ACTIVE);
|
|
|
|
if (sc->afi_mem_res == NULL) {
|
|
|
|
device_printf(dev, "Cannot allocate AFI register\n");
|
|
|
|
rv = ENXIO;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
rid = 2;
|
|
|
|
sc->cfg_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
|
|
|
|
RF_ALLOCATED);
|
|
|
|
if (sc->cfg_mem_res == NULL) {
|
|
|
|
device_printf(dev, "Cannot allocate config space memory\n");
|
|
|
|
rv = ENXIO;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
sc->cfg_base_addr = rman_get_start(sc->cfg_mem_res);
|
|
|
|
|
|
|
|
|
|
|
|
/* Map RP slots */
|
|
|
|
for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) {
|
|
|
|
if (sc->ports[i] == NULL)
|
|
|
|
continue;
|
|
|
|
port = sc->ports[i];
|
|
|
|
rv = bus_space_map(sc->bus_tag, port->rp_base_addr,
|
|
|
|
port->rp_size, 0, &port->cfg_handle);
|
|
|
|
if (rv != 0) {
|
|
|
|
device_printf(sc->dev, "Cannot allocate memory for "
|
|
|
|
"port: %d\n", i);
|
|
|
|
rv = ENXIO;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2016-07-17 14:45:15 +00:00
|
|
|
* Get PCI interrupt
|
2016-03-16 13:01:48 +00:00
|
|
|
*/
|
|
|
|
rid = 0;
|
|
|
|
sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
|
|
|
|
RF_ACTIVE | RF_SHAREABLE);
|
|
|
|
if (sc->irq_res == NULL) {
|
|
|
|
device_printf(dev, "Cannot allocate IRQ resources\n");
|
|
|
|
rv = ENXIO;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
rid = 1;
|
|
|
|
sc->msi_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
|
|
|
|
RF_ACTIVE);
|
|
|
|
if (sc->irq_res == NULL) {
|
|
|
|
device_printf(dev, "Cannot allocate MSI IRQ resources\n");
|
|
|
|
rv = ENXIO;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2016-07-17 14:45:15 +00:00
|
|
|
sc->ofw_pci.sc_range_mask = 0x3;
|
|
|
|
rv = ofw_pci_init(dev);
|
|
|
|
if (rv != 0)
|
2016-03-16 13:01:48 +00:00
|
|
|
goto out;
|
|
|
|
|
2016-07-17 14:45:15 +00:00
|
|
|
rv = tegra_pcib_decode_ranges(sc, sc->ofw_pci.sc_range,
|
|
|
|
sc->ofw_pci.sc_nrange);
|
2016-03-16 13:01:48 +00:00
|
|
|
if (rv != 0)
|
|
|
|
goto out;
|
|
|
|
|
2016-07-17 14:45:15 +00:00
|
|
|
if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
|
2016-08-19 10:53:17 +00:00
|
|
|
tegra_pci_intr, NULL, sc, &sc->intr_cookie)) {
|
2016-07-17 14:45:15 +00:00
|
|
|
device_printf(dev, "cannot setup interrupt handler\n");
|
|
|
|
rv = ENXIO;
|
2016-03-16 13:01:48 +00:00
|
|
|
goto out;
|
2016-07-17 14:45:15 +00:00
|
|
|
}
|
2016-03-16 13:01:48 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable PCIE device.
|
|
|
|
*/
|
2016-07-09 13:27:14 +00:00
|
|
|
rv = tegra_pcib_enable(sc);
|
2016-03-16 13:01:48 +00:00
|
|
|
if (rv != 0)
|
|
|
|
goto out;
|
|
|
|
for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) {
|
|
|
|
if (sc->ports[i] == NULL)
|
|
|
|
continue;
|
|
|
|
if (sc->ports[i]->enabled)
|
|
|
|
tegra_pcib_port_enable(sc, i);
|
|
|
|
else
|
|
|
|
tegra_pcib_port_disable(sc, i);
|
|
|
|
}
|
|
|
|
|
2016-08-19 10:53:17 +00:00
|
|
|
#ifdef TEGRA_PCIB_MSI_ENABLE
|
|
|
|
rv = tegra_pcib_attach_msi(dev);
|
|
|
|
if (rv != 0)
|
|
|
|
goto out;
|
|
|
|
#endif
|
2016-03-16 13:01:48 +00:00
|
|
|
device_add_child(dev, "pci", -1);
|
|
|
|
|
|
|
|
return (bus_generic_attach(dev));
|
|
|
|
|
|
|
|
out:
|
|
|
|
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static device_method_t tegra_pcib_methods[] = {
|
|
|
|
/* Device interface */
|
|
|
|
DEVMETHOD(device_probe, tegra_pcib_probe),
|
|
|
|
DEVMETHOD(device_attach, tegra_pcib_attach),
|
|
|
|
|
|
|
|
/* Bus interface */
|
|
|
|
DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
|
|
|
|
DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
|
|
|
|
|
|
|
|
/* pcib interface */
|
|
|
|
DEVMETHOD(pcib_maxslots, tegra_pcib_maxslots),
|
|
|
|
DEVMETHOD(pcib_read_config, tegra_pcib_read_config),
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DEVMETHOD(pcib_write_config, tegra_pcib_write_config),
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DEVMETHOD(pcib_route_interrupt, tegra_pcib_route_interrupt),
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DEVMETHOD(pcib_alloc_msi, tegra_pcib_alloc_msi),
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DEVMETHOD(pcib_release_msi, tegra_pcib_release_msi),
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DEVMETHOD(pcib_map_msi, tegra_pcib_map_msi),
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2017-02-25 06:11:59 +00:00
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DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
|
2016-08-19 10:53:17 +00:00
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#ifdef TEGRA_PCIB_MSI_ENABLE
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/* MSI/MSI-X */
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DEVMETHOD(msi_alloc_msi, tegra_pcib_msi_alloc_msi),
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DEVMETHOD(msi_release_msi, tegra_pcib_msi_release_msi),
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DEVMETHOD(msi_map_msi, tegra_pcib_msi_map_msi),
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|
/* Interrupt controller interface */
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DEVMETHOD(pic_disable_intr, tegra_pcib_msi_disable_intr),
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DEVMETHOD(pic_enable_intr, tegra_pcib_msi_enable_intr),
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DEVMETHOD(pic_setup_intr, tegra_pcib_msi_setup_intr),
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DEVMETHOD(pic_teardown_intr, tegra_pcib_msi_teardown_intr),
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|
|
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DEVMETHOD(pic_post_filter, tegra_pcib_msi_post_filter),
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|
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DEVMETHOD(pic_post_ithread, tegra_pcib_msi_post_ithread),
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DEVMETHOD(pic_pre_ithread, tegra_pcib_msi_pre_ithread),
|
2016-03-16 13:01:48 +00:00
|
|
|
#endif
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/* OFW bus interface */
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|
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DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
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DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
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|
|
|
DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
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DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
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DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
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DEVMETHOD_END
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|
|
|
};
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|
|
|
|
2016-09-30 05:25:15 +00:00
|
|
|
static devclass_t pcib_devclass;
|
2016-07-17 14:45:15 +00:00
|
|
|
DEFINE_CLASS_1(pcib, tegra_pcib_driver, tegra_pcib_methods,
|
|
|
|
sizeof(struct tegra_pcib_softc), ofw_pci_driver);
|
2016-09-30 05:25:15 +00:00
|
|
|
DRIVER_MODULE(pcib, simplebus, tegra_pcib_driver, pcib_devclass,
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|
|
|
NULL, NULL);
|