289 lines
7.8 KiB
C
289 lines
7.8 KiB
C
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/*-
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* Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bio.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/endian.h>
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#include <sys/kernel.h>
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#include <sys/kthread.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/queue.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/time.h>
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#include <sys/timetc.h>
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#include <sys/watchdog.h>
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#include <sys/kdb.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/lpc/lpcreg.h>
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#include <arm/lpc/lpcvar.h>
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struct lpc_dmac_channel
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{
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struct lpc_dmac_channel_config *ldc_config;
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int ldc_flags;
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};
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struct lpc_dmac_softc
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{
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device_t ld_dev;
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struct mtx ld_mtx;
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struct resource * ld_mem_res;
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struct resource * ld_irq_res;
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bus_space_tag_t ld_bst;
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bus_space_handle_t ld_bsh;
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void * ld_intrhand;
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struct lpc_dmac_channel ld_channels[8];
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};
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static struct lpc_dmac_softc *lpc_dmac_sc = NULL;
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static int lpc_dmac_probe(device_t);
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static int lpc_dmac_attach(device_t);
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static void lpc_dmac_intr(void *);
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#define lpc_dmac_read_4(_sc, _reg) \
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bus_space_read_4(_sc->ld_bst, _sc->ld_bsh, _reg)
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#define lpc_dmac_write_4(_sc, _reg, _value) \
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bus_space_write_4(_sc->ld_bst, _sc->ld_bsh, _reg, _value)
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#define lpc_dmac_read_ch_4(_sc, _n, _reg) \
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bus_space_read_4(_sc->ld_bst, _sc->ld_bsh, (_reg + LPC_DMAC_CHADDR(_n)))
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#define lpc_dmac_write_ch_4(_sc, _n, _reg, _value) \
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bus_space_write_4(_sc->ld_bst, _sc->ld_bsh, (_reg + LPC_DMAC_CHADDR(_n)), _value)
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static int lpc_dmac_probe(device_t dev)
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{
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if (!ofw_bus_is_compatible(dev, "lpc,dmac"))
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return (ENXIO);
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device_set_desc(dev, "LPC32x0 General Purpose DMA controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int lpc_dmac_attach(device_t dev)
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{
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struct lpc_dmac_softc *sc = device_get_softc(dev);
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int rid;
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rid = 0;
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sc->ld_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (!sc->ld_mem_res) {
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device_printf(dev, "cannot allocate memory window\n");
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return (ENXIO);
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}
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sc->ld_bst = rman_get_bustag(sc->ld_mem_res);
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sc->ld_bsh = rman_get_bushandle(sc->ld_mem_res);
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rid = 0;
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sc->ld_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_ACTIVE);
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if (!sc->ld_irq_res) {
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device_printf(dev, "cannot allocate cmd interrupt\n");
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->ld_mem_res);
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return (ENXIO);
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}
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if (bus_setup_intr(dev, sc->ld_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
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NULL, lpc_dmac_intr, sc, &sc->ld_intrhand))
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{
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->ld_mem_res);
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bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ld_irq_res);
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device_printf(dev, "cannot setup interrupt handler\n");
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return (ENXIO);
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}
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lpc_dmac_sc = sc;
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lpc_pwr_write(dev, LPC_CLKPWR_DMACLK_CTRL, LPC_CLKPWR_DMACLK_CTRL_EN);
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lpc_dmac_write_4(sc, LPC_DMAC_CONFIG, LPC_DMAC_CONFIG_ENABLE);
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lpc_dmac_write_4(sc, LPC_DMAC_INTTCCLEAR, 0xff);
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lpc_dmac_write_4(sc, LPC_DMAC_INTERRCLEAR, 0xff);
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return (0);
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}
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static void lpc_dmac_intr(void *arg)
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{
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struct lpc_dmac_softc *sc = (struct lpc_dmac_softc *)arg;
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struct lpc_dmac_channel *ch;
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uint32_t intstat, tcstat, errstat;
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int i;
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do {
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intstat = lpc_dmac_read_4(sc, LPC_DMAC_INTSTAT);
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for (i = 0; i < LPC_DMAC_CHNUM; i++) {
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if ((intstat & (1 << i)) == 0)
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continue;
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ch = &sc->ld_channels[i];
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tcstat = lpc_dmac_read_4(sc, LPC_DMAC_INTTCSTAT);
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errstat = lpc_dmac_read_4(sc, LPC_DMAC_INTERRSTAT);
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if (tcstat & (1 << i)) {
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ch->ldc_config->ldc_success_handler(
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ch->ldc_config->ldc_handler_arg);
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lpc_dmac_write_4(sc, LPC_DMAC_INTTCCLEAR, (1 << i));
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}
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if (errstat & (1 << i)) {
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ch->ldc_config->ldc_error_handler(
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ch->ldc_config->ldc_handler_arg);
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lpc_dmac_write_4(sc, LPC_DMAC_INTERRCLEAR, (1 << i));
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}
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}
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} while (intstat);
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}
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int
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lpc_dmac_config_channel(device_t dev, int chno, struct lpc_dmac_channel_config *cfg)
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{
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struct lpc_dmac_softc *sc = lpc_dmac_sc;
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struct lpc_dmac_channel *ch;
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if (sc == NULL)
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return (ENXIO);
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ch = &sc->ld_channels[chno];
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ch->ldc_config = cfg;
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return 0;
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}
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int
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lpc_dmac_setup_transfer(device_t dev, int chno, bus_addr_t src, bus_addr_t dst,
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bus_size_t size, int flags)
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{
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struct lpc_dmac_softc *sc = lpc_dmac_sc;
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struct lpc_dmac_channel *ch;
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uint32_t ctrl, cfg;
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if (sc == NULL)
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return (ENXIO);
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ch = &sc->ld_channels[chno];
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ctrl = LPC_DMAC_CH_CONTROL_I |
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(ch->ldc_config->ldc_dst_incr ? LPC_DMAC_CH_CONTROL_DI : 0) |
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(ch->ldc_config->ldc_src_incr ? LPC_DMAC_CH_CONTROL_SI : 0) |
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LPC_DMAC_CH_CONTROL_DWIDTH(ch->ldc_config->ldc_dst_width) |
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LPC_DMAC_CH_CONTROL_SWIDTH(ch->ldc_config->ldc_src_width) |
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LPC_DMAC_CH_CONTROL_DBSIZE(ch->ldc_config->ldc_dst_burst) |
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LPC_DMAC_CH_CONTROL_SBSIZE(ch->ldc_config->ldc_src_burst) |
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size;
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cfg = LPC_DMAC_CH_CONFIG_ITC | LPC_DMAC_CH_CONFIG_IE |
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LPC_DMAC_CH_CONFIG_FLOWCNTL(ch->ldc_config->ldc_fcntl) |
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LPC_DMAC_CH_CONFIG_DESTP(ch->ldc_config->ldc_dst_periph) |
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LPC_DMAC_CH_CONFIG_SRCP(ch->ldc_config->ldc_src_periph) | LPC_DMAC_CH_CONFIG_E;
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lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_SRCADDR, src);
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lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_DSTADDR, dst);
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lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_LLI, 0);
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lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_CONTROL, ctrl);
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lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_CONFIG, cfg);
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return 0;
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}
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int
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lpc_dmac_enable_channel(device_t dev, int chno)
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{
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struct lpc_dmac_softc *sc = lpc_dmac_sc;
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uint32_t cfg;
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if (sc == NULL)
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return (ENXIO);
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cfg = lpc_dmac_read_ch_4(sc, chno, LPC_DMAC_CH_CONFIG);
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cfg |= LPC_DMAC_CH_CONFIG_E;
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lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_CONFIG, cfg);
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return 0;
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}
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int
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lpc_dmac_disable_channel(device_t dev, int chno)
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{
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struct lpc_dmac_softc *sc = lpc_dmac_sc;
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uint32_t cfg;
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if (sc == NULL)
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return (ENXIO);
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cfg = lpc_dmac_read_ch_4(sc, chno, LPC_DMAC_CH_CONFIG);
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cfg &= ~LPC_DMAC_CH_CONFIG_E;
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lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_CONFIG, cfg);
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return 0;
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}
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int
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lpc_dmac_start_burst(device_t dev, int id)
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{
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struct lpc_dmac_softc *sc = lpc_dmac_sc;
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lpc_dmac_write_4(sc, LPC_DMAC_SOFTBREQ, (1 << id));
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return (0);
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}
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static device_method_t lpc_dmac_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, lpc_dmac_probe),
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DEVMETHOD(device_attach, lpc_dmac_attach),
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{ 0, 0 },
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};
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static devclass_t lpc_dmac_devclass;
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static driver_t lpc_dmac_driver = {
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"dmac",
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lpc_dmac_methods,
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sizeof(struct lpc_dmac_softc),
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};
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DRIVER_MODULE(dmac, simplebus, lpc_dmac_driver, lpc_dmac_devclass, 0, 0);
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