d/freebsd-dev
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
864fb934d0
freebsd-dev/sys/sparc64/pci/psycho.c

1401 lines
40 KiB
C
Raw Normal View History

/* -> /*- for license, minor formatting changes
2005-01-07 02:29:27 +00:00
/*-
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
* Copyright (c) 1999, 2000 Matthew R. Green
Add the new sparc64 OFW PCI framework, conditional on options OFW_NEWPCI for now. It introduces a OFW PCI bus driver and a generic OFW PCI-PCI bridge driver. By utilizing these, the PCI handling is much more elegant now. The advantages of the new approach are: - Device enumeration should hopefully be more like on Solaris now, so unit numbers should match what's printed on the box more closely. - Real interrupt routing is implemented now, so cardbus bridges etc. have at least a chance to work. - The quirk tables are gone and have been replaced by (hopefully sufficient) heuristics. - Much cleaner code. There was also a report that previously bogus interrupt assignments are fixed now, which can be attributed to the new heuristics. A pitfall, and the reason why this is not the default yet, is that it changes device enumeration, as mentioned above, which can make it necessary to change the system configuration if more than one unit of a device type is present (on a system with two hme cars, for example, it is possible that hme0 becomes hme1 and vice versa after enabling the option). Systems with multiple disk controllers may need to be booted into single user (and require manual specification of the root file system on boot) to adjust the fstab. Nevertheless, I would like to encourage users to use this option, so that it can be made the default soon. In detail, the changes are: - Introduce an OFW PCI bus driver; it inherits most methods from the generic PCI bus driver, but uses the firmware for enumeration, performs additional initialization for devices and firmware-specific interrupt routing. It also implements an OFW-specific method to allow child devices to get their firmware nodes. - Introduce an OFW PCI-PCI bridge driver; again, it inherits most of the generic PCI-PCI bridge driver; it has it's own method for interrupt routing, as well as some sparc64-specific methods (one to get the node again, and one to adjust the bridge bus range, since we need to reenumerate all PCI buses). - Convert the apb driver to the new way of handling things. - Provide a common framework for OFW bridge drivers, used be the two drivers above. - Provide a small common framework for interrupt routing (for all bridge types). - Convert the psycho driver to the new framework; this gets rid of a bunch of old kludges in pci_read_config(), and the whole preinitialization (ofw_pci_init()). - Convert the ISA MD part and the EBus driver to the new way interrupts and nodes are handled. - Introduce types for firmware interrupt properties. - Rename the old sparcbus_if to ofw_pci_if by repo copy (it is only required for PCI), and move it to a more correct location (new support methodsx were also added, and an old one was deprecated). - Fix a bunch of minor bugs, perform some cleanups. In some cases, I introduced some minor code duplication to keep the new code clean, in hopes that the old code will be unifdef'ed soon. Reviewed in part by: imp Tested by: jake, Marius Strobl <marius@alchemy.franken.de>, Sergey Mokryshev <mokr@mokr.net>, Chris Jackman <cjackNOSPAM@klatsch.org> Info on u30 firmware provided by: kris
2003-07-01 14:52:47 +00:00
* Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
2007-03-07 21:13:51 +00:00
* Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org>
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
* from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
*/
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
/*
- Improve the comment regarding the workaround for the E250 interrupt map bug by explaining what the problem is and how the workaround works. - Fix some cosmetics nits, mainly properly terminate sentences in comments, which I missed when backporting the style changes to psycho(4) in psycho.c rev. 1.54 due to lack of corresponding code. - The "USIIe version of the Sabre bridge" actually is termed "Hummingbird"; name it as such in comments and messages.
2005-12-03 13:08:05 +00:00
* Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+'
* (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges.
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
*/
Add the new sparc64 OFW PCI framework, conditional on options OFW_NEWPCI for now. It introduces a OFW PCI bus driver and a generic OFW PCI-PCI bridge driver. By utilizing these, the PCI handling is much more elegant now. The advantages of the new approach are: - Device enumeration should hopefully be more like on Solaris now, so unit numbers should match what's printed on the box more closely. - Real interrupt routing is implemented now, so cardbus bridges etc. have at least a chance to work. - The quirk tables are gone and have been replaced by (hopefully sufficient) heuristics. - Much cleaner code. There was also a report that previously bogus interrupt assignments are fixed now, which can be attributed to the new heuristics. A pitfall, and the reason why this is not the default yet, is that it changes device enumeration, as mentioned above, which can make it necessary to change the system configuration if more than one unit of a device type is present (on a system with two hme cars, for example, it is possible that hme0 becomes hme1 and vice versa after enabling the option). Systems with multiple disk controllers may need to be booted into single user (and require manual specification of the root file system on boot) to adjust the fstab. Nevertheless, I would like to encourage users to use this option, so that it can be made the default soon. In detail, the changes are: - Introduce an OFW PCI bus driver; it inherits most methods from the generic PCI bus driver, but uses the firmware for enumeration, performs additional initialization for devices and firmware-specific interrupt routing. It also implements an OFW-specific method to allow child devices to get their firmware nodes. - Introduce an OFW PCI-PCI bridge driver; again, it inherits most of the generic PCI-PCI bridge driver; it has it's own method for interrupt routing, as well as some sparc64-specific methods (one to get the node again, and one to adjust the bridge bus range, since we need to reenumerate all PCI buses). - Convert the apb driver to the new way of handling things. - Provide a common framework for OFW bridge drivers, used be the two drivers above. - Provide a small common framework for interrupt routing (for all bridge types). - Convert the psycho driver to the new framework; this gets rid of a bunch of old kludges in pci_read_config(), and the whole preinitialization (ofw_pci_init()). - Convert the ISA MD part and the EBus driver to the new way interrupts and nodes are handled. - Introduce types for firmware interrupt properties. - Rename the old sparcbus_if to ofw_pci_if by repo copy (it is only required for PCI), and move it to a more correct location (new support methodsx were also added, and an old one was deprecated). - Fix a bunch of minor bugs, perform some cleanups. In some cases, I introduced some minor code duplication to keep the new code clean, in hopes that the old code will be unifdef'ed soon. Reviewed in part by: imp Tested by: jake, Marius Strobl <marius@alchemy.franken.de>, Sergey Mokryshev <mokr@mokr.net>, Chris Jackman <cjackNOSPAM@klatsch.org> Info on u30 firmware provided by: kris
2003-07-01 14:52:47 +00:00
#include "opt_ofw_pci.h"
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
#include "opt_psycho.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
- Add the PCI side of the HOST-PCI bridge itself to the bus. This is required by the X.Org PCI domains code and additionally needs a workaround for Hummingbird and Sabre bridges as these don't allow their config headers to be read at any width, which is an unusual behavior. - In psycho(4) take advantage of DEFINE_CLASS_0 and use more appropriate types for some softc members. MFC after: 3 days
2007-11-30 23:02:42 +00:00
#include <sys/endian.h>
Update for the KDB framework: o Call kdb_enter() instead of Debugger().
2004-07-10 23:06:41 +00:00
#include <sys/kdb.h>
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
#include <sys/kernel.h>
- Use the newly introduced pcib_mtx spin lock to lock psycho_ce(), allowing it to be a filter/"fast" handler. Locking the interrupt handlers with a spin lock is mainly a requirement in schizo(4) but as we ought to register the spin lock anyway it should not hurt to take advantage of it in psycho(4). - Pass both a driver_filter_t and a driver_intr_t argument to psycho_set_intr(), allowing to get rid of the FAST interrupt flag hack. - Don't register the over-temperature interrupt handler as filter/ "fast" handler so shutdown_nice() can acquire the process lock. - Use bus_{read,write}_8() instead of bus_space_{read,write}_8() in order to get rid of sc_bushandle and sc_bustag in the softc. - Correct the debug output for adjusting the subordinate bus number. - Remove the banal and outdated above psycho_filter_stub(). - Fix some white space nits.
2007-06-16 23:46:41 +00:00
#include <sys/lock.h>
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
#include <sys/malloc.h>
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
2007-03-07 21:13:51 +00:00
#include <sys/module.h>
- Use the newly introduced pcib_mtx spin lock to lock psycho_ce(), allowing it to be a filter/"fast" handler. Locking the interrupt handlers with a spin lock is mainly a requirement in schizo(4) but as we ought to register the spin lock anyway it should not hurt to take advantage of it in psycho(4). - Pass both a driver_filter_t and a driver_intr_t argument to psycho_set_intr(), allowing to get rid of the FAST interrupt flag hack. - Don't register the over-temperature interrupt handler as filter/ "fast" handler so shutdown_nice() can acquire the process lock. - Use bus_{read,write}_8() instead of bus_space_{read,write}_8() in order to get rid of sc_bushandle and sc_bustag in the softc. - Correct the debug output for adjusting the subordinate bus number. - Remove the banal and outdated above psycho_filter_stub(). - Fix some white space nits.
2007-06-16 23:46:41 +00:00
#include <sys/mutex.h>
Always initialize the UPA target module id in the interrupt mapping register to the one of the processor doing the interrupt setup. This is required since this field is preinitialized to 0, but there exist machines which have no processor with a MID of 0 (e.g. e450s with 1 or 2 processors). Add some more macros for handle the interrupt mapping registers, and rename some existing ones for consistency. Approved by: re
2002-12-01 23:30:26 +00:00
#include <sys/pcpu.h>
- Register the PCI bus error interrupt handler according to which half of the bridge (PCI bus A or B) we are attaching to rather than registering both handlers at once when attaching to the first half we encounter. This is a bit cleaner as it corresponds to which PCI bus error interrupt actually is assigned to the respective half by the OFW and allows to collapse both PCI bus error interrupt handlers into one function easily. - Use the actual RID of the respective interrupt resource as index into sc_irq_res and also use it when allocating the resource. For now this is a bit cleaner and will be mandatory later on. - According to OpenSolaris the spare hardware interrupt is used as the over-temperature interrupt in systems with Psycho bridges. Unlike as with the SBus-based workstations I didn't manage to trigger it when covering the fan outlets of an U60 but better be safe than sorry and register a handler anyway. MFC after: 1 month
2005-12-03 16:36:54 +00:00
#include <sys/reboot.h>
- Divorce the IOTSBs, which so far where handled via a global list instead of per IOMMU, so we no longer need to program all of them identically in systems having multiple IOMMUs. This continues the rototilling of the nexus(4) done about 5 months ago, which amongst others changed nexus(4) and the drivers for host-to-foo bridges to provide bus_get_dma_tag methods, allowing to handle DMA tags in a hierarchical way and to link them with devices. This still doesn't move the silicon bug workarounds for Sabre (and in the uncommitted schizo(4) for Tomatillo) bridges into special bus_dma_tag_create() and bus_dmamap_sync() methods though, as w/o fully newbus'ified bus_dma_tag_create() and bus_dma_tag_destroy() this still requires too much hackery, i.e. per-child parent DMA tags in the parent driver. - Let the host-to-foo drivers supply the maximum physical address of the IOMMU accompanying the bridges. Previously iommu(4) hard- coded an upper limit of 16GB, which actually only applies to the IOMMUs of the Hummingbird and Sabre bridges. The Psycho variants as well as the U2S in fact can can translate to up to 2TB, i.e. translate to 41-bit physical addresses. According to the recently available Tomatillo documentation these bridges even translate to 43-bit physical addresses and hints at the Schizo bridges doing 43 bits as well. This fixes the issue the FreeBSD 6.0 todo list item "Max RAM on sparc64" was refering to and pretty much obsoletes the lack of support for bounce buffers on sparc64. Thanks to Nathan Whitehorn for pointing me at the Tomatillo manual. Approved by: re (kensmith)
2007-08-05 11:56:44 +00:00
#include <sys/rman.h>
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
- Introduce an ofw_bus kobj-interface for retrieving the OFW node and a subset ("compatible", "device_type", "model" and "name") of the standard properties in drivers for devices on Open Firmware supported busses. The standard properties "reg", "interrupts" und "address" are not covered by this interface because they are only of interest in the respective bridge code. There's a remaining standard property "status" which is unclear how to support properly but which also isn't used in FreeBSD at present. This ofw_bus kobj-interface allows to replace the various (ebus_get_node(), ofw_pci_get_node(), etc.) and partially inconsistent (central_get_type() vs. sbus_get_device_type(), etc.) existing IVAR ones with a common one. This in turn allows to simplify and remove code-duplication in drivers for devices that can hang off of more than one OFW supported bus. - Convert the sparc64 Central, EBus, FHC, PCI and SBus bus drivers and the drivers for their children to use the ofw_bus kobj-interface. The IVAR- interfaces of the Central, EBus and FHC are entirely replaced by this. The PCI bus driver used its own kobj-interface and now also uses the ofw_bus one. The IVARs special to the SBus, e.g. for retrieving the burst size, remain. Beware: this causes an ABI-breakage for modules of drivers which used the IVAR-interfaces, i.e. esp(4), hme(4), isp(4) and uart(4), which need to be recompiled. The style-inconsistencies introduced in some of the bus drivers will be fixed by tmm@ in a generic clean-up of the respective drivers later (he requested to add the changes in the "new" style). - Convert the powerpc MacIO bus driver and the drivers for its children to use the ofw_bus kobj-interface. This invloves removing the IVARs related to the "reg" property which were unused and a leftover from the NetBSD origini of the code. There's no ABI-breakage caused by this because none of these driver are currently built as modules. There are other powerpc bus drivers which can be converted to the ofw_bus kobj-interface, e.g. the PCI bus driver, which should be done together with converting powerpc to use the OFW PCI code from sparc64. - Make the SBus and FHC front-end of zs(4) and the sparc64 eeprom(4) take advantage of the ofw_bus kobj-interface and simplify them a bit. Reviewed by: grehan, tmm Approved by: re (scottl) Discussed with: tmm Tested with: Sun AX1105, AXe, Ultra 2, Ultra 60; PPC cross-build on i386
2004-08-12 17:41:33 +00:00
#include <dev/ofw/ofw_bus.h>
s=include <ofw/=include <dev/ofw/= to reflect removal of -I$S/dev
2003-08-23 00:11:16 +00:00
#include <dev/ofw/ofw_pci.h>
- Introduce an ofw_bus kobj-interface for retrieving the OFW node and a subset ("compatible", "device_type", "model" and "name") of the standard properties in drivers for devices on Open Firmware supported busses. The standard properties "reg", "interrupts" und "address" are not covered by this interface because they are only of interest in the respective bridge code. There's a remaining standard property "status" which is unclear how to support properly but which also isn't used in FreeBSD at present. This ofw_bus kobj-interface allows to replace the various (ebus_get_node(), ofw_pci_get_node(), etc.) and partially inconsistent (central_get_type() vs. sbus_get_device_type(), etc.) existing IVAR ones with a common one. This in turn allows to simplify and remove code-duplication in drivers for devices that can hang off of more than one OFW supported bus. - Convert the sparc64 Central, EBus, FHC, PCI and SBus bus drivers and the drivers for their children to use the ofw_bus kobj-interface. The IVAR- interfaces of the Central, EBus and FHC are entirely replaced by this. The PCI bus driver used its own kobj-interface and now also uses the ofw_bus one. The IVARs special to the SBus, e.g. for retrieving the burst size, remain. Beware: this causes an ABI-breakage for modules of drivers which used the IVAR-interfaces, i.e. esp(4), hme(4), isp(4) and uart(4), which need to be recompiled. The style-inconsistencies introduced in some of the bus drivers will be fixed by tmm@ in a generic clean-up of the respective drivers later (he requested to add the changes in the "new" style). - Convert the powerpc MacIO bus driver and the drivers for its children to use the ofw_bus kobj-interface. This invloves removing the IVARs related to the "reg" property which were unused and a leftover from the NetBSD origini of the code. There's no ABI-breakage caused by this because none of these driver are currently built as modules. There are other powerpc bus drivers which can be converted to the ofw_bus kobj-interface, e.g. the PCI bus driver, which should be done together with converting powerpc to use the OFW PCI code from sparc64. - Make the SBus and FHC front-end of zs(4) and the sparc64 eeprom(4) take advantage of the ofw_bus kobj-interface and simplify them a bit. Reviewed by: grehan, tmm Approved by: re (scottl) Discussed with: tmm Tested with: Sun AX1105, AXe, Ultra 2, Ultra 60; PPC cross-build on i386
2004-08-12 17:41:33 +00:00
#include <dev/ofw/openfirm.h>
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
#include <machine/bus.h>
#include <machine/bus_common.h>
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
2007-03-07 21:13:51 +00:00
#include <machine/bus_private.h>
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
#include <machine/iommureg.h>
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
2007-03-07 21:13:51 +00:00
#include <machine/iommuvar.h>
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
#include <machine/resource.h>
- Add a workaround (change the interrupt map mask to compare the full INO) for incorrect interrupt map entries on E250 machines. These incorrect entries caused the INO of the on-board HME to be also assigned to the second on-board NS16550 and to the on-board printer port controller. Further down the road caused hme(4) to fail to attach to the on-board HME in FreeBSD 5 and 6 as INTR_FAST and non-INTR_FAST handlers can't share the same IRQ there (it's unknown what whould happen in -CURRENT now that INTR_FAST and non-INTR_FAST handlers can share an IRQ but I'd expect funny problems with uart(4)). - Make sure there are exactly 4 PCI ranges instead of just checking that the bridge has a 'ranges' property in the OFW device tree at all. Besides the fact that currently the 64bit memory range isn't used by this driver it we can't really work with less than 4 ranges and don't have memory for more than 4 bus handles for the ranges in the softc. - Remove sc_range and sc_nrange from softc; for the bridges supported by this driver we no longer need to know the ranges besides the bus handles obtained from them once this driver is attached. That way we also can free the memory allocated for sc_range during attach again. - Remove sc_dvmabase from the softc and pass it to psycho_iommu_init() via an additional argument as we no longer need to know the DVMA base in this driver once the IOMMU is initialized. - Remove sc_dmatag from the softc, there isn't much sense in keeping the nexus dma tag around locally. PR: 88279 [1] Info from: OpenSolaris [1] Tested by: kensmith [1] MFC after: 1 month
2005-11-22 22:32:50 +00:00
#include <machine/ver.h>
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
#include <dev/pci/pcireg.h>
Prefer new location of pci include files (which have only been in the tree for two or more years now), except in a few places where there's code to be compatible with older versions of FreeBSD.
2003-08-22 07:39:05 +00:00
#include <dev/pci/pcivar.h>
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
#include <sparc64/pci/ofw_pci.h>
#include <sparc64/pci/psychoreg.h>
#include <sparc64/pci/psychovar.h>
#include "pcib_if.h"
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *,
const char *);
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
2007-03-07 21:13:51 +00:00
static const struct psycho_desc *psycho_get_desc(device_t);
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
static void psycho_set_intr(struct psycho_softc *, u_int, bus_addr_t,
- Use the newly introduced pcib_mtx spin lock to lock psycho_ce(), allowing it to be a filter/"fast" handler. Locking the interrupt handlers with a spin lock is mainly a requirement in schizo(4) but as we ought to register the spin lock anyway it should not hurt to take advantage of it in psycho(4). - Pass both a driver_filter_t and a driver_intr_t argument to psycho_set_intr(), allowing to get rid of the FAST interrupt flag hack. - Don't register the over-temperature interrupt handler as filter/ "fast" handler so shutdown_nice() can acquire the process lock. - Use bus_{read,write}_8() instead of bus_space_{read,write}_8() in order to get rid of sc_bushandle and sc_bustag in the softc. - Correct the debug output for adjusting the subordinate bus number. - Remove the banal and outdated above psycho_filter_stub(). - Fix some white space nits.
2007-06-16 23:46:41 +00:00
driver_filter_t, driver_intr_t);
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
static int psycho_find_intrmap(struct psycho_softc *, u_int, bus_addr_t *,
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
bus_addr_t *, u_long *);
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
static driver_filter_t psycho_dma_sync_stub;
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
static void psycho_intr_enable(void *);
static void psycho_intr_disable(void *);
o Rename ic_eoi to ic_clear to emphasize the functions it points don't send and EOI which works like on amd64/i386 and blocks all interrupts on the relevant interrupt controller. o Replace the post_filter and post_inthread hooks registered when creating the interrupt events with just ic_clear as on sparc64 we don't need to do any disable->EOI->enable dance to unblock all but the relevant interrupt while running the filter or handler; just not clearing the interrupt already has the same effect. o Merge from amd64/i386: - Split the intr_table_lock into an sx lock used for most things, and a spin lock to protect intrcnt_index. - Add support for binding interrupts to CPUs, including for the bus_bind_intr(9) interface, a assign_cpu hook and initially shuffling interrupts arround in a round-robin fashion. Reviewed by: jhb MFC after: 1 month
2008-04-23 20:04:38 +00:00
static void psycho_intr_assign(void *);
static void psycho_intr_clear(void *);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int);
/* Interrupt handlers */
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
2007-03-07 21:13:51 +00:00
static driver_filter_t psycho_ue;
static driver_filter_t psycho_ce;
static driver_filter_t psycho_pci_bus;
static driver_filter_t psycho_powerfail;
- Use the newly introduced pcib_mtx spin lock to lock psycho_ce(), allowing it to be a filter/"fast" handler. Locking the interrupt handlers with a spin lock is mainly a requirement in schizo(4) but as we ought to register the spin lock anyway it should not hurt to take advantage of it in psycho(4). - Pass both a driver_filter_t and a driver_intr_t argument to psycho_set_intr(), allowing to get rid of the FAST interrupt flag hack. - Don't register the over-temperature interrupt handler as filter/ "fast" handler so shutdown_nice() can acquire the process lock. - Use bus_{read,write}_8() instead of bus_space_{read,write}_8() in order to get rid of sc_bushandle and sc_bustag in the softc. - Correct the debug output for adjusting the subordinate bus number. - Remove the banal and outdated above psycho_filter_stub(). - Fix some white space nits.
2007-06-16 23:46:41 +00:00
static driver_intr_t psycho_overtemp;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
#ifdef PSYCHO_MAP_WAKEUP
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
2007-03-07 21:13:51 +00:00
static driver_filter_t psycho_wakeup;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
#endif
/* IOMMU support */
- Add a workaround (change the interrupt map mask to compare the full INO) for incorrect interrupt map entries on E250 machines. These incorrect entries caused the INO of the on-board HME to be also assigned to the second on-board NS16550 and to the on-board printer port controller. Further down the road caused hme(4) to fail to attach to the on-board HME in FreeBSD 5 and 6 as INTR_FAST and non-INTR_FAST handlers can't share the same IRQ there (it's unknown what whould happen in -CURRENT now that INTR_FAST and non-INTR_FAST handlers can share an IRQ but I'd expect funny problems with uart(4)). - Make sure there are exactly 4 PCI ranges instead of just checking that the bridge has a 'ranges' property in the OFW device tree at all. Besides the fact that currently the 64bit memory range isn't used by this driver it we can't really work with less than 4 ranges and don't have memory for more than 4 bus handles for the ranges in the softc. - Remove sc_range and sc_nrange from softc; for the bridges supported by this driver we no longer need to know the ranges besides the bus handles obtained from them once this driver is attached. That way we also can free the memory allocated for sc_range during attach again. - Remove sc_dvmabase from the softc and pass it to psycho_iommu_init() via an additional argument as we no longer need to know the DVMA base in this driver once the IOMMU is initialized. - Remove sc_dmatag from the softc, there isn't much sense in keeping the nexus dma tag around locally. PR: 88279 [1] Info from: OpenSolaris [1] Tested by: kensmith [1] MFC after: 1 month
2005-11-22 22:32:50 +00:00
static void psycho_iommu_init(struct psycho_softc *, int, uint32_t);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
/*
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
* Methods
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
*/
Add the new sparc64 OFW PCI framework, conditional on options OFW_NEWPCI for now. It introduces a OFW PCI bus driver and a generic OFW PCI-PCI bridge driver. By utilizing these, the PCI handling is much more elegant now. The advantages of the new approach are: - Device enumeration should hopefully be more like on Solaris now, so unit numbers should match what's printed on the box more closely. - Real interrupt routing is implemented now, so cardbus bridges etc. have at least a chance to work. - The quirk tables are gone and have been replaced by (hopefully sufficient) heuristics. - Much cleaner code. There was also a report that previously bogus interrupt assignments are fixed now, which can be attributed to the new heuristics. A pitfall, and the reason why this is not the default yet, is that it changes device enumeration, as mentioned above, which can make it necessary to change the system configuration if more than one unit of a device type is present (on a system with two hme cars, for example, it is possible that hme0 becomes hme1 and vice versa after enabling the option). Systems with multiple disk controllers may need to be booted into single user (and require manual specification of the root file system on boot) to adjust the fstab. Nevertheless, I would like to encourage users to use this option, so that it can be made the default soon. In detail, the changes are: - Introduce an OFW PCI bus driver; it inherits most methods from the generic PCI bus driver, but uses the firmware for enumeration, performs additional initialization for devices and firmware-specific interrupt routing. It also implements an OFW-specific method to allow child devices to get their firmware nodes. - Introduce an OFW PCI-PCI bridge driver; again, it inherits most of the generic PCI-PCI bridge driver; it has it's own method for interrupt routing, as well as some sparc64-specific methods (one to get the node again, and one to adjust the bridge bus range, since we need to reenumerate all PCI buses). - Convert the apb driver to the new way of handling things. - Provide a common framework for OFW bridge drivers, used be the two drivers above. - Provide a small common framework for interrupt routing (for all bridge types). - Convert the psycho driver to the new framework; this gets rid of a bunch of old kludges in pci_read_config(), and the whole preinitialization (ofw_pci_init()). - Convert the ISA MD part and the EBus driver to the new way interrupts and nodes are handled. - Introduce types for firmware interrupt properties. - Rename the old sparcbus_if to ofw_pci_if by repo copy (it is only required for PCI), and move it to a more correct location (new support methodsx were also added, and an old one was deprecated). - Fix a bunch of minor bugs, perform some cleanups. In some cases, I introduced some minor code duplication to keep the new code clean, in hopes that the old code will be unifdef'ed soon. Reviewed in part by: imp Tested by: jake, Marius Strobl <marius@alchemy.franken.de>, Sergey Mokryshev <mokr@mokr.net>, Chris Jackman <cjackNOSPAM@klatsch.org> Info on u30 firmware provided by: kris
2003-07-01 14:52:47 +00:00
static device_probe_t psycho_probe;
static device_attach_t psycho_attach;
static bus_read_ivar_t psycho_read_ivar;
static bus_setup_intr_t psycho_setup_intr;
static bus_teardown_intr_t psycho_teardown_intr;
static bus_alloc_resource_t psycho_alloc_resource;
static bus_activate_resource_t psycho_activate_resource;
static bus_deactivate_resource_t psycho_deactivate_resource;
static bus_release_resource_t psycho_release_resource;
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
2007-03-07 21:13:51 +00:00
static bus_get_dma_tag_t psycho_get_dma_tag;
Add the new sparc64 OFW PCI framework, conditional on options OFW_NEWPCI for now. It introduces a OFW PCI bus driver and a generic OFW PCI-PCI bridge driver. By utilizing these, the PCI handling is much more elegant now. The advantages of the new approach are: - Device enumeration should hopefully be more like on Solaris now, so unit numbers should match what's printed on the box more closely. - Real interrupt routing is implemented now, so cardbus bridges etc. have at least a chance to work. - The quirk tables are gone and have been replaced by (hopefully sufficient) heuristics. - Much cleaner code. There was also a report that previously bogus interrupt assignments are fixed now, which can be attributed to the new heuristics. A pitfall, and the reason why this is not the default yet, is that it changes device enumeration, as mentioned above, which can make it necessary to change the system configuration if more than one unit of a device type is present (on a system with two hme cars, for example, it is possible that hme0 becomes hme1 and vice versa after enabling the option). Systems with multiple disk controllers may need to be booted into single user (and require manual specification of the root file system on boot) to adjust the fstab. Nevertheless, I would like to encourage users to use this option, so that it can be made the default soon. In detail, the changes are: - Introduce an OFW PCI bus driver; it inherits most methods from the generic PCI bus driver, but uses the firmware for enumeration, performs additional initialization for devices and firmware-specific interrupt routing. It also implements an OFW-specific method to allow child devices to get their firmware nodes. - Introduce an OFW PCI-PCI bridge driver; again, it inherits most of the generic PCI-PCI bridge driver; it has it's own method for interrupt routing, as well as some sparc64-specific methods (one to get the node again, and one to adjust the bridge bus range, since we need to reenumerate all PCI buses). - Convert the apb driver to the new way of handling things. - Provide a common framework for OFW bridge drivers, used be the two drivers above. - Provide a small common framework for interrupt routing (for all bridge types). - Convert the psycho driver to the new framework; this gets rid of a bunch of old kludges in pci_read_config(), and the whole preinitialization (ofw_pci_init()). - Convert the ISA MD part and the EBus driver to the new way interrupts and nodes are handled. - Introduce types for firmware interrupt properties. - Rename the old sparcbus_if to ofw_pci_if by repo copy (it is only required for PCI), and move it to a more correct location (new support methodsx were also added, and an old one was deprecated). - Fix a bunch of minor bugs, perform some cleanups. In some cases, I introduced some minor code duplication to keep the new code clean, in hopes that the old code will be unifdef'ed soon. Reviewed in part by: imp Tested by: jake, Marius Strobl <marius@alchemy.franken.de>, Sergey Mokryshev <mokr@mokr.net>, Chris Jackman <cjackNOSPAM@klatsch.org> Info on u30 firmware provided by: kris
2003-07-01 14:52:47 +00:00
static pcib_maxslots_t psycho_maxslots;
static pcib_read_config_t psycho_read_config;
static pcib_write_config_t psycho_write_config;
static pcib_route_interrupt_t psycho_route_interrupt;
- Introduce an ofw_bus kobj-interface for retrieving the OFW node and a subset ("compatible", "device_type", "model" and "name") of the standard properties in drivers for devices on Open Firmware supported busses. The standard properties "reg", "interrupts" und "address" are not covered by this interface because they are only of interest in the respective bridge code. There's a remaining standard property "status" which is unclear how to support properly but which also isn't used in FreeBSD at present. This ofw_bus kobj-interface allows to replace the various (ebus_get_node(), ofw_pci_get_node(), etc.) and partially inconsistent (central_get_type() vs. sbus_get_device_type(), etc.) existing IVAR ones with a common one. This in turn allows to simplify and remove code-duplication in drivers for devices that can hang off of more than one OFW supported bus. - Convert the sparc64 Central, EBus, FHC, PCI and SBus bus drivers and the drivers for their children to use the ofw_bus kobj-interface. The IVAR- interfaces of the Central, EBus and FHC are entirely replaced by this. The PCI bus driver used its own kobj-interface and now also uses the ofw_bus one. The IVARs special to the SBus, e.g. for retrieving the burst size, remain. Beware: this causes an ABI-breakage for modules of drivers which used the IVAR-interfaces, i.e. esp(4), hme(4), isp(4) and uart(4), which need to be recompiled. The style-inconsistencies introduced in some of the bus drivers will be fixed by tmm@ in a generic clean-up of the respective drivers later (he requested to add the changes in the "new" style). - Convert the powerpc MacIO bus driver and the drivers for its children to use the ofw_bus kobj-interface. This invloves removing the IVARs related to the "reg" property which were unused and a leftover from the NetBSD origini of the code. There's no ABI-breakage caused by this because none of these driver are currently built as modules. There are other powerpc bus drivers which can be converted to the ofw_bus kobj-interface, e.g. the PCI bus driver, which should be done together with converting powerpc to use the OFW PCI code from sparc64. - Make the SBus and FHC front-end of zs(4) and the sparc64 eeprom(4) take advantage of the ofw_bus kobj-interface and simplify them a bit. Reviewed by: grehan, tmm Approved by: re (scottl) Discussed with: tmm Tested with: Sun AX1105, AXe, Ultra 2, Ultra 60; PPC cross-build on i386
2004-08-12 17:41:33 +00:00
static ofw_bus_get_node_t psycho_get_node;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
static device_method_t psycho_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, psycho_probe),
DEVMETHOD(device_attach, psycho_attach),
- Register the generic implementations for the device shutdown, suspend and resume methods so these events propagate through the device driver hierarchy. - In dma(4) enable the chaining of the DMA engine interrupt handler for the LANCE devices via a dma_setup_intr(). This was commented out before as I was unsure whether I'd use it but this is probably cleaner than fiddling with the DMA engine interrupt in the LANCE driver directly. - In ebus_setup_dinfo() free 'intrs' instead of 'reg' twice in case setting up a child fails due to routing one of its interrupts fails. [1] Found by: Coverity Prevent [1] MFC after: 3 days
2006-01-26 21:14:32 +00:00
DEVMETHOD(device_shutdown, bus_generic_shutdown),
DEVMETHOD(device_suspend, bus_generic_suspend),
DEVMETHOD(device_resume, bus_generic_resume),
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
/* Bus interface */
DEVMETHOD(bus_print_child, bus_generic_print_child),
DEVMETHOD(bus_read_ivar, psycho_read_ivar),
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
DEVMETHOD(bus_setup_intr, psycho_setup_intr),
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
DEVMETHOD(bus_teardown_intr, psycho_teardown_intr),
DEVMETHOD(bus_alloc_resource, psycho_alloc_resource),
DEVMETHOD(bus_activate_resource, psycho_activate_resource),
DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource),
DEVMETHOD(bus_release_resource, psycho_release_resource),
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
2007-03-07 21:13:51 +00:00
DEVMETHOD(bus_get_dma_tag, psycho_get_dma_tag),
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
/* pcib interface */
DEVMETHOD(pcib_maxslots, psycho_maxslots),
DEVMETHOD(pcib_read_config, psycho_read_config),
DEVMETHOD(pcib_write_config, psycho_write_config),
DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt),
- Introduce an ofw_bus kobj-interface for retrieving the OFW node and a subset ("compatible", "device_type", "model" and "name") of the standard properties in drivers for devices on Open Firmware supported busses. The standard properties "reg", "interrupts" und "address" are not covered by this interface because they are only of interest in the respective bridge code. There's a remaining standard property "status" which is unclear how to support properly but which also isn't used in FreeBSD at present. This ofw_bus kobj-interface allows to replace the various (ebus_get_node(), ofw_pci_get_node(), etc.) and partially inconsistent (central_get_type() vs. sbus_get_device_type(), etc.) existing IVAR ones with a common one. This in turn allows to simplify and remove code-duplication in drivers for devices that can hang off of more than one OFW supported bus. - Convert the sparc64 Central, EBus, FHC, PCI and SBus bus drivers and the drivers for their children to use the ofw_bus kobj-interface. The IVAR- interfaces of the Central, EBus and FHC are entirely replaced by this. The PCI bus driver used its own kobj-interface and now also uses the ofw_bus one. The IVARs special to the SBus, e.g. for retrieving the burst size, remain. Beware: this causes an ABI-breakage for modules of drivers which used the IVAR-interfaces, i.e. esp(4), hme(4), isp(4) and uart(4), which need to be recompiled. The style-inconsistencies introduced in some of the bus drivers will be fixed by tmm@ in a generic clean-up of the respective drivers later (he requested to add the changes in the "new" style). - Convert the powerpc MacIO bus driver and the drivers for its children to use the ofw_bus kobj-interface. This invloves removing the IVARs related to the "reg" property which were unused and a leftover from the NetBSD origini of the code. There's no ABI-breakage caused by this because none of these driver are currently built as modules. There are other powerpc bus drivers which can be converted to the ofw_bus kobj-interface, e.g. the PCI bus driver, which should be done together with converting powerpc to use the OFW PCI code from sparc64. - Make the SBus and FHC front-end of zs(4) and the sparc64 eeprom(4) take advantage of the ofw_bus kobj-interface and simplify them a bit. Reviewed by: grehan, tmm Approved by: re (scottl) Discussed with: tmm Tested with: Sun AX1105, AXe, Ultra 2, Ultra 60; PPC cross-build on i386
2004-08-12 17:41:33 +00:00
/* ofw_bus interface */
DEVMETHOD(ofw_bus_get_node, psycho_get_node),
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
KOBJMETHOD_END
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
};
static devclass_t psycho_devclass;
- Add the PCI side of the HOST-PCI bridge itself to the bus. This is required by the X.Org PCI domains code and additionally needs a workaround for Hummingbird and Sabre bridges as these don't allow their config headers to be read at any width, which is an unusual behavior. - In psycho(4) take advantage of DEFINE_CLASS_0 and use more appropriate types for some softc members. MFC after: 3 days
2007-11-30 23:02:42 +00:00
DEFINE_CLASS_0(pcib, psycho_driver, psycho_methods,
sizeof(struct psycho_softc));
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0);
- Move ofw_pci_alloc_busno() to the ofw_pci KOBJ interface, allowing the driver for the host-PCI-bridge to indicate that reenumeration of the PCI busses isn't supported by returning -1 instead of a valid PCI bus number. This is needed in order support both Tomatillo, which don't support reenumeration and thus are apparently intended to be used for independently numbered PCI domains only, and Psycho bridges, whose busses need to be reenumerated on at least some E450, without the #ifndef currently used for sun4v in order to support multiple independently PCI domains. The actual allocation/incrementation of the PCI bus numbers is now done in psycho(4), though it no longer establish a mapping between bus numbers and device nodes like ofw_pci_alloc_busno() did as that functionality wasn't used (but can easily brought back if really needed). The now no longer used sys/sparc64/pci/ofw_pci.c is also removed from sys/conf/files.sun4v as ofw_pci_alloc_busno() wasn't used there in the first place. - In ofw_pci_default_{adjust_busrange,intr_pending}() sanity check that the device has a parent before passing it on. - Make psycho_softcs static to sys/sparc64/pci/psycho.c as it's not used outside of that module. - In sys/sparc64/pci/ofw_pcib_subr.c remove the superfluous inclusion of opt_global.h and correct the debug output for adjusting the subordinate bus number.
2007-06-18 21:49:42 +00:00
static SLIST_HEAD(, psycho_softc) psycho_softcs =
Use a linked list to keep the psycho softcs instead of a statically sized array. While being there, deuglify the psycho pair detection loop which became quite awkward in a previous code reorganization.
2002-10-16 17:03:36 +00:00
SLIST_HEAD_INITIALIZER(psycho_softcs);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
static const struct intr_controller psycho_ic = {
psycho_intr_enable,
psycho_intr_disable,
o Rename ic_eoi to ic_clear to emphasize the functions it points don't send and EOI which works like on amd64/i386 and blocks all interrupts on the relevant interrupt controller. o Replace the post_filter and post_inthread hooks registered when creating the interrupt events with just ic_clear as on sparc64 we don't need to do any disable->EOI->enable dance to unblock all but the relevant interrupt while running the filter or handler; just not clearing the interrupt already has the same effect. o Merge from amd64/i386: - Split the intr_table_lock into an sx lock used for most things, and a spin lock to protect intrcnt_index. - Add support for binding interrupts to CPUs, including for the bus_bind_intr(9) interface, a assign_cpu hook and initially shuffling interrupts arround in a round-robin fashion. Reviewed by: jhb MFC after: 1 month
2008-04-23 20:04:38 +00:00
psycho_intr_assign,
psycho_intr_clear
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
};
struct psycho_icarg {
struct psycho_softc *pica_sc;
bus_addr_t pica_map;
bus_addr_t pica_clr;
};
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
struct psycho_dma_sync {
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
struct psycho_softc *pds_sc;
driver_filter_t *pds_handler; /* handler to call */
void *pds_arg; /* argument for the handler */
void *pds_cookie; /* parent bus int. cookie */
device_t pds_ppb; /* farest PCI-PCI bridge */
uint8_t pds_bus; /* bus of farest PCI device */
uint8_t pds_slot; /* slot of farest PCI device */
uint8_t pds_func; /* func. of farest PCI device */
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
};
#define PSYCHO_READ8(sc, off) \
- Use the newly introduced pcib_mtx spin lock to lock psycho_ce(), allowing it to be a filter/"fast" handler. Locking the interrupt handlers with a spin lock is mainly a requirement in schizo(4) but as we ought to register the spin lock anyway it should not hurt to take advantage of it in psycho(4). - Pass both a driver_filter_t and a driver_intr_t argument to psycho_set_intr(), allowing to get rid of the FAST interrupt flag hack. - Don't register the over-temperature interrupt handler as filter/ "fast" handler so shutdown_nice() can acquire the process lock. - Use bus_{read,write}_8() instead of bus_space_{read,write}_8() in order to get rid of sc_bushandle and sc_bustag in the softc. - Correct the debug output for adjusting the subordinate bus number. - Remove the banal and outdated above psycho_filter_stub(). - Fix some white space nits.
2007-06-16 23:46:41 +00:00
bus_read_8((sc)->sc_mem_res, (off))
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
#define PSYCHO_WRITE8(sc, off, v) \
- Use the newly introduced pcib_mtx spin lock to lock psycho_ce(), allowing it to be a filter/"fast" handler. Locking the interrupt handlers with a spin lock is mainly a requirement in schizo(4) but as we ought to register the spin lock anyway it should not hurt to take advantage of it in psycho(4). - Pass both a driver_filter_t and a driver_intr_t argument to psycho_set_intr(), allowing to get rid of the FAST interrupt flag hack. - Don't register the over-temperature interrupt handler as filter/ "fast" handler so shutdown_nice() can acquire the process lock. - Use bus_{read,write}_8() instead of bus_space_{read,write}_8() in order to get rid of sc_bushandle and sc_bustag in the softc. - Correct the debug output for adjusting the subordinate bus number. - Remove the banal and outdated above psycho_filter_stub(). - Fix some white space nits.
2007-06-16 23:46:41 +00:00
bus_write_8((sc)->sc_mem_res, (off), (v))
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
#define PCICTL_READ8(sc, off) \
PSYCHO_READ8((sc), (sc)->sc_pcictl + (off))
#define PCICTL_WRITE8(sc, off, v) \
PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v))
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
/*
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
* "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
* single PCI bus and does not have a streaming buffer. It often has an APB
* (advanced PCI bridge) connected to it, which was designed specifically for
* the IIi. The APB let's the IIi handle two independednt PCI buses, and
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
* appears as two "Simba"'s underneath the Sabre.
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
*
- Improve the comment regarding the workaround for the E250 interrupt map bug by explaining what the problem is and how the workaround works. - Fix some cosmetics nits, mainly properly terminate sentences in comments, which I missed when backporting the style changes to psycho(4) in psycho.c rev. 1.54 due to lack of corresponding code. - The "USIIe version of the Sabre bridge" actually is termed "Hummingbird"; name it as such in comments and messages.
2005-12-03 13:08:05 +00:00
* "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's
* basically the same as Sabre but without an APB underneath it.
*
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
* "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA bus
* and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while
* "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You
* will usually find a "Psycho+" since I don't think the original "Psycho"
Add a workaround for quirky PCI devices that set the intpin register to 0, but use this mechanism to generate interrupts. Preserve the child device when setting up and tearing down interrupts. Some style nits.
2001-12-21 21:35:47 +00:00
* ever shipped, and if it did it would be in the U30.
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
*
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
* Each "Psycho" PCI bus appears as a separate OFW node, but since they are
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
* both part of the same IC, they only have a single register space. As such,
* they need to be configured together, even though the autoconfiguration will
* attach them separately.
*
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
* On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
* as pci1 and pci2, although they have been implemented with other PCI bus
* numbers on some machines.
*
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
* On UltraII machines, there can be any number of "Psycho+" ICs, each
Add a workaround for quirky PCI devices that set the intpin register to 0, but use this mechanism to generate interrupts. Preserve the child device when setting up and tearing down interrupts. Some style nits.
2001-12-21 21:35:47 +00:00
* providing two PCI buses.
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
*/
o break newbus api: add a new argument of type driver_filter_t to bus_setup_intr() o add an int return code to all fast handlers o retire INTR_FAST/IH_FAST For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current Reviewed by: many Approved by: re@
2007-02-23 12:19:07 +00:00
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
#define OFW_PCI_TYPE "pci"
Add "pci108e,8000" (psycho) and "pci108e,a000" (US-IIi sabre) to the list of recognized compat properties. This should make the psycho driver attach properly on SPARCengine Ultra AX machines. Switch to a table-driven logic to recognize the ID's, since their number is now large enough to justify this. These changes are analogous to those made in NetBSD r.1.35, but implemented a bit differently.
2002-10-16 17:37:50 +00:00
struct psycho_desc {
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
const char *pd_string;
int pd_mode;
const char *pd_name;
Add "pci108e,8000" (psycho) and "pci108e,a000" (US-IIi sabre) to the list of recognized compat properties. This should make the psycho driver attach properly on SPARCengine Ultra AX machines. Switch to a table-driven logic to recognize the ID's, since their number is now large enough to justify this. These changes are analogous to those made in NetBSD r.1.35, but implemented a bit differently.
2002-10-16 17:37:50 +00:00
};
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
static const struct psycho_desc const psycho_compats[] = {
Add "pci108e,8000" (psycho) and "pci108e,a000" (US-IIi sabre) to the list of recognized compat properties. This should make the psycho driver attach properly on SPARCengine Ultra AX machines. Switch to a table-driven logic to recognize the ID's, since their number is now large enough to justify this. These changes are analogous to those made in NetBSD r.1.35, but implemented a bit differently.
2002-10-16 17:37:50 +00:00
{ "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" },
- Improve the comment regarding the workaround for the E250 interrupt map bug by explaining what the problem is and how the workaround works. - Fix some cosmetics nits, mainly properly terminate sentences in comments, which I missed when backporting the style changes to psycho(4) in psycho.c rev. 1.54 due to lack of corresponding code. - The "USIIe version of the Sabre bridge" actually is termed "Hummingbird"; name it as such in comments and messages.
2005-12-03 13:08:05 +00:00
{ "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" },
{ "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" },
Add "pci108e,8000" (psycho) and "pci108e,a000" (US-IIi sabre) to the list of recognized compat properties. This should make the psycho driver attach properly on SPARCengine Ultra AX machines. Switch to a table-driven logic to recognize the ID's, since their number is now large enough to justify this. These changes are analogous to those made in NetBSD r.1.35, but implemented a bit differently.
2002-10-16 17:37:50 +00:00
{ NULL, 0, NULL }
};
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
static const struct psycho_desc const psycho_models[] = {
Add "pci108e,8000" (psycho) and "pci108e,a000" (US-IIi sabre) to the list of recognized compat properties. This should make the psycho driver attach properly on SPARCengine Ultra AX machines. Switch to a table-driven logic to recognize the ID's, since their number is now large enough to justify this. These changes are analogous to those made in NetBSD r.1.35, but implemented a bit differently.
2002-10-16 17:37:50 +00:00
{ "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" },
{ "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" },
{ NULL, 0, NULL }
};
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
static const struct psycho_desc *
psycho_find_desc(const struct psycho_desc *table, const char *string)
Add "pci108e,8000" (psycho) and "pci108e,a000" (US-IIi sabre) to the list of recognized compat properties. This should make the psycho driver attach properly on SPARCengine Ultra AX machines. Switch to a table-driven logic to recognize the ID's, since their number is now large enough to justify this. These changes are analogous to those made in NetBSD r.1.35, but implemented a bit differently.
2002-10-16 17:37:50 +00:00
{
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
const struct psycho_desc *desc;
Add "pci108e,8000" (psycho) and "pci108e,a000" (US-IIi sabre) to the list of recognized compat properties. This should make the psycho driver attach properly on SPARCengine Ultra AX machines. Switch to a table-driven logic to recognize the ID's, since their number is now large enough to justify this. These changes are analogous to those made in NetBSD r.1.35, but implemented a bit differently.
2002-10-16 17:37:50 +00:00
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
2007-03-07 21:13:51 +00:00
if (string == NULL)
return (NULL);
for (desc = table; desc->pd_string != NULL; desc++)
Add "pci108e,8000" (psycho) and "pci108e,a000" (US-IIi sabre) to the list of recognized compat properties. This should make the psycho driver attach properly on SPARCengine Ultra AX machines. Switch to a table-driven logic to recognize the ID's, since their number is now large enough to justify this. These changes are analogous to those made in NetBSD r.1.35, but implemented a bit differently.
2002-10-16 17:37:50 +00:00
if (strcmp(desc->pd_string, string) == 0)
return (desc);
return (NULL);
}
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
static const struct psycho_desc *
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
2007-03-07 21:13:51 +00:00
psycho_get_desc(device_t dev)
Add "pci108e,8000" (psycho) and "pci108e,a000" (US-IIi sabre) to the list of recognized compat properties. This should make the psycho driver attach properly on SPARCengine Ultra AX machines. Switch to a table-driven logic to recognize the ID's, since their number is now large enough to justify this. These changes are analogous to those made in NetBSD r.1.35, but implemented a bit differently.
2002-10-16 17:37:50 +00:00
{
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
const struct psycho_desc *rv;
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
2007-03-07 21:13:51 +00:00
rv = psycho_find_desc(psycho_models, ofw_bus_get_model(dev));
if (rv == NULL)
rv = psycho_find_desc(psycho_compats, ofw_bus_get_compat(dev));
Add "pci108e,8000" (psycho) and "pci108e,a000" (US-IIi sabre) to the list of recognized compat properties. This should make the psycho driver attach properly on SPARCengine Ultra AX machines. Switch to a table-driven logic to recognize the ID's, since their number is now large enough to justify this. These changes are analogous to those made in NetBSD r.1.35, but implemented a bit differently.
2002-10-16 17:37:50 +00:00
return (rv);
}
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
static int
psycho_probe(device_t dev)
{
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
const char *dtype;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
2007-03-07 21:13:51 +00:00
dtype = ofw_bus_get_type(dev);
if (dtype != NULL && strcmp(dtype, OFW_PCI_TYPE) == 0 &&
psycho_get_desc(dev) != NULL) {
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
device_set_desc(dev, "U2P UPA-PCI bridge");
return (0);
}
return (ENXIO);
}
static int
psycho_attach(device_t dev)
{
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
char name[sizeof("pci108e,1000")];
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
struct psycho_icarg *pica;
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
struct psycho_softc *asc, *sc, *osc;
- Move the declaration of struct upa_ranges and the UPA_RANGE_* macros from sys/sparc64/include/ofw_upa.h to sys/sparc64/pci/ofw_pci.h and rename them to struct ofw_pci_ranges and OFW_PCI_RANGE_* respectively. This ranges struct only applies to host-PCI bridges but no to other bridges found on UPA. At the same time it applies to all host-PCI bridges regardless of whether the interconnection bus is Fireplane/ Safari, JBus or UPA. - While here rename the PCI_CS_* macros in sys/sparc64/pci/ofw_pci.h to OFW_PCI_CS_* in order to be consistent and change this header to use uintXX_t instead of u_intXX_t.
2005-12-03 19:52:20 +00:00
struct ofw_pci_ranges *range;
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
const struct psycho_desc *desc;
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
bus_addr_t intrclr, intrmap;
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
uint64_t csr, dr;
- Add the PCI side of the HOST-PCI bridge itself to the bus. This is required by the X.Org PCI domains code and additionally needs a workaround for Hummingbird and Sabre bridges as these don't allow their config headers to be read at any width, which is an unusual behavior. - In psycho(4) take advantage of DEFINE_CLASS_0 and use more appropriate types for some softc members. MFC after: 3 days
2007-11-30 23:02:42 +00:00
phandle_t child, node;
Announce the speed of the PCI bus for informational purpose. MFC after: 3 days
2008-08-24 16:22:04 +00:00
uint32_t dvmabase, prop, prop_array[2];
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
int32_t rev;
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
u_int rerun, ver;
int i, n;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
2007-03-07 21:13:51 +00:00
node = ofw_bus_get_node(dev);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
sc = device_get_softc(dev);
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
2007-03-07 21:13:51 +00:00
desc = psycho_get_desc(dev);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
sc->sc_node = node;
sc->sc_dev = dev;
Add "pci108e,8000" (psycho) and "pci108e,a000" (US-IIi sabre) to the list of recognized compat properties. This should make the psycho driver attach properly on SPARCengine Ultra AX machines. Switch to a table-driven logic to recognize the ID's, since their number is now large enough to justify this. These changes are analogous to those made in NetBSD r.1.35, but implemented a bit differently.
2002-10-16 17:37:50 +00:00
sc->sc_mode = desc->pd_mode;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
/*
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
* The Psycho gets three register banks:
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
* (0) per-PBM configuration and status registers
* (1) per-PBM PCI configuration space, containing only the
* PBM 256-byte PCI header
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
* (2) the shared Psycho configuration registers
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
*/
if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
i = 2;
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
2007-03-07 21:13:51 +00:00
sc->sc_pcictl =
bus_get_resource_start(dev, SYS_RES_MEMORY, 0) -
bus_get_resource_start(dev, SYS_RES_MEMORY, 2);
Fix interrupt assignment for non-builtin PCI devices on e450s. This machine uses a non-standard scheme to specify the interrupts to be assigned for devices in PCI slots; instead of giving the INO or full interrupt number (which is done for the other devices in this box), the firmware interrupt properties contain intpin numbers, which have to be swizzled as usual on PCI-PCI bridges; however, the PCI host bridge nodes have no interrupt map, so we need to guess the correct INO by slot number of the device or the closest PCI-PCI bridge leading to it, and the intpin. To do this, this fix makes the following changes: - Add a newbus method for sparc64 PCI host bridges to guess the INO, and glue code in ofw_pci_orb_callback() to invoke it based on a new quirk entry. The guessing is only done for interrupt numbers too low to contain any IGN found on e450s. - Create another new quirk entry was created to prevent mapping of EBus interrupts at PCI level; the e450 has full INOs in the interrupt properties of EBus devices, so trying to remap them could cause problems. - Set both quirk entries for e450s; remove the no-swizzle entry. - Determine the psycho half (bus A or B) a driver instance manages in psycho_attach() - Implement the new guessing method for psycho, using the slot number, psycho half and property value (intpin). Thanks go to the testers, especially Brian Denehy, who tested many kernels for me until I had found the right workaround. Tested by: Brian Denehy <B.Denehy@90east.com>, jake, fenner, Marius Strobl <marius@alchemy.franken.de>, Marian Dobre <mari@onix.ro> Approved by: re (scottl)
2003-05-30 20:48:05 +00:00
switch (sc->sc_pcictl) {
case PSR_PCICTL0:
sc->sc_half = 0;
break;
case PSR_PCICTL1:
sc->sc_half = 1;
break;
default:
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
panic("%s: bogus PCI control register location",
__func__);
cosmetic changes and style fixes
2008-08-22 20:28:19 +00:00
/* NOTREACHED */
Fix interrupt assignment for non-builtin PCI devices on e450s. This machine uses a non-standard scheme to specify the interrupts to be assigned for devices in PCI slots; instead of giving the INO or full interrupt number (which is done for the other devices in this box), the firmware interrupt properties contain intpin numbers, which have to be swizzled as usual on PCI-PCI bridges; however, the PCI host bridge nodes have no interrupt map, so we need to guess the correct INO by slot number of the device or the closest PCI-PCI bridge leading to it, and the intpin. To do this, this fix makes the following changes: - Add a newbus method for sparc64 PCI host bridges to guess the INO, and glue code in ofw_pci_orb_callback() to invoke it based on a new quirk entry. The guessing is only done for interrupt numbers too low to contain any IGN found on e450s. - Create another new quirk entry was created to prevent mapping of EBus interrupts at PCI level; the e450 has full INOs in the interrupt properties of EBus devices, so trying to remap them could cause problems. - Set both quirk entries for e450s; remove the no-swizzle entry. - Determine the psycho half (bus A or B) a driver instance manages in psycho_attach() - Implement the new guessing method for psycho, using the slot number, psycho half and property value (intpin). Thanks go to the testers, especially Brian Denehy, who tested many kernels for me until I had found the right workaround. Tested by: Brian Denehy <B.Denehy@90east.com>, jake, fenner, Marius Strobl <marius@alchemy.franken.de>, Marian Dobre <mari@onix.ro> Approved by: re (scottl)
2003-05-30 20:48:05 +00:00
}
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
} else {
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
i = 0;
Fix interrupt assignment for non-builtin PCI devices on e450s. This machine uses a non-standard scheme to specify the interrupts to be assigned for devices in PCI slots; instead of giving the INO or full interrupt number (which is done for the other devices in this box), the firmware interrupt properties contain intpin numbers, which have to be swizzled as usual on PCI-PCI bridges; however, the PCI host bridge nodes have no interrupt map, so we need to guess the correct INO by slot number of the device or the closest PCI-PCI bridge leading to it, and the intpin. To do this, this fix makes the following changes: - Add a newbus method for sparc64 PCI host bridges to guess the INO, and glue code in ofw_pci_orb_callback() to invoke it based on a new quirk entry. The guessing is only done for interrupt numbers too low to contain any IGN found on e450s. - Create another new quirk entry was created to prevent mapping of EBus interrupts at PCI level; the e450 has full INOs in the interrupt properties of EBus devices, so trying to remap them could cause problems. - Set both quirk entries for e450s; remove the no-swizzle entry. - Determine the psycho half (bus A or B) a driver instance manages in psycho_attach() - Implement the new guessing method for psycho, using the slot number, psycho half and property value (intpin). Thanks go to the testers, especially Brian Denehy, who tested many kernels for me until I had found the right workaround. Tested by: Brian Denehy <B.Denehy@90east.com>, jake, fenner, Marius Strobl <marius@alchemy.franken.de>, Marian Dobre <mari@onix.ro> Approved by: re (scottl)
2003-05-30 20:48:05 +00:00
sc->sc_pcictl = PSR_PCICTL0;
sc->sc_half = 0;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
}
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i,
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
2007-03-07 21:13:51 +00:00
(sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) |
RF_ACTIVE);
if (sc->sc_mem_res == NULL)
panic("%s: could not allocate registers", __func__);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
/*
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
* Match other Psychos that are already configured against
- Use the name returned by device_get_nameunit(9) for the name of the counter-timer timecounter so the associated SYSCTL nodes don't clash on machines having multiple U2P and U2S bridges as well as establishing a clear mapping between these bridges and their timecounter device. - Don't bother setting up a "nice" name for the IOMMU, just use the name returned by device_get_nameunit(9), too. - Fix some minor style(9) bugs. - Use __FBSDID in counter.c MFC after: 1 week
2008-05-07 21:22:15 +00:00
* the base physical address. This will be the same for a
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
* pair of devices that share register space.
*/
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
osc = NULL;
Use a linked list to keep the psycho softcs instead of a statically sized array. While being there, deuglify the psycho pair detection loop which became quite awkward in a previous code reorganization.
2002-10-16 17:03:36 +00:00
SLIST_FOREACH(asc, &psycho_softcs, sc_link) {
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
2007-03-07 21:13:51 +00:00
if (rman_get_start(asc->sc_mem_res) ==
rman_get_start(sc->sc_mem_res)) {
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
/* Found partner. */
Use a linked list to keep the psycho softcs instead of a statically sized array. While being there, deuglify the psycho pair detection loop which became quite awkward in a previous code reorganization.
2002-10-16 17:03:36 +00:00
osc = asc;
break;
}
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
}
- Use the newly introduced pcib_mtx spin lock to lock psycho_ce(), allowing it to be a filter/"fast" handler. Locking the interrupt handlers with a spin lock is mainly a requirement in schizo(4) but as we ought to register the spin lock anyway it should not hurt to take advantage of it in psycho(4). - Pass both a driver_filter_t and a driver_intr_t argument to psycho_set_intr(), allowing to get rid of the FAST interrupt flag hack. - Don't register the over-temperature interrupt handler as filter/ "fast" handler so shutdown_nice() can acquire the process lock. - Use bus_{read,write}_8() instead of bus_space_{read,write}_8() in order to get rid of sc_bushandle and sc_bustag in the softc. - Correct the debug output for adjusting the subordinate bus number. - Remove the banal and outdated above psycho_filter_stub(). - Fix some white space nits.
2007-06-16 23:46:41 +00:00
if (osc == NULL) {
sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF,
M_NOWAIT | M_ZERO);
if (sc->sc_mtx == NULL)
panic("%s: could not malloc mutex", __func__);
mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN);
} else {
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
if (sc->sc_mode != PSYCHO_MODE_PSYCHO)
panic("%s: no partner expected", __func__);
- Use the newly introduced pcib_mtx spin lock to lock psycho_ce(), allowing it to be a filter/"fast" handler. Locking the interrupt handlers with a spin lock is mainly a requirement in schizo(4) but as we ought to register the spin lock anyway it should not hurt to take advantage of it in psycho(4). - Pass both a driver_filter_t and a driver_intr_t argument to psycho_set_intr(), allowing to get rid of the FAST interrupt flag hack. - Don't register the over-temperature interrupt handler as filter/ "fast" handler so shutdown_nice() can acquire the process lock. - Use bus_{read,write}_8() instead of bus_space_{read,write}_8() in order to get rid of sc_bushandle and sc_bustag in the softc. - Correct the debug output for adjusting the subordinate bus number. - Remove the banal and outdated above psycho_filter_stub(). - Fix some white space nits.
2007-06-16 23:46:41 +00:00
if (mtx_initialized(osc->sc_mtx) == 0)
panic("%s: mutex not initialized", __func__);
sc->sc_mtx = osc->sc_mtx;
}
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
csr = PSYCHO_READ8(sc, PSR_CS);
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
ver = PSYCHO_GCSR_VERS(csr);
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
sc->sc_ign = PSYCHO_GCSR_IGN(csr);
Announce the speed of the PCI bus for informational purpose. MFC after: 3 days
2008-08-24 16:22:04 +00:00
if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1)
prop = 33000000;
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
Announce the speed of the PCI bus for informational purpose. MFC after: 3 days
2008-08-24 16:22:04 +00:00
device_printf(dev,
"%s, impl %d, version %d, IGN %#x, bus %c, %dMHz\n",
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign,
Announce the speed of the PCI bus for informational purpose. MFC after: 3 days
2008-08-24 16:22:04 +00:00
'A' + sc->sc_half, prop / 1000 / 1000);
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
/* Set up the PCI control and PCI diagnostic registers. */
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
/*
* Revision 0 EBus bridges have a bug which prevents them from
* working when bus parking is enabled.
*/
rev = -1;
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
csr = PCICTL_READ8(sc, PCR_CS);
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
csr &= ~PCICTL_ARB_PARK;
for (child = OF_child(node); child != 0; child = OF_peer(child)) {
if (OF_getprop(child, "name", name, sizeof(name)) == -1)
continue;
if ((strcmp(name, "ebus") == 0 ||
strcmp(name, "pci108e,1000") == 0) &&
OF_getprop(child, "revision-id", &rev, sizeof(rev)) > 0 &&
rev == 0)
break;
}
if (rev != 0 && OF_getproplen(node, "no-bus-parking") < 0)
csr |= PCICTL_ARB_PARK;
/* Workarounds for version specific bugs. */
dr = PCICTL_READ8(sc, PCR_DIAG);
switch (ver) {
case 0:
dr |= DIAG_RTRY_DIS;
dr &= ~DIAG_DWSYNC_DIS;
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
rerun = 0;
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
break;
case 1:
csr &= ~PCICTL_ARB_PARK;
dr |= DIAG_RTRY_DIS | DIAG_DWSYNC_DIS;
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
rerun = 0;
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
break;
default:
dr |= DIAG_DWSYNC_DIS;
dr &= ~DIAG_RTRY_DIS;
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
rerun = 1;
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
break;
}
Clear any possibly pending PCI error bits left by the firmware. These could trigger an error interrupt that we can't actually to do anything against as soon as enabling the error handlers. While at it don't bother about writing only to the write-one-to-clear bits when clearing error bits.
2008-09-18 19:45:22 +00:00
csr |= PCICTL_ERRINTEN | PCICTL_ARB_4;
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN);
#ifdef PSYCHO_DEBUG
device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n",
(unsigned long long)PCICTL_READ8(sc, PCR_CS),
(unsigned long long)csr);
#endif
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
PCICTL_WRITE8(sc, PCR_CS, csr);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
dr &= ~DIAG_ISYNC_DIS;
#ifdef PSYCHO_DEBUG
device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n",
(unsigned long long)PCICTL_READ8(sc, PCR_DIAG),
(unsigned long long)dr);
#endif
PCICTL_WRITE8(sc, PCR_DIAG, dr);
- remove some outdated comments - tweak the announce message a bit - remove '\n's from a few panic() calls - don't use the DVMA base adress the firmware reports; instead, figure it out from the appropriate register on Sabres and let the IOMMU code choose it on Psychos. This also makes the IOMMU TSB size freely selectable.
2003-01-06 16:51:06 +00:00
if (sc->sc_mode == PSYCHO_MODE_SABRE) {
Some code cleanup: - Fix some comments; remove numerous superfluous or outdated ones. - Correctly pass on the requesting device when handing requests up to the parent bus. - Use the complete device name, including unit number, to build the IOMMU instance name. - Inline a function that was only used once, and was trivial.
2004-04-25 00:30:28 +00:00
/* Use the PROM preset for now. */
- remove some outdated comments - tweak the announce message a bit - remove '\n's from a few panic() calls - don't use the DVMA base adress the firmware reports; instead, figure it out from the appropriate register on Sabres and let the IOMMU code choose it on Psychos. This also makes the IOMMU TSB size freely selectable.
2003-01-06 16:51:06 +00:00
csr = PCICTL_READ8(sc, PCR_TAS);
if (csr == 0)
- Improve the comment regarding the workaround for the E250 interrupt map bug by explaining what the problem is and how the workaround works. - Fix some cosmetics nits, mainly properly terminate sentences in comments, which I missed when backporting the style changes to psycho(4) in psycho.c rev. 1.54 due to lack of corresponding code. - The "USIIe version of the Sabre bridge" actually is termed "Hummingbird"; name it as such in comments and messages.
2005-12-03 13:08:05 +00:00
panic("%s: Hummingbird/Sabre TAS not initialized.",
__func__);
- Add a workaround (change the interrupt map mask to compare the full INO) for incorrect interrupt map entries on E250 machines. These incorrect entries caused the INO of the on-board HME to be also assigned to the second on-board NS16550 and to the on-board printer port controller. Further down the road caused hme(4) to fail to attach to the on-board HME in FreeBSD 5 and 6 as INTR_FAST and non-INTR_FAST handlers can't share the same IRQ there (it's unknown what whould happen in -CURRENT now that INTR_FAST and non-INTR_FAST handlers can share an IRQ but I'd expect funny problems with uart(4)). - Make sure there are exactly 4 PCI ranges instead of just checking that the bridge has a 'ranges' property in the OFW device tree at all. Besides the fact that currently the 64bit memory range isn't used by this driver it we can't really work with less than 4 ranges and don't have memory for more than 4 bus handles for the ranges in the softc. - Remove sc_range and sc_nrange from softc; for the bridges supported by this driver we no longer need to know the ranges besides the bus handles obtained from them once this driver is attached. That way we also can free the memory allocated for sc_range during attach again. - Remove sc_dvmabase from the softc and pass it to psycho_iommu_init() via an additional argument as we no longer need to know the DVMA base in this driver once the IOMMU is initialized. - Remove sc_dmatag from the softc, there isn't much sense in keeping the nexus dma tag around locally. PR: 88279 [1] Info from: OpenSolaris [1] Tested by: kensmith [1] MFC after: 1 month
2005-11-22 22:32:50 +00:00
dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT;
- remove some outdated comments - tweak the announce message a bit - remove '\n's from a few panic() calls - don't use the DVMA base adress the firmware reports; instead, figure it out from the appropriate register on Sabres and let the IOMMU code choose it on Psychos. This also makes the IOMMU TSB size freely selectable.
2003-01-06 16:51:06 +00:00
} else
- Add a workaround (change the interrupt map mask to compare the full INO) for incorrect interrupt map entries on E250 machines. These incorrect entries caused the INO of the on-board HME to be also assigned to the second on-board NS16550 and to the on-board printer port controller. Further down the road caused hme(4) to fail to attach to the on-board HME in FreeBSD 5 and 6 as INTR_FAST and non-INTR_FAST handlers can't share the same IRQ there (it's unknown what whould happen in -CURRENT now that INTR_FAST and non-INTR_FAST handlers can share an IRQ but I'd expect funny problems with uart(4)). - Make sure there are exactly 4 PCI ranges instead of just checking that the bridge has a 'ranges' property in the OFW device tree at all. Besides the fact that currently the 64bit memory range isn't used by this driver it we can't really work with less than 4 ranges and don't have memory for more than 4 bus handles for the ranges in the softc. - Remove sc_range and sc_nrange from softc; for the bridges supported by this driver we no longer need to know the ranges besides the bus handles obtained from them once this driver is attached. That way we also can free the memory allocated for sc_range during attach again. - Remove sc_dvmabase from the softc and pass it to psycho_iommu_init() via an additional argument as we no longer need to know the DVMA base in this driver once the IOMMU is initialized. - Remove sc_dmatag from the softc, there isn't much sense in keeping the nexus dma tag around locally. PR: 88279 [1] Info from: OpenSolaris [1] Tested by: kensmith [1] MFC after: 1 month
2005-11-22 22:32:50 +00:00
dvmabase = -1;
- remove some outdated comments - tweak the announce message a bit - remove '\n's from a few panic() calls - don't use the DVMA base adress the firmware reports; instead, figure it out from the appropriate register on Sabres and let the IOMMU code choose it on Psychos. This also makes the IOMMU TSB size freely selectable.
2003-01-06 16:51:06 +00:00
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
/* Initialize memory and I/O rmans. */
sc->sc_pci_io_rman.rm_type = RMAN_ARRAY;
sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports";
if (rman_init(&sc->sc_pci_io_rman) != 0 ||
rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0)
panic("%s: failed to set up I/O rman", __func__);
sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY;
sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory";
if (rman_init(&sc->sc_pci_mem_rman) != 0 ||
rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0)
panic("%s: failed to set up memory rman", __func__);
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
n = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range);
- Add a workaround (change the interrupt map mask to compare the full INO) for incorrect interrupt map entries on E250 machines. These incorrect entries caused the INO of the on-board HME to be also assigned to the second on-board NS16550 and to the on-board printer port controller. Further down the road caused hme(4) to fail to attach to the on-board HME in FreeBSD 5 and 6 as INTR_FAST and non-INTR_FAST handlers can't share the same IRQ there (it's unknown what whould happen in -CURRENT now that INTR_FAST and non-INTR_FAST handlers can share an IRQ but I'd expect funny problems with uart(4)). - Make sure there are exactly 4 PCI ranges instead of just checking that the bridge has a 'ranges' property in the OFW device tree at all. Besides the fact that currently the 64bit memory range isn't used by this driver it we can't really work with less than 4 ranges and don't have memory for more than 4 bus handles for the ranges in the softc. - Remove sc_range and sc_nrange from softc; for the bridges supported by this driver we no longer need to know the ranges besides the bus handles obtained from them once this driver is attached. That way we also can free the memory allocated for sc_range during attach again. - Remove sc_dvmabase from the softc and pass it to psycho_iommu_init() via an additional argument as we no longer need to know the DVMA base in this driver once the IOMMU is initialized. - Remove sc_dmatag from the softc, there isn't much sense in keeping the nexus dma tag around locally. PR: 88279 [1] Info from: OpenSolaris [1] Tested by: kensmith [1] MFC after: 1 month
2005-11-22 22:32:50 +00:00
/*
- Use the name returned by device_get_nameunit(9) for the name of the counter-timer timecounter so the associated SYSCTL nodes don't clash on machines having multiple U2P and U2S bridges as well as establishing a clear mapping between these bridges and their timecounter device. - Don't bother setting up a "nice" name for the IOMMU, just use the name returned by device_get_nameunit(9), too. - Fix some minor style(9) bugs. - Use __FBSDID in counter.c MFC after: 1 week
2008-05-07 21:22:15 +00:00
* Make sure that the expected ranges are present. The
* OFW_PCI_CS_MEM64 one is not currently used though.
- Add a workaround (change the interrupt map mask to compare the full INO) for incorrect interrupt map entries on E250 machines. These incorrect entries caused the INO of the on-board HME to be also assigned to the second on-board NS16550 and to the on-board printer port controller. Further down the road caused hme(4) to fail to attach to the on-board HME in FreeBSD 5 and 6 as INTR_FAST and non-INTR_FAST handlers can't share the same IRQ there (it's unknown what whould happen in -CURRENT now that INTR_FAST and non-INTR_FAST handlers can share an IRQ but I'd expect funny problems with uart(4)). - Make sure there are exactly 4 PCI ranges instead of just checking that the bridge has a 'ranges' property in the OFW device tree at all. Besides the fact that currently the 64bit memory range isn't used by this driver it we can't really work with less than 4 ranges and don't have memory for more than 4 bus handles for the ranges in the softc. - Remove sc_range and sc_nrange from softc; for the bridges supported by this driver we no longer need to know the ranges besides the bus handles obtained from them once this driver is attached. That way we also can free the memory allocated for sc_range during attach again. - Remove sc_dvmabase from the softc and pass it to psycho_iommu_init() via an additional argument as we no longer need to know the DVMA base in this driver once the IOMMU is initialized. - Remove sc_dmatag from the softc, there isn't much sense in keeping the nexus dma tag around locally. PR: 88279 [1] Info from: OpenSolaris [1] Tested by: kensmith [1] MFC after: 1 month
2005-11-22 22:32:50 +00:00
*/
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
if (n != PSYCHO_NRANGE)
- Add a workaround (change the interrupt map mask to compare the full INO) for incorrect interrupt map entries on E250 machines. These incorrect entries caused the INO of the on-board HME to be also assigned to the second on-board NS16550 and to the on-board printer port controller. Further down the road caused hme(4) to fail to attach to the on-board HME in FreeBSD 5 and 6 as INTR_FAST and non-INTR_FAST handlers can't share the same IRQ there (it's unknown what whould happen in -CURRENT now that INTR_FAST and non-INTR_FAST handlers can share an IRQ but I'd expect funny problems with uart(4)). - Make sure there are exactly 4 PCI ranges instead of just checking that the bridge has a 'ranges' property in the OFW device tree at all. Besides the fact that currently the 64bit memory range isn't used by this driver it we can't really work with less than 4 ranges and don't have memory for more than 4 bus handles for the ranges in the softc. - Remove sc_range and sc_nrange from softc; for the bridges supported by this driver we no longer need to know the ranges besides the bus handles obtained from them once this driver is attached. That way we also can free the memory allocated for sc_range during attach again. - Remove sc_dvmabase from the softc and pass it to psycho_iommu_init() via an additional argument as we no longer need to know the DVMA base in this driver once the IOMMU is initialized. - Remove sc_dmatag from the softc, there isn't much sense in keeping the nexus dma tag around locally. PR: 88279 [1] Info from: OpenSolaris [1] Tested by: kensmith [1] MFC after: 1 month
2005-11-22 22:32:50 +00:00
panic("%s: unsupported number of ranges", __func__);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
/*
* Find the addresses of the various bus spaces.
* There should not be multiple ones of one kind.
* The physical start addresses of the ranges are the configuration,
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
* memory and I/O handles.
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
*/
- Add a workaround (change the interrupt map mask to compare the full INO) for incorrect interrupt map entries on E250 machines. These incorrect entries caused the INO of the on-board HME to be also assigned to the second on-board NS16550 and to the on-board printer port controller. Further down the road caused hme(4) to fail to attach to the on-board HME in FreeBSD 5 and 6 as INTR_FAST and non-INTR_FAST handlers can't share the same IRQ there (it's unknown what whould happen in -CURRENT now that INTR_FAST and non-INTR_FAST handlers can share an IRQ but I'd expect funny problems with uart(4)). - Make sure there are exactly 4 PCI ranges instead of just checking that the bridge has a 'ranges' property in the OFW device tree at all. Besides the fact that currently the 64bit memory range isn't used by this driver it we can't really work with less than 4 ranges and don't have memory for more than 4 bus handles for the ranges in the softc. - Remove sc_range and sc_nrange from softc; for the bridges supported by this driver we no longer need to know the ranges besides the bus handles obtained from them once this driver is attached. That way we also can free the memory allocated for sc_range during attach again. - Remove sc_dvmabase from the softc and pass it to psycho_iommu_init() via an additional argument as we no longer need to know the DVMA base in this driver once the IOMMU is initialized. - Remove sc_dmatag from the softc, there isn't much sense in keeping the nexus dma tag around locally. PR: 88279 [1] Info from: OpenSolaris [1] Tested by: kensmith [1] MFC after: 1 month
2005-11-22 22:32:50 +00:00
for (n = 0; n < PSYCHO_NRANGE; n++) {
- Move the declaration of struct upa_ranges and the UPA_RANGE_* macros from sys/sparc64/include/ofw_upa.h to sys/sparc64/pci/ofw_pci.h and rename them to struct ofw_pci_ranges and OFW_PCI_RANGE_* respectively. This ranges struct only applies to host-PCI bridges but no to other bridges found on UPA. At the same time it applies to all host-PCI bridges regardless of whether the interconnection bus is Fireplane/ Safari, JBus or UPA. - While here rename the PCI_CS_* macros in sys/sparc64/pci/ofw_pci.h to OFW_PCI_CS_* in order to be consistent and change this header to use uintXX_t instead of u_intXX_t.
2005-12-03 19:52:20 +00:00
i = OFW_PCI_RANGE_CS(&range[n]);
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
if (sc->sc_pci_bh[i] != 0)
panic("%s: duplicate range for space %d", __func__, i);
- Move the declaration of struct upa_ranges and the UPA_RANGE_* macros from sys/sparc64/include/ofw_upa.h to sys/sparc64/pci/ofw_pci.h and rename them to struct ofw_pci_ranges and OFW_PCI_RANGE_* respectively. This ranges struct only applies to host-PCI bridges but no to other bridges found on UPA. At the same time it applies to all host-PCI bridges regardless of whether the interconnection bus is Fireplane/ Safari, JBus or UPA. - While here rename the PCI_CS_* macros in sys/sparc64/pci/ofw_pci.h to OFW_PCI_CS_* in order to be consistent and change this header to use uintXX_t instead of u_intXX_t.
2005-12-03 19:52:20 +00:00
sc->sc_pci_bh[i] = OFW_PCI_RANGE_PHYS(&range[n]);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
}
- Add a workaround (change the interrupt map mask to compare the full INO) for incorrect interrupt map entries on E250 machines. These incorrect entries caused the INO of the on-board HME to be also assigned to the second on-board NS16550 and to the on-board printer port controller. Further down the road caused hme(4) to fail to attach to the on-board HME in FreeBSD 5 and 6 as INTR_FAST and non-INTR_FAST handlers can't share the same IRQ there (it's unknown what whould happen in -CURRENT now that INTR_FAST and non-INTR_FAST handlers can share an IRQ but I'd expect funny problems with uart(4)). - Make sure there are exactly 4 PCI ranges instead of just checking that the bridge has a 'ranges' property in the OFW device tree at all. Besides the fact that currently the 64bit memory range isn't used by this driver it we can't really work with less than 4 ranges and don't have memory for more than 4 bus handles for the ranges in the softc. - Remove sc_range and sc_nrange from softc; for the bridges supported by this driver we no longer need to know the ranges besides the bus handles obtained from them once this driver is attached. That way we also can free the memory allocated for sc_range during attach again. - Remove sc_dvmabase from the softc and pass it to psycho_iommu_init() via an additional argument as we no longer need to know the DVMA base in this driver once the IOMMU is initialized. - Remove sc_dmatag from the softc, there isn't much sense in keeping the nexus dma tag around locally. PR: 88279 [1] Info from: OpenSolaris [1] Tested by: kensmith [1] MFC after: 1 month
2005-11-22 22:32:50 +00:00
free(range, M_OFWPROP);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
/* Register the softc, this is needed for paired Psychos. */
Use a linked list to keep the psycho softcs instead of a statically sized array. While being there, deuglify the psycho pair detection loop which became quite awkward in a previous code reorganization.
2002-10-16 17:03:36 +00:00
SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link);
- Register the PCI bus error interrupt handler according to which half of the bridge (PCI bus A or B) we are attaching to rather than registering both handlers at once when attaching to the first half we encounter. This is a bit cleaner as it corresponds to which PCI bus error interrupt actually is assigned to the respective half by the OFW and allows to collapse both PCI bus error interrupt handlers into one function easily. - Use the actual RID of the respective interrupt resource as index into sc_irq_res and also use it when allocating the resource. For now this is a bit cleaner and will be mandatory later on. - According to OpenSolaris the spare hardware interrupt is used as the over-temperature interrupt in systems with Psycho bridges. Unlike as with the SBus-based workstations I didn't manage to trigger it when covering the fan outlets of an U60 but better be safe than sorry and register a handler anyway. MFC after: 1 month
2005-12-03 16:36:54 +00:00
/*
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
* If we're a Hummingbird/Sabre or the first of a pair of Psychos
* to arrive here, do the interrupt setup and start up the IOMMU.
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
*/
if (osc == NULL) {
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
/*
* Hunt through all the interrupt mapping regs and register
* our interrupt controller for the corresponding interrupt
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
* vectors. We do this early in order to be able to catch
* stray interrupts.
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
*/
for (n = 0; n <= PSYCHO_MAX_INO; n++) {
if (psycho_find_intrmap(sc, n, &intrmap, &intrclr,
NULL) == 0)
continue;
pica = malloc(sizeof(*pica), M_DEVBUF, M_NOWAIT);
if (pica == NULL)
panic("%s: could not allocate interrupt "
"controller argument", __func__);
pica->pica_sc = sc;
pica->pica_map = intrmap;
pica->pica_clr = intrclr;
#ifdef PSYCHO_DEBUG
/*
* Enable all interrupts and clear all interrupt
- Use the name returned by device_get_nameunit(9) for the name of the counter-timer timecounter so the associated SYSCTL nodes don't clash on machines having multiple U2P and U2S bridges as well as establishing a clear mapping between these bridges and their timecounter device. - Don't bother setting up a "nice" name for the IOMMU, just use the name returned by device_get_nameunit(9), too. - Fix some minor style(9) bugs. - Use __FBSDID in counter.c MFC after: 1 week
2008-05-07 21:22:15 +00:00
* states. This aids the debugging of interrupt
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
* routing problems.
*/
device_printf(dev,
"intr map (INO %d, %s) %#lx: %#lx, clr: %#lx\n",
n, intrmap <= PSR_PCIB3_INT_MAP ? "PCI" : "OBIO",
(u_long)intrmap, (u_long)PSYCHO_READ8(sc, intrmap),
(u_long)intrclr);
PSYCHO_WRITE8(sc, intrmap, INTMAP_VEC(sc->sc_ign, n));
PSYCHO_WRITE8(sc, intrclr, 0);
PSYCHO_WRITE8(sc, intrmap,
INTMAP_ENABLE(INTMAP_VEC(sc->sc_ign, n),
PCPU_GET(mid)));
#endif
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
i = intr_controller_register(INTMAP_VEC(sc->sc_ign, n),
&psycho_ic, pica);
if (i != 0)
device_printf(dev, "could not register "
"interrupt controller for INO %d (%d)\n",
n, i);
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
}
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
- Use the name returned by device_get_nameunit(9) for the name of the counter-timer timecounter so the associated SYSCTL nodes don't clash on machines having multiple U2P and U2S bridges as well as establishing a clear mapping between these bridges and their timecounter device. - Don't bother setting up a "nice" name for the IOMMU, just use the name returned by device_get_nameunit(9), too. - Fix some minor style(9) bugs. - Use __FBSDID in counter.c MFC after: 1 week
2008-05-07 21:22:15 +00:00
sparc64_counter_init(device_get_nameunit(dev),
rman_get_bustag(sc->sc_mem_res),
- Use the newly introduced pcib_mtx spin lock to lock psycho_ce(), allowing it to be a filter/"fast" handler. Locking the interrupt handlers with a spin lock is mainly a requirement in schizo(4) but as we ought to register the spin lock anyway it should not hurt to take advantage of it in psycho(4). - Pass both a driver_filter_t and a driver_intr_t argument to psycho_set_intr(), allowing to get rid of the FAST interrupt flag hack. - Don't register the over-temperature interrupt handler as filter/ "fast" handler so shutdown_nice() can acquire the process lock. - Use bus_{read,write}_8() instead of bus_space_{read,write}_8() in order to get rid of sc_bushandle and sc_bustag in the softc. - Correct the debug output for adjusting the subordinate bus number. - Remove the banal and outdated above psycho_filter_stub(). - Fix some white space nits.
2007-06-16 23:46:41 +00:00
rman_get_bushandle(sc->sc_mem_res), PSR_TC0);
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
/*
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
* Set up IOMMU and PCI configuration if we're the first
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
* of a pair of Psychos to arrive here or a Hummingbird
* or Sabre.
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
*
* We should calculate a TSB size based on amount of RAM
Fix typos, mostly s/ an / a / where appropriate and a few s/an/and/ Add FreeBSD Id tag where missing.
2002-12-30 21:18:15 +00:00
* and number of bus controllers and number and type of
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
* child devices.
*
* For the moment, 32KB should be more than enough.
*/
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF,
- Divorce the IOTSBs, which so far where handled via a global list instead of per IOMMU, so we no longer need to program all of them identically in systems having multiple IOMMUs. This continues the rototilling of the nexus(4) done about 5 months ago, which amongst others changed nexus(4) and the drivers for host-to-foo bridges to provide bus_get_dma_tag methods, allowing to handle DMA tags in a hierarchical way and to link them with devices. This still doesn't move the silicon bug workarounds for Sabre (and in the uncommitted schizo(4) for Tomatillo) bridges into special bus_dma_tag_create() and bus_dmamap_sync() methods though, as w/o fully newbus'ified bus_dma_tag_create() and bus_dma_tag_destroy() this still requires too much hackery, i.e. per-child parent DMA tags in the parent driver. - Let the host-to-foo drivers supply the maximum physical address of the IOMMU accompanying the bridges. Previously iommu(4) hard- coded an upper limit of 16GB, which actually only applies to the IOMMUs of the Hummingbird and Sabre bridges. The Psycho variants as well as the U2S in fact can can translate to up to 2TB, i.e. translate to 41-bit physical addresses. According to the recently available Tomatillo documentation these bridges even translate to 43-bit physical addresses and hints at the Schizo bridges doing 43 bits as well. This fixes the issue the FreeBSD 6.0 todo list item "Max RAM on sparc64" was refering to and pretty much obsoletes the lack of support for bounce buffers on sparc64. Thanks to Nathan Whitehorn for pointing me at the Tomatillo manual. Approved by: re (kensmith)
2007-08-05 11:56:44 +00:00
M_NOWAIT | M_ZERO);
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
if (sc->sc_is == NULL)
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
panic("%s: malloc iommu_state failed", __func__);
- Divorce the IOTSBs, which so far where handled via a global list instead of per IOMMU, so we no longer need to program all of them identically in systems having multiple IOMMUs. This continues the rototilling of the nexus(4) done about 5 months ago, which amongst others changed nexus(4) and the drivers for host-to-foo bridges to provide bus_get_dma_tag methods, allowing to handle DMA tags in a hierarchical way and to link them with devices. This still doesn't move the silicon bug workarounds for Sabre (and in the uncommitted schizo(4) for Tomatillo) bridges into special bus_dma_tag_create() and bus_dmamap_sync() methods though, as w/o fully newbus'ified bus_dma_tag_create() and bus_dma_tag_destroy() this still requires too much hackery, i.e. per-child parent DMA tags in the parent driver. - Let the host-to-foo drivers supply the maximum physical address of the IOMMU accompanying the bridges. Previously iommu(4) hard- coded an upper limit of 16GB, which actually only applies to the IOMMUs of the Hummingbird and Sabre bridges. The Psycho variants as well as the U2S in fact can can translate to up to 2TB, i.e. translate to 41-bit physical addresses. According to the recently available Tomatillo documentation these bridges even translate to 43-bit physical addresses and hints at the Schizo bridges doing 43 bits as well. This fixes the issue the FreeBSD 6.0 todo list item "Max RAM on sparc64" was refering to and pretty much obsoletes the lack of support for bounce buffers on sparc64. Thanks to Nathan Whitehorn for pointing me at the Tomatillo manual. Approved by: re (kensmith)
2007-08-05 11:56:44 +00:00
if (sc->sc_mode == PSYCHO_MODE_SABRE)
sc->sc_is->is_pmaxaddr =
IOMMU_MAXADDR(SABRE_IOMMU_BITS);
else
sc->sc_is->is_pmaxaddr =
IOMMU_MAXADDR(PSYCHO_IOMMU_BITS);
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = 0;
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
if (OF_getproplen(node, "no-streaming-cache") < 0)
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF;
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
sc->sc_is->is_flags |= (rerun != 1) ? IOMMU_RERUN_DISABLE : 0;
- Add a workaround (change the interrupt map mask to compare the full INO) for incorrect interrupt map entries on E250 machines. These incorrect entries caused the INO of the on-board HME to be also assigned to the second on-board NS16550 and to the on-board printer port controller. Further down the road caused hme(4) to fail to attach to the on-board HME in FreeBSD 5 and 6 as INTR_FAST and non-INTR_FAST handlers can't share the same IRQ there (it's unknown what whould happen in -CURRENT now that INTR_FAST and non-INTR_FAST handlers can share an IRQ but I'd expect funny problems with uart(4)). - Make sure there are exactly 4 PCI ranges instead of just checking that the bridge has a 'ranges' property in the OFW device tree at all. Besides the fact that currently the 64bit memory range isn't used by this driver it we can't really work with less than 4 ranges and don't have memory for more than 4 bus handles for the ranges in the softc. - Remove sc_range and sc_nrange from softc; for the bridges supported by this driver we no longer need to know the ranges besides the bus handles obtained from them once this driver is attached. That way we also can free the memory allocated for sc_range during attach again. - Remove sc_dvmabase from the softc and pass it to psycho_iommu_init() via an additional argument as we no longer need to know the DVMA base in this driver once the IOMMU is initialized. - Remove sc_dmatag from the softc, there isn't much sense in keeping the nexus dma tag around locally. PR: 88279 [1] Info from: OpenSolaris [1] Tested by: kensmith [1] MFC after: 1 month
2005-11-22 22:32:50 +00:00
psycho_iommu_init(sc, 3, dvmabase);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
} else {
- Improve the comment regarding the workaround for the E250 interrupt map bug by explaining what the problem is and how the workaround works. - Fix some cosmetics nits, mainly properly terminate sentences in comments, which I missed when backporting the style changes to psycho(4) in psycho.c rev. 1.54 due to lack of corresponding code. - The "USIIe version of the Sabre bridge" actually is termed "Hummingbird"; name it as such in comments and messages.
2005-12-03 13:08:05 +00:00
/* Just copy IOMMU state, config tag and address. */
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
sc->sc_is = osc->sc_is;
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
if (OF_getproplen(node, "no-streaming-cache") < 0)
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF;
iommu_reset(sc->sc_is);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
}
Remove the psycho and sbus iommu function stubs, and put the pointer to the iommu_state structure directly into dt_cookie. The stubs have not been needed for a long time now.
2003-06-11 20:30:52 +00:00
/* Allocate our tags. */
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
sc->sc_pci_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE);
sc->sc_pci_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE);
sc->sc_pci_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE);
- Divorce the IOTSBs, which so far where handled via a global list instead of per IOMMU, so we no longer need to program all of them identically in systems having multiple IOMMUs. This continues the rototilling of the nexus(4) done about 5 months ago, which amongst others changed nexus(4) and the drivers for host-to-foo bridges to provide bus_get_dma_tag methods, allowing to handle DMA tags in a hierarchical way and to link them with devices. This still doesn't move the silicon bug workarounds for Sabre (and in the uncommitted schizo(4) for Tomatillo) bridges into special bus_dma_tag_create() and bus_dmamap_sync() methods though, as w/o fully newbus'ified bus_dma_tag_create() and bus_dma_tag_destroy() this still requires too much hackery, i.e. per-child parent DMA tags in the parent driver. - Let the host-to-foo drivers supply the maximum physical address of the IOMMU accompanying the bridges. Previously iommu(4) hard- coded an upper limit of 16GB, which actually only applies to the IOMMUs of the Hummingbird and Sabre bridges. The Psycho variants as well as the U2S in fact can can translate to up to 2TB, i.e. translate to 41-bit physical addresses. According to the recently available Tomatillo documentation these bridges even translate to 43-bit physical addresses and hints at the Schizo bridges doing 43 bits as well. This fixes the issue the FreeBSD 6.0 todo list item "Max RAM on sparc64" was refering to and pretty much obsoletes the lack of support for bounce buffers on sparc64. Thanks to Nathan Whitehorn for pointing me at the Tomatillo manual. Approved by: re (kensmith)
2007-08-05 11:56:44 +00:00
if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr,
0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0)
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
panic("%s: bus_dma_tag_create failed", __func__);
Remove the psycho and sbus iommu function stubs, and put the pointer to the iommu_state structure directly into dt_cookie. The stubs have not been needed for a long time now.
2003-06-11 20:30:52 +00:00
/* Customize the tag. */
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
sc->sc_pci_dmat->dt_cookie = sc->sc_is;
sc->sc_pci_dmat->dt_mt = &iommu_dma_methods;
Remove the psycho and sbus iommu function stubs, and put the pointer to the iommu_state structure directly into dt_cookie. The stubs have not been needed for a long time now.
2003-06-11 20:30:52 +00:00
On sparc64 machines with multiple host-PCI-bridges these bridges have separate configuration spaces so by definition they implement different PCI domains. Thus change psycho(4) to use PCI domains instead of reenumerating all PCI busses so they have globally unique bus numbers and drop support for reenumerating busses in the OFW PCI code. According to CVS history reenumeration was also required in order to get some E450 to boot but given that no other open source kernel changes the PCI bus numbers assigned by the firmware I believe the real problem was that the old code used the bus number as the device number for the PCI busses and unlike most of the other machines the firmwares of the problematic ones don't use disjoint PCI bus numbers across the host-PCI-bridges. MFC after: 1 month
2008-04-17 12:38:00 +00:00
n = OF_getprop(node, "bus-range", (void *)prop_array,
sizeof(prop_array));
Add PCI bus enumeration and latency timer setup to the sparc64 MD PCI code. Both tasks are not always performed completely by the firmware. The former is required to get some e450 models to boot; the latter fixes the repeated fifo underruns with hme(4)s and gem(4)s observed on some machines (and probably performance problems with other peripherals as well).
2002-06-12 19:20:57 +00:00
if (n == -1)
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
panic("%s: could not get bus-range", __func__);
On sparc64 machines with multiple host-PCI-bridges these bridges have separate configuration spaces so by definition they implement different PCI domains. Thus change psycho(4) to use PCI domains instead of reenumerating all PCI busses so they have globally unique bus numbers and drop support for reenumerating busses in the OFW PCI code. According to CVS history reenumeration was also required in order to get some E450 to boot but given that no other open source kernel changes the PCI bus numbers assigned by the firmware I believe the real problem was that the old code used the bus number as the device number for the PCI busses and unlike most of the other machines the firmwares of the problematic ones don't use disjoint PCI bus numbers across the host-PCI-bridges. MFC after: 1 month
2008-04-17 12:38:00 +00:00
if (n != sizeof(prop_array))
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
panic("%s: broken bus-range (%d)", __func__, n);
On sparc64 machines with multiple host-PCI-bridges these bridges have separate configuration spaces so by definition they implement different PCI domains. Thus change psycho(4) to use PCI domains instead of reenumerating all PCI busses so they have globally unique bus numbers and drop support for reenumerating busses in the OFW PCI code. According to CVS history reenumeration was also required in order to get some E450 to boot but given that no other open source kernel changes the PCI bus numbers assigned by the firmware I believe the real problem was that the old code used the bus number as the device number for the PCI busses and unlike most of the other machines the firmwares of the problematic ones don't use disjoint PCI bus numbers across the host-PCI-bridges. MFC after: 1 month
2008-04-17 12:38:00 +00:00
if (bootverbose)
device_printf(dev, "bus range %u to %u; PCI bus %d\n",
prop_array[0], prop_array[1], prop_array[0]);
sc->sc_pci_secbus = prop_array[0];
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
Clear any possibly pending PCI error bits left by the firmware. These could trigger an error interrupt that we can't actually to do anything against as soon as enabling the error handlers. While at it don't bother about writing only to the write-one-to-clear bits when clearing error bits.
2008-09-18 19:45:22 +00:00
/* Clear any pending PCI error bits. */
On sparc64 machines with multiple host-PCI-bridges these bridges have separate configuration spaces so by definition they implement different PCI domains. Thus change psycho(4) to use PCI domains instead of reenumerating all PCI busses so they have globally unique bus numbers and drop support for reenumerating busses in the OFW PCI code. According to CVS history reenumeration was also required in order to get some E450 to boot but given that no other open source kernel changes the PCI bus numbers assigned by the firmware I believe the real problem was that the old code used the bus number as the device number for the PCI busses and unlike most of the other machines the firmwares of the problematic ones don't use disjoint PCI bus numbers across the host-PCI-bridges. MFC after: 1 month
2008-04-17 12:38:00 +00:00
PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
Clear any possibly pending PCI error bits left by the firmware. These could trigger an error interrupt that we can't actually to do anything against as soon as enabling the error handlers. While at it don't bother about writing only to the write-one-to-clear bits when clearing error bits.
2008-09-18 19:45:22 +00:00
PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus,
PCS_DEVICE, PCS_FUNC, PCIR_STATUS, 2), 2);
PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS));
PCICTL_WRITE8(sc, PCR_AFS, PCICTL_READ8(sc, PCR_AFS));
if (osc == NULL) {
/*
* Establish handlers for interesting interrupts...
*
* XXX We need to remember these and remove this to support
* hotplug on the UPA/FHC bus.
*
* XXX Not all controllers have these, but installing them
* is better than trying to sort through this mess.
*/
psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL);
psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL);
#ifdef DEBUGGER_ON_POWERFAIL
psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, psycho_powerfail,
NULL);
#else
psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL,
(driver_intr_t *)psycho_powerfail);
#endif
if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
/*
* Hummingbirds/Sabres do not have the following two
* interrupts.
*/
/*
* The spare hardware interrupt is used for the
* over-temperature interrupt.
*/
psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP,
NULL, psycho_overtemp);
#ifdef PSYCHO_MAP_WAKEUP
/*
* psycho_wakeup() doesn't do anything useful right
* now.
*/
psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP,
psycho_wakeup, NULL);
#endif /* PSYCHO_MAP_WAKEUP */
}
}
/*
* Register a PCI bus error interrupt handler according to which
* half this is. Hummingbird/Sabre don't have a PCI bus B error
* interrupt but they are also only used for PCI bus A.
*/
psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP :
PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL);
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
/*
* Set the latency timer register as this isn't always done by the
* firmware.
*/
On sparc64 machines with multiple host-PCI-bridges these bridges have separate configuration spaces so by definition they implement different PCI domains. Thus change psycho(4) to use PCI domains instead of reenumerating all PCI busses so they have globally unique bus numbers and drop support for reenumerating busses in the OFW PCI code. According to CVS history reenumeration was also required in order to get some E450 to boot but given that no other open source kernel changes the PCI bus numbers assigned by the firmware I believe the real problem was that the old code used the bus number as the device number for the PCI busses and unlike most of the other machines the firmwares of the problematic ones don't use disjoint PCI bus numbers across the host-PCI-bridges. MFC after: 1 month
2008-04-17 12:38:00 +00:00
PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
cosmetic changes and style fixes
2008-08-22 20:28:19 +00:00
PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
Add PCI bus enumeration and latency timer setup to the sparc64 MD PCI code. Both tasks are not always performed completely by the firmware. The former is required to get some e450 models to boot; the latter fixes the repeated fifo underruns with hme(4)s and gem(4)s observed on some machines (and probably performance problems with other peripherals as well).
2002-06-12 19:20:57 +00:00
- Add the PCI side of the HOST-PCI bridge itself to the bus. This is required by the X.Org PCI domains code and additionally needs a workaround for Hummingbird and Sabre bridges as these don't allow their config headers to be read at any width, which is an unusual behavior. - In psycho(4) take advantage of DEFINE_CLASS_0 and use more appropriate types for some softc members. MFC after: 3 days
2007-11-30 23:02:42 +00:00
for (n = PCIR_VENDOR; n < PCIR_STATUS; n += sizeof(uint16_t))
le16enc(&sc->sc_pci_hpbcfg[n], bus_space_read_2(
sc->sc_pci_cfgt, sc->sc_pci_bh[OFW_PCI_CS_CONFIG],
PSYCHO_CONF_OFF(sc->sc_pci_secbus, PCS_DEVICE,
PCS_FUNC, n)));
for (n = PCIR_REVID; n <= PCIR_BIST; n += sizeof(uint8_t))
sc->sc_pci_hpbcfg[n] = bus_space_read_1(sc->sc_pci_cfgt,
sc->sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF(
sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, n));
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t));
- Add a workaround (change the interrupt map mask to compare the full INO) for incorrect interrupt map entries on E250 machines. These incorrect entries caused the INO of the on-board HME to be also assigned to the second on-board NS16550 and to the on-board printer port controller. Further down the road caused hme(4) to fail to attach to the on-board HME in FreeBSD 5 and 6 as INTR_FAST and non-INTR_FAST handlers can't share the same IRQ there (it's unknown what whould happen in -CURRENT now that INTR_FAST and non-INTR_FAST handlers can share an IRQ but I'd expect funny problems with uart(4)). - Make sure there are exactly 4 PCI ranges instead of just checking that the bridge has a 'ranges' property in the OFW device tree at all. Besides the fact that currently the 64bit memory range isn't used by this driver it we can't really work with less than 4 ranges and don't have memory for more than 4 bus handles for the ranges in the softc. - Remove sc_range and sc_nrange from softc; for the bridges supported by this driver we no longer need to know the ranges besides the bus handles obtained from them once this driver is attached. That way we also can free the memory allocated for sc_range during attach again. - Remove sc_dvmabase from the softc and pass it to psycho_iommu_init() via an additional argument as we no longer need to know the DVMA base in this driver once the IOMMU is initialized. - Remove sc_dmatag from the softc, there isn't much sense in keeping the nexus dma tag around locally. PR: 88279 [1] Info from: OpenSolaris [1] Tested by: kensmith [1] MFC after: 1 month
2005-11-22 22:32:50 +00:00
/*
- Improve the comment regarding the workaround for the E250 interrupt map bug by explaining what the problem is and how the workaround works. - Fix some cosmetics nits, mainly properly terminate sentences in comments, which I missed when backporting the style changes to psycho(4) in psycho.c rev. 1.54 due to lack of corresponding code. - The "USIIe version of the Sabre bridge" actually is termed "Hummingbird"; name it as such in comments and messages.
2005-12-03 13:08:05 +00:00
* On E250 the interrupt map entry for the EBus bridge is wrong,
* causing incorrect interrupts to be assigned to some devices on
- Use the name returned by device_get_nameunit(9) for the name of the counter-timer timecounter so the associated SYSCTL nodes don't clash on machines having multiple U2P and U2S bridges as well as establishing a clear mapping between these bridges and their timecounter device. - Don't bother setting up a "nice" name for the IOMMU, just use the name returned by device_get_nameunit(9), too. - Fix some minor style(9) bugs. - Use __FBSDID in counter.c MFC after: 1 week
2008-05-07 21:22:15 +00:00
* the EBus. Work around it by changing our copy of the interrupt
* map mask to perform a full comparison of the INO. That way
- Improve the comment regarding the workaround for the E250 interrupt map bug by explaining what the problem is and how the workaround works. - Fix some cosmetics nits, mainly properly terminate sentences in comments, which I missed when backporting the style changes to psycho(4) in psycho.c rev. 1.54 due to lack of corresponding code. - The "USIIe version of the Sabre bridge" actually is termed "Hummingbird"; name it as such in comments and messages.
2005-12-03 13:08:05 +00:00
* the interrupt map entry for the EBus bridge won't match at all
* and the INOs specified in the "interrupts" properties of the
* EBus devices will be used directly instead.
- Add a workaround (change the interrupt map mask to compare the full INO) for incorrect interrupt map entries on E250 machines. These incorrect entries caused the INO of the on-board HME to be also assigned to the second on-board NS16550 and to the on-board printer port controller. Further down the road caused hme(4) to fail to attach to the on-board HME in FreeBSD 5 and 6 as INTR_FAST and non-INTR_FAST handlers can't share the same IRQ there (it's unknown what whould happen in -CURRENT now that INTR_FAST and non-INTR_FAST handlers can share an IRQ but I'd expect funny problems with uart(4)). - Make sure there are exactly 4 PCI ranges instead of just checking that the bridge has a 'ranges' property in the OFW device tree at all. Besides the fact that currently the 64bit memory range isn't used by this driver it we can't really work with less than 4 ranges and don't have memory for more than 4 bus handles for the ranges in the softc. - Remove sc_range and sc_nrange from softc; for the bridges supported by this driver we no longer need to know the ranges besides the bus handles obtained from them once this driver is attached. That way we also can free the memory allocated for sc_range during attach again. - Remove sc_dvmabase from the softc and pass it to psycho_iommu_init() via an additional argument as we no longer need to know the DVMA base in this driver once the IOMMU is initialized. - Remove sc_dmatag from the softc, there isn't much sense in keeping the nexus dma tag around locally. PR: 88279 [1] Info from: OpenSolaris [1] Tested by: kensmith [1] MFC after: 1 month
2005-11-22 22:32:50 +00:00
*/
if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 &&
sc->sc_pci_iinfo.opi_imapmsk != NULL)
*(ofw_pci_intr_t *)(&sc->sc_pci_iinfo.opi_imapmsk[
sc->sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK;
Add a workaround for quirky PCI devices that set the intpin register to 0, but use this mechanism to generate interrupts. Preserve the child device when setting up and tearing down interrupts. Some style nits.
2001-12-21 21:35:47 +00:00
On sparc64 machines with multiple host-PCI-bridges these bridges have separate configuration spaces so by definition they implement different PCI domains. Thus change psycho(4) to use PCI domains instead of reenumerating all PCI busses so they have globally unique bus numbers and drop support for reenumerating busses in the OFW PCI code. According to CVS history reenumeration was also required in order to get some E450 to boot but given that no other open source kernel changes the PCI bus numbers assigned by the firmware I believe the real problem was that the old code used the bus number as the device number for the PCI busses and unlike most of the other machines the firmwares of the problematic ones don't use disjoint PCI bus numbers across the host-PCI-bridges. MFC after: 1 month
2008-04-17 12:38:00 +00:00
device_add_child(dev, "pci", -1);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
return (bus_generic_attach(dev));
}
static void
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
psycho_set_intr(struct psycho_softc *sc, u_int index, bus_addr_t intrmap,
- Use the newly introduced pcib_mtx spin lock to lock psycho_ce(), allowing it to be a filter/"fast" handler. Locking the interrupt handlers with a spin lock is mainly a requirement in schizo(4) but as we ought to register the spin lock anyway it should not hurt to take advantage of it in psycho(4). - Pass both a driver_filter_t and a driver_intr_t argument to psycho_set_intr(), allowing to get rid of the FAST interrupt flag hack. - Don't register the over-temperature interrupt handler as filter/ "fast" handler so shutdown_nice() can acquire the process lock. - Use bus_{read,write}_8() instead of bus_space_{read,write}_8() in order to get rid of sc_bushandle and sc_bustag in the softc. - Correct the debug output for adjusting the subordinate bus number. - Remove the banal and outdated above psycho_filter_stub(). - Fix some white space nits.
2007-06-16 23:46:41 +00:00
driver_filter_t filt, driver_intr_t intr)
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
{
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
u_long vec;
- Use the newly introduced pcib_mtx spin lock to lock psycho_ce(), allowing it to be a filter/"fast" handler. Locking the interrupt handlers with a spin lock is mainly a requirement in schizo(4) but as we ought to register the spin lock anyway it should not hurt to take advantage of it in psycho(4). - Pass both a driver_filter_t and a driver_intr_t argument to psycho_set_intr(), allowing to get rid of the FAST interrupt flag hack. - Don't register the over-temperature interrupt handler as filter/ "fast" handler so shutdown_nice() can acquire the process lock. - Use bus_{read,write}_8() instead of bus_space_{read,write}_8() in order to get rid of sc_bushandle and sc_bustag in the softc. - Correct the debug output for adjusting the subordinate bus number. - Remove the banal and outdated above psycho_filter_stub(). - Fix some white space nits.
2007-06-16 23:46:41 +00:00
int rid;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
- Register the PCI bus error interrupt handler according to which half of the bridge (PCI bus A or B) we are attaching to rather than registering both handlers at once when attaching to the first half we encounter. This is a bit cleaner as it corresponds to which PCI bus error interrupt actually is assigned to the respective half by the OFW and allows to collapse both PCI bus error interrupt handlers into one function easily. - Use the actual RID of the respective interrupt resource as index into sc_irq_res and also use it when allocating the resource. For now this is a bit cleaner and will be mandatory later on. - According to OpenSolaris the spare hardware interrupt is used as the over-temperature interrupt in systems with Psycho bridges. Unlike as with the SBus-based workstations I didn't manage to trigger it when covering the fan outlets of an U60 but better be safe than sorry and register a handler anyway. MFC after: 1 month
2005-12-03 16:36:54 +00:00
rid = index;
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
2007-03-07 21:13:51 +00:00
sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ,
&rid, RF_ACTIVE);
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
if (sc->sc_irq_res[index] == NULL && intrmap >= PSR_POWER_INT_MAP) {
/*
* These interrupts aren't mandatory and not available
* with all controllers (not even Psychos).
*/
return;
}
- Use the newly introduced pcib_mtx spin lock to lock psycho_ce(), allowing it to be a filter/"fast" handler. Locking the interrupt handlers with a spin lock is mainly a requirement in schizo(4) but as we ought to register the spin lock anyway it should not hurt to take advantage of it in psycho(4). - Pass both a driver_filter_t and a driver_intr_t argument to psycho_set_intr(), allowing to get rid of the FAST interrupt flag hack. - Don't register the over-temperature interrupt handler as filter/ "fast" handler so shutdown_nice() can acquire the process lock. - Use bus_{read,write}_8() instead of bus_space_{read,write}_8() in order to get rid of sc_bushandle and sc_bustag in the softc. - Correct the debug output for adjusting the subordinate bus number. - Remove the banal and outdated above psycho_filter_stub(). - Fix some white space nits.
2007-06-16 23:46:41 +00:00
if (sc->sc_irq_res[index] == NULL ||
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) != sc->sc_ign ||
INTVEC(PSYCHO_READ8(sc, intrmap)) != vec ||
intr_vectors[vec].iv_ic != &psycho_ic ||
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index],
INTR_TYPE_MISC | INTR_FAST, filt, intr, sc,
&sc->sc_ihand[index]) != 0)
- Use the newly introduced pcib_mtx spin lock to lock psycho_ce(), allowing it to be a filter/"fast" handler. Locking the interrupt handlers with a spin lock is mainly a requirement in schizo(4) but as we ought to register the spin lock anyway it should not hurt to take advantage of it in psycho(4). - Pass both a driver_filter_t and a driver_intr_t argument to psycho_set_intr(), allowing to get rid of the FAST interrupt flag hack. - Don't register the over-temperature interrupt handler as filter/ "fast" handler so shutdown_nice() can acquire the process lock. - Use bus_{read,write}_8() instead of bus_space_{read,write}_8() in order to get rid of sc_bushandle and sc_bustag in the softc. - Correct the debug output for adjusting the subordinate bus number. - Remove the banal and outdated above psycho_filter_stub(). - Fix some white space nits.
2007-06-16 23:46:41 +00:00
panic("%s: failed to set up interrupt %d", __func__, index);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
}
static int
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
psycho_find_intrmap(struct psycho_softc *sc, u_int ino, bus_addr_t *intrmapptr,
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr)
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
{
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
bus_addr_t intrclr, intrmap;
uint64_t diag;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
int found;
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
/*
* XXX we only compare INOs rather than INRs since the firmware may
* not provide the IGN and the IGN is constant for all devices on
* that PCI controller.
* This could cause problems for the FFB/external interrupt which
* has a full vector that can be set arbitrarily.
*/
if (ino > PSYCHO_MAX_INO) {
device_printf(sc->sc_dev, "out of range INO %d requested\n",
ino);
return (0);
}
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
found = 0;
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
/* Hunt through OBIO first. */
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG);
for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR;
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
intrmap <= PSR_PWRMGT_INT_MAP; intrmap += 8, intrclr += 8,
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
2007-03-07 21:13:51 +00:00
diag >>= 2) {
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
if (sc->sc_mode == PSYCHO_MODE_SABRE &&
(intrmap == PSR_TIMER0_INT_MAP ||
intrmap == PSR_TIMER1_INT_MAP ||
intrmap == PSR_PCIBERR_INT_MAP ||
intrmap == PSR_PWRMGT_INT_MAP))
continue;
if (INTINO(PSYCHO_READ8(sc, intrmap)) == ino) {
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
diag &= 2;
found = 1;
break;
}
}
if (!found) {
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG);
- Improve the comment regarding the workaround for the E250 interrupt map bug by explaining what the problem is and how the workaround works. - Fix some cosmetics nits, mainly properly terminate sentences in comments, which I missed when backporting the style changes to psycho(4) in psycho.c rev. 1.54 due to lack of corresponding code. - The "USIIe version of the Sabre bridge" actually is termed "Hummingbird"; name it as such in comments and messages.
2005-12-03 13:08:05 +00:00
/* Now do PCI interrupts. */
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR;
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
2007-03-07 21:13:51 +00:00
intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32,
diag >>= 8) {
1.) Do not look for PCI INOs in the FFB interrupt mapping registers; they are nevers used for PCI interrupts, but can cause false matches since they are fully programmable. 2.) Skip the mapping registers for slot a2 and a3 on "psycho" bridges, since they are not present there. Again, this could cause false matches, which would result in the interrupt being delivered at most once. Submitted by: jake (2) Approved by: re
2002-12-01 23:21:15 +00:00
if (sc->sc_mode == PSYCHO_MODE_PSYCHO &&
(intrmap == PSR_PCIA2_INT_MAP ||
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
intrmap == PSR_PCIA3_INT_MAP))
1.) Do not look for PCI INOs in the FFB interrupt mapping registers; they are nevers used for PCI interrupts, but can cause false matches since they are fully programmable. 2.) Skip the mapping registers for slot a2 and a3 on "psycho" bridges, since they are not present there. Again, this could cause false matches, which would result in the interrupt being delivered at most once. Submitted by: jake (2) Approved by: re
2002-12-01 23:21:15 +00:00
continue;
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
if (((PSYCHO_READ8(sc, intrmap) ^ ino) & 0x3c) == 0) {
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
intrclr += 8 * (ino & 3);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
diag = (diag >> ((ino & 3) * 2)) & 2;
found = 1;
break;
}
}
}
if (intrmapptr != NULL)
*intrmapptr = intrmap;
if (intrclrptr != NULL)
*intrclrptr = intrclr;
if (intrdiagptr != NULL)
*intrdiagptr = diag;
return (found);
}
/*
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
* Interrupt handlers
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
*/
o break newbus api: add a new argument of type driver_filter_t to bus_setup_intr() o add an int return code to all fast handlers o retire INTR_FAST/IH_FAST For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current Reviewed by: many Approved by: re@
2007-02-23 12:19:07 +00:00
static int
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
psycho_ue(void *arg)
{
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
struct psycho_softc *sc = arg;
uint64_t afar, afsr;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
afar = PSYCHO_READ8(sc, PSR_UE_AFA);
afsr = PSYCHO_READ8(sc, PSR_UE_AFS);
Add code to print the fault virtual address for uncorrectable DMA errors caused by IOMMU misses to aid debugging. This will only work on UltraSPARC-IIi and IIe.
2002-03-23 20:42:23 +00:00
/*
* On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause
* the AFAR to be set to the physical address of the TTE entry that
- Use the name returned by device_get_nameunit(9) for the name of the counter-timer timecounter so the associated SYSCTL nodes don't clash on machines having multiple U2P and U2S bridges as well as establishing a clear mapping between these bridges and their timecounter device. - Don't bother setting up a "nice" name for the IOMMU, just use the name returned by device_get_nameunit(9), too. - Fix some minor style(9) bugs. - Use __FBSDID in counter.c MFC after: 1 week
2008-05-07 21:22:15 +00:00
* was invalid/write protected. Call into the IOMMU code to have
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
* them decoded to virtual I/O addresses.
Add code to print the fault virtual address for uncorrectable DMA errors caused by IOMMU misses to aid debugging. This will only work on UltraSPARC-IIi and IIe.
2002-03-23 20:42:23 +00:00
*/
if ((afsr & UEAFSR_P_DTE) != 0)
iommu_decode_fault(sc->sc_is, afar);
- remove some outdated comments - tweak the announce message a bit - remove '\n's from a few panic() calls - don't use the DVMA base adress the firmware reports; instead, figure it out from the appropriate register on Sabres and let the IOMMU code choose it on Psychos. This also makes the IOMMU TSB size freely selectable.
2003-01-06 16:51:06 +00:00
panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx",
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr);
o break newbus api: add a new argument of type driver_filter_t to bus_setup_intr() o add an int return code to all fast handlers o retire INTR_FAST/IH_FAST For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current Reviewed by: many Approved by: re@
2007-02-23 12:19:07 +00:00
return (FILTER_HANDLED);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
}
o break newbus api: add a new argument of type driver_filter_t to bus_setup_intr() o add an int return code to all fast handlers o retire INTR_FAST/IH_FAST For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current Reviewed by: many Approved by: re@
2007-02-23 12:19:07 +00:00
static int
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
psycho_ce(void *arg)
{
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
struct psycho_softc *sc = arg;
uint64_t afar, afsr;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
- Use the newly introduced pcib_mtx spin lock to lock psycho_ce(), allowing it to be a filter/"fast" handler. Locking the interrupt handlers with a spin lock is mainly a requirement in schizo(4) but as we ought to register the spin lock anyway it should not hurt to take advantage of it in psycho(4). - Pass both a driver_filter_t and a driver_intr_t argument to psycho_set_intr(), allowing to get rid of the FAST interrupt flag hack. - Don't register the over-temperature interrupt handler as filter/ "fast" handler so shutdown_nice() can acquire the process lock. - Use bus_{read,write}_8() instead of bus_space_{read,write}_8() in order to get rid of sc_bushandle and sc_bustag in the softc. - Correct the debug output for adjusting the subordinate bus number. - Remove the banal and outdated above psycho_filter_stub(). - Fix some white space nits.
2007-06-16 23:46:41 +00:00
mtx_lock_spin(sc->sc_mtx);
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
afar = PSYCHO_READ8(sc, PSR_CE_AFA);
afsr = PSYCHO_READ8(sc, PSR_CE_AFS);
Add the new sparc64 OFW PCI framework, conditional on options OFW_NEWPCI for now. It introduces a OFW PCI bus driver and a generic OFW PCI-PCI bridge driver. By utilizing these, the PCI handling is much more elegant now. The advantages of the new approach are: - Device enumeration should hopefully be more like on Solaris now, so unit numbers should match what's printed on the box more closely. - Real interrupt routing is implemented now, so cardbus bridges etc. have at least a chance to work. - The quirk tables are gone and have been replaced by (hopefully sufficient) heuristics. - Much cleaner code. There was also a report that previously bogus interrupt assignments are fixed now, which can be attributed to the new heuristics. A pitfall, and the reason why this is not the default yet, is that it changes device enumeration, as mentioned above, which can make it necessary to change the system configuration if more than one unit of a device type is present (on a system with two hme cars, for example, it is possible that hme0 becomes hme1 and vice versa after enabling the option). Systems with multiple disk controllers may need to be booted into single user (and require manual specification of the root file system on boot) to adjust the fstab. Nevertheless, I would like to encourage users to use this option, so that it can be made the default soon. In detail, the changes are: - Introduce an OFW PCI bus driver; it inherits most methods from the generic PCI bus driver, but uses the firmware for enumeration, performs additional initialization for devices and firmware-specific interrupt routing. It also implements an OFW-specific method to allow child devices to get their firmware nodes. - Introduce an OFW PCI-PCI bridge driver; again, it inherits most of the generic PCI-PCI bridge driver; it has it's own method for interrupt routing, as well as some sparc64-specific methods (one to get the node again, and one to adjust the bridge bus range, since we need to reenumerate all PCI buses). - Convert the apb driver to the new way of handling things. - Provide a common framework for OFW bridge drivers, used be the two drivers above. - Provide a small common framework for interrupt routing (for all bridge types). - Convert the psycho driver to the new framework; this gets rid of a bunch of old kludges in pci_read_config(), and the whole preinitialization (ofw_pci_init()). - Convert the ISA MD part and the EBus driver to the new way interrupts and nodes are handled. - Introduce types for firmware interrupt properties. - Rename the old sparcbus_if to ofw_pci_if by repo copy (it is only required for PCI), and move it to a more correct location (new support methodsx were also added, and an old one was deprecated). - Fix a bunch of minor bugs, perform some cleanups. In some cases, I introduced some minor code duplication to keep the new code clean, in hopes that the old code will be unifdef'ed soon. Reviewed in part by: imp Tested by: jake, Marius Strobl <marius@alchemy.franken.de>, Sergey Mokryshev <mokr@mokr.net>, Chris Jackman <cjackNOSPAM@klatsch.org> Info on u30 firmware provided by: kris
2003-07-01 14:52:47 +00:00
device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx "
"AFSR %#lx\n", (u_long)afar, (u_long)afsr);
- Clear the CE AFSR bits which indicate the error condition when handling a correctable DMA error. Failing to do so can cause the error interrupt to be triggered over and over again. - Clean up the comments for UEAFSR_* constants, fix a typo (UEAFSR_BLK is (1 << 23), not (1 << 22)), and add two more. Also, add similar constants for the CE AFSR bits.
2003-09-04 15:25:10 +00:00
/* Clear the error bits that we caught. */
Clear any possibly pending PCI error bits left by the firmware. These could trigger an error interrupt that we can't actually to do anything against as soon as enabling the error handlers. While at it don't bother about writing only to the write-one-to-clear bits when clearing error bits.
2008-09-18 19:45:22 +00:00
PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr);
- Use the newly introduced pcib_mtx spin lock to lock psycho_ce(), allowing it to be a filter/"fast" handler. Locking the interrupt handlers with a spin lock is mainly a requirement in schizo(4) but as we ought to register the spin lock anyway it should not hurt to take advantage of it in psycho(4). - Pass both a driver_filter_t and a driver_intr_t argument to psycho_set_intr(), allowing to get rid of the FAST interrupt flag hack. - Don't register the over-temperature interrupt handler as filter/ "fast" handler so shutdown_nice() can acquire the process lock. - Use bus_{read,write}_8() instead of bus_space_{read,write}_8() in order to get rid of sc_bushandle and sc_bustag in the softc. - Correct the debug output for adjusting the subordinate bus number. - Remove the banal and outdated above psycho_filter_stub(). - Fix some white space nits.
2007-06-16 23:46:41 +00:00
mtx_unlock_spin(sc->sc_mtx);
o break newbus api: add a new argument of type driver_filter_t to bus_setup_intr() o add an int return code to all fast handlers o retire INTR_FAST/IH_FAST For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current Reviewed by: many Approved by: re@
2007-02-23 12:19:07 +00:00
return (FILTER_HANDLED);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
}
o break newbus api: add a new argument of type driver_filter_t to bus_setup_intr() o add an int return code to all fast handlers o retire INTR_FAST/IH_FAST For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current Reviewed by: many Approved by: re@
2007-02-23 12:19:07 +00:00
static int
- Register the PCI bus error interrupt handler according to which half of the bridge (PCI bus A or B) we are attaching to rather than registering both handlers at once when attaching to the first half we encounter. This is a bit cleaner as it corresponds to which PCI bus error interrupt actually is assigned to the respective half by the OFW and allows to collapse both PCI bus error interrupt handlers into one function easily. - Use the actual RID of the respective interrupt resource as index into sc_irq_res and also use it when allocating the resource. For now this is a bit cleaner and will be mandatory later on. - According to OpenSolaris the spare hardware interrupt is used as the over-temperature interrupt in systems with Psycho bridges. Unlike as with the SBus-based workstations I didn't manage to trigger it when covering the fan outlets of an U60 but better be safe than sorry and register a handler anyway. MFC after: 1 month
2005-12-03 16:36:54 +00:00
psycho_pci_bus(void *arg)
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
{
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
struct psycho_softc *sc = arg;
uint64_t afar, afsr;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
- Register the PCI bus error interrupt handler according to which half of the bridge (PCI bus A or B) we are attaching to rather than registering both handlers at once when attaching to the first half we encounter. This is a bit cleaner as it corresponds to which PCI bus error interrupt actually is assigned to the respective half by the OFW and allows to collapse both PCI bus error interrupt handlers into one function easily. - Use the actual RID of the respective interrupt resource as index into sc_irq_res and also use it when allocating the resource. For now this is a bit cleaner and will be mandatory later on. - According to OpenSolaris the spare hardware interrupt is used as the over-temperature interrupt in systems with Psycho bridges. Unlike as with the SBus-based workstations I didn't manage to trigger it when covering the fan outlets of an U60 but better be safe than sorry and register a handler anyway. MFC after: 1 month
2005-12-03 16:36:54 +00:00
afar = PCICTL_READ8(sc, PCR_AFA);
afsr = PCICTL_READ8(sc, PCR_AFS);
panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx",
device_get_name(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar,
(u_long)afsr);
o break newbus api: add a new argument of type driver_filter_t to bus_setup_intr() o add an int return code to all fast handlers o retire INTR_FAST/IH_FAST For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current Reviewed by: many Approved by: re@
2007-02-23 12:19:07 +00:00
return (FILTER_HANDLED);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
}
o break newbus api: add a new argument of type driver_filter_t to bus_setup_intr() o add an int return code to all fast handlers o retire INTR_FAST/IH_FAST For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current Reviewed by: many Approved by: re@
2007-02-23 12:19:07 +00:00
static int
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
psycho_powerfail(void *arg)
{
Add a DEBUGGER_ON_POWERFAIL option. This makes the power button on ultra 10s work like an NMI button.
2002-03-13 05:58:45 +00:00
#ifdef DEBUGGER_ON_POWERFAIL
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
struct psycho_softc *sc = arg;
Add a DEBUGGER_ON_POWERFAIL option. This makes the power button on ultra 10s work like an NMI button.
2002-03-13 05:58:45 +00:00
Add a new 'why' argument to kdb_enter(), and a set of constants to use for that argument. This will allow DDB to detect the broad category of reason why the debugger has been entered, which it can use for the purposes of deciding which DDB script to run. Assign approximate why values to all current consumers of the kdb_enter() interface.
2007-12-25 17:52:02 +00:00
kdb_enter(KDB_WHY_POWERFAIL, "powerfail");
Add a DEBUGGER_ON_POWERFAIL option. This makes the power button on ultra 10s work like an NMI button.
2002-03-13 05:58:45 +00:00
#else
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
static int shutdown;
/* As the interrupt is cleared we may be called multiple times. */
if (shutdown != 0)
return (FILTER_HANDLED);
shutdown++;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
printf("Power Failure Detected: Shutting down NOW.\n");
shutdown_nice(0);
Add a DEBUGGER_ON_POWERFAIL option. This makes the power button on ultra 10s work like an NMI button.
2002-03-13 05:58:45 +00:00
#endif
o break newbus api: add a new argument of type driver_filter_t to bus_setup_intr() o add an int return code to all fast handlers o retire INTR_FAST/IH_FAST For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current Reviewed by: many Approved by: re@
2007-02-23 12:19:07 +00:00
return (FILTER_HANDLED);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
}
- Use the newly introduced pcib_mtx spin lock to lock psycho_ce(), allowing it to be a filter/"fast" handler. Locking the interrupt handlers with a spin lock is mainly a requirement in schizo(4) but as we ought to register the spin lock anyway it should not hurt to take advantage of it in psycho(4). - Pass both a driver_filter_t and a driver_intr_t argument to psycho_set_intr(), allowing to get rid of the FAST interrupt flag hack. - Don't register the over-temperature interrupt handler as filter/ "fast" handler so shutdown_nice() can acquire the process lock. - Use bus_{read,write}_8() instead of bus_space_{read,write}_8() in order to get rid of sc_bushandle and sc_bustag in the softc. - Correct the debug output for adjusting the subordinate bus number. - Remove the banal and outdated above psycho_filter_stub(). - Fix some white space nits.
2007-06-16 23:46:41 +00:00
static void
- Register the PCI bus error interrupt handler according to which half of the bridge (PCI bus A or B) we are attaching to rather than registering both handlers at once when attaching to the first half we encounter. This is a bit cleaner as it corresponds to which PCI bus error interrupt actually is assigned to the respective half by the OFW and allows to collapse both PCI bus error interrupt handlers into one function easily. - Use the actual RID of the respective interrupt resource as index into sc_irq_res and also use it when allocating the resource. For now this is a bit cleaner and will be mandatory later on. - According to OpenSolaris the spare hardware interrupt is used as the over-temperature interrupt in systems with Psycho bridges. Unlike as with the SBus-based workstations I didn't manage to trigger it when covering the fan outlets of an U60 but better be safe than sorry and register a handler anyway. MFC after: 1 month
2005-12-03 16:36:54 +00:00
psycho_overtemp(void *arg)
{
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
static int shutdown;
- Register the PCI bus error interrupt handler according to which half of the bridge (PCI bus A or B) we are attaching to rather than registering both handlers at once when attaching to the first half we encounter. This is a bit cleaner as it corresponds to which PCI bus error interrupt actually is assigned to the respective half by the OFW and allows to collapse both PCI bus error interrupt handlers into one function easily. - Use the actual RID of the respective interrupt resource as index into sc_irq_res and also use it when allocating the resource. For now this is a bit cleaner and will be mandatory later on. - According to OpenSolaris the spare hardware interrupt is used as the over-temperature interrupt in systems with Psycho bridges. Unlike as with the SBus-based workstations I didn't manage to trigger it when covering the fan outlets of an U60 but better be safe than sorry and register a handler anyway. MFC after: 1 month
2005-12-03 16:36:54 +00:00
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
/* As the interrupt is cleared we may be called multiple times. */
if (shutdown != 0)
return;
shutdown++;
- Register the PCI bus error interrupt handler according to which half of the bridge (PCI bus A or B) we are attaching to rather than registering both handlers at once when attaching to the first half we encounter. This is a bit cleaner as it corresponds to which PCI bus error interrupt actually is assigned to the respective half by the OFW and allows to collapse both PCI bus error interrupt handlers into one function easily. - Use the actual RID of the respective interrupt resource as index into sc_irq_res and also use it when allocating the resource. For now this is a bit cleaner and will be mandatory later on. - According to OpenSolaris the spare hardware interrupt is used as the over-temperature interrupt in systems with Psycho bridges. Unlike as with the SBus-based workstations I didn't manage to trigger it when covering the fan outlets of an U60 but better be safe than sorry and register a handler anyway. MFC after: 1 month
2005-12-03 16:36:54 +00:00
printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n");
shutdown_nice(RB_POWEROFF);
}
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
#ifdef PSYCHO_MAP_WAKEUP
o break newbus api: add a new argument of type driver_filter_t to bus_setup_intr() o add an int return code to all fast handlers o retire INTR_FAST/IH_FAST For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current Reviewed by: many Approved by: re@
2007-02-23 12:19:07 +00:00
static int
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
psycho_wakeup(void *arg)
{
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
struct psycho_softc *sc = arg;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
/* Gee, we don't really have a framework to deal with this properly. */
Add the new sparc64 OFW PCI framework, conditional on options OFW_NEWPCI for now. It introduces a OFW PCI bus driver and a generic OFW PCI-PCI bridge driver. By utilizing these, the PCI handling is much more elegant now. The advantages of the new approach are: - Device enumeration should hopefully be more like on Solaris now, so unit numbers should match what's printed on the box more closely. - Real interrupt routing is implemented now, so cardbus bridges etc. have at least a chance to work. - The quirk tables are gone and have been replaced by (hopefully sufficient) heuristics. - Much cleaner code. There was also a report that previously bogus interrupt assignments are fixed now, which can be attributed to the new heuristics. A pitfall, and the reason why this is not the default yet, is that it changes device enumeration, as mentioned above, which can make it necessary to change the system configuration if more than one unit of a device type is present (on a system with two hme cars, for example, it is possible that hme0 becomes hme1 and vice versa after enabling the option). Systems with multiple disk controllers may need to be booted into single user (and require manual specification of the root file system on boot) to adjust the fstab. Nevertheless, I would like to encourage users to use this option, so that it can be made the default soon. In detail, the changes are: - Introduce an OFW PCI bus driver; it inherits most methods from the generic PCI bus driver, but uses the firmware for enumeration, performs additional initialization for devices and firmware-specific interrupt routing. It also implements an OFW-specific method to allow child devices to get their firmware nodes. - Introduce an OFW PCI-PCI bridge driver; again, it inherits most of the generic PCI-PCI bridge driver; it has it's own method for interrupt routing, as well as some sparc64-specific methods (one to get the node again, and one to adjust the bridge bus range, since we need to reenumerate all PCI buses). - Convert the apb driver to the new way of handling things. - Provide a common framework for OFW bridge drivers, used be the two drivers above. - Provide a small common framework for interrupt routing (for all bridge types). - Convert the psycho driver to the new framework; this gets rid of a bunch of old kludges in pci_read_config(), and the whole preinitialization (ofw_pci_init()). - Convert the ISA MD part and the EBus driver to the new way interrupts and nodes are handled. - Introduce types for firmware interrupt properties. - Rename the old sparcbus_if to ofw_pci_if by repo copy (it is only required for PCI), and move it to a more correct location (new support methodsx were also added, and an old one was deprecated). - Fix a bunch of minor bugs, perform some cleanups. In some cases, I introduced some minor code duplication to keep the new code clean, in hopes that the old code will be unifdef'ed soon. Reviewed in part by: imp Tested by: jake, Marius Strobl <marius@alchemy.franken.de>, Sergey Mokryshev <mokr@mokr.net>, Chris Jackman <cjackNOSPAM@klatsch.org> Info on u30 firmware provided by: kris
2003-07-01 14:52:47 +00:00
device_printf(sc->sc_dev, "power management wakeup\n");
o break newbus api: add a new argument of type driver_filter_t to bus_setup_intr() o add an int return code to all fast handlers o retire INTR_FAST/IH_FAST For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current Reviewed by: many Approved by: re@
2007-02-23 12:19:07 +00:00
return (FILTER_HANDLED);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
}
#endif /* PSYCHO_MAP_WAKEUP */
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
static void
- Add a workaround (change the interrupt map mask to compare the full INO) for incorrect interrupt map entries on E250 machines. These incorrect entries caused the INO of the on-board HME to be also assigned to the second on-board NS16550 and to the on-board printer port controller. Further down the road caused hme(4) to fail to attach to the on-board HME in FreeBSD 5 and 6 as INTR_FAST and non-INTR_FAST handlers can't share the same IRQ there (it's unknown what whould happen in -CURRENT now that INTR_FAST and non-INTR_FAST handlers can share an IRQ but I'd expect funny problems with uart(4)). - Make sure there are exactly 4 PCI ranges instead of just checking that the bridge has a 'ranges' property in the OFW device tree at all. Besides the fact that currently the 64bit memory range isn't used by this driver it we can't really work with less than 4 ranges and don't have memory for more than 4 bus handles for the ranges in the softc. - Remove sc_range and sc_nrange from softc; for the bridges supported by this driver we no longer need to know the ranges besides the bus handles obtained from them once this driver is attached. That way we also can free the memory allocated for sc_range during attach again. - Remove sc_dvmabase from the softc and pass it to psycho_iommu_init() via an additional argument as we no longer need to know the DVMA base in this driver once the IOMMU is initialized. - Remove sc_dmatag from the softc, there isn't much sense in keeping the nexus dma tag around locally. PR: 88279 [1] Info from: OpenSolaris [1] Tested by: kensmith [1] MFC after: 1 month
2005-11-22 22:32:50 +00:00
psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase)
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
{
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
struct iommu_state *is = sc->sc_is;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
/* Punch in our copies. */
- Use the newly introduced pcib_mtx spin lock to lock psycho_ce(), allowing it to be a filter/"fast" handler. Locking the interrupt handlers with a spin lock is mainly a requirement in schizo(4) but as we ought to register the spin lock anyway it should not hurt to take advantage of it in psycho(4). - Pass both a driver_filter_t and a driver_intr_t argument to psycho_set_intr(), allowing to get rid of the FAST interrupt flag hack. - Don't register the over-temperature interrupt handler as filter/ "fast" handler so shutdown_nice() can acquire the process lock. - Use bus_{read,write}_8() instead of bus_space_{read,write}_8() in order to get rid of sc_bushandle and sc_bustag in the softc. - Correct the debug output for adjusting the subordinate bus number. - Remove the banal and outdated above psycho_filter_stub(). - Fix some white space nits.
2007-06-16 23:46:41 +00:00
is->is_bustag = rman_get_bustag(sc->sc_mem_res);
is->is_bushandle = rman_get_bushandle(sc->sc_mem_res);
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
is->is_iommu = PSR_IOMMU;
is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG;
is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG;
is->is_dqueue = PSR_IOMMU_QUEUE_DIAG;
is->is_dva = PSR_IOMMU_SVADIAG;
is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
- Use the name returned by device_get_nameunit(9) for the name of the counter-timer timecounter so the associated SYSCTL nodes don't clash on machines having multiple U2P and U2S bridges as well as establishing a clear mapping between these bridges and their timecounter device. - Don't bother setting up a "nice" name for the IOMMU, just use the name returned by device_get_nameunit(9), too. - Fix some minor style(9) bugs. - Use __FBSDID in counter.c MFC after: 1 week
2008-05-07 21:22:15 +00:00
iommu_init(device_get_nameunit(sc->sc_dev), is, tsbsize, dvmabase, 0);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
}
static int
psycho_maxslots(device_t dev)
{
Add the new sparc64 OFW PCI framework, conditional on options OFW_NEWPCI for now. It introduces a OFW PCI bus driver and a generic OFW PCI-PCI bridge driver. By utilizing these, the PCI handling is much more elegant now. The advantages of the new approach are: - Device enumeration should hopefully be more like on Solaris now, so unit numbers should match what's printed on the box more closely. - Real interrupt routing is implemented now, so cardbus bridges etc. have at least a chance to work. - The quirk tables are gone and have been replaced by (hopefully sufficient) heuristics. - Much cleaner code. There was also a report that previously bogus interrupt assignments are fixed now, which can be attributed to the new heuristics. A pitfall, and the reason why this is not the default yet, is that it changes device enumeration, as mentioned above, which can make it necessary to change the system configuration if more than one unit of a device type is present (on a system with two hme cars, for example, it is possible that hme0 becomes hme1 and vice versa after enabling the option). Systems with multiple disk controllers may need to be booted into single user (and require manual specification of the root file system on boot) to adjust the fstab. Nevertheless, I would like to encourage users to use this option, so that it can be made the default soon. In detail, the changes are: - Introduce an OFW PCI bus driver; it inherits most methods from the generic PCI bus driver, but uses the firmware for enumeration, performs additional initialization for devices and firmware-specific interrupt routing. It also implements an OFW-specific method to allow child devices to get their firmware nodes. - Introduce an OFW PCI-PCI bridge driver; again, it inherits most of the generic PCI-PCI bridge driver; it has it's own method for interrupt routing, as well as some sparc64-specific methods (one to get the node again, and one to adjust the bridge bus range, since we need to reenumerate all PCI buses). - Convert the apb driver to the new way of handling things. - Provide a common framework for OFW bridge drivers, used be the two drivers above. - Provide a small common framework for interrupt routing (for all bridge types). - Convert the psycho driver to the new framework; this gets rid of a bunch of old kludges in pci_read_config(), and the whole preinitialization (ofw_pci_init()). - Convert the ISA MD part and the EBus driver to the new way interrupts and nodes are handled. - Introduce types for firmware interrupt properties. - Rename the old sparcbus_if to ofw_pci_if by repo copy (it is only required for PCI), and move it to a more correct location (new support methodsx were also added, and an old one was deprecated). - Fix a bunch of minor bugs, perform some cleanups. In some cases, I introduced some minor code duplication to keep the new code clean, in hopes that the old code will be unifdef'ed soon. Reviewed in part by: imp Tested by: jake, Marius Strobl <marius@alchemy.franken.de>, Sergey Mokryshev <mokr@mokr.net>, Chris Jackman <cjackNOSPAM@klatsch.org> Info on u30 firmware provided by: kris
2003-07-01 14:52:47 +00:00
/* XXX: is this correct? */
return (PCI_SLOTMAX);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
}
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
static uint32_t
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
int width)
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
{
struct psycho_softc *sc;
bus_space_handle_t bh;
u_long offset = 0;
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
uint8_t byte;
uint16_t shrt;
- Add the PCI side of the HOST-PCI bridge itself to the bus. This is required by the X.Org PCI domains code and additionally needs a workaround for Hummingbird and Sabre bridges as these don't allow their config headers to be read at any width, which is an unusual behavior. - In psycho(4) take advantage of DEFINE_CLASS_0 and use more appropriate types for some softc members. MFC after: 3 days
2007-11-30 23:02:42 +00:00
uint32_t r, wrd;
Add a workaround for quirky PCI devices that set the intpin register to 0, but use this mechanism to generate interrupts. Preserve the child device when setting up and tearing down interrupts. Some style nits.
2001-12-21 21:35:47 +00:00
int i;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
sc = device_get_softc(dev);
- Move the declaration of struct upa_ranges and the UPA_RANGE_* macros from sys/sparc64/include/ofw_upa.h to sys/sparc64/pci/ofw_pci.h and rename them to struct ofw_pci_ranges and OFW_PCI_RANGE_* respectively. This ranges struct only applies to host-PCI bridges but no to other bridges found on UPA. At the same time it applies to all host-PCI bridges regardless of whether the interconnection bus is Fireplane/ Safari, JBus or UPA. - While here rename the PCI_CS_* macros in sys/sparc64/pci/ofw_pci.h to OFW_PCI_CS_* in order to be consistent and change this header to use uintXX_t instead of u_intXX_t.
2005-12-03 19:52:20 +00:00
bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
- Add the PCI side of the HOST-PCI bridge itself to the bus. This is required by the X.Org PCI domains code and additionally needs a workaround for Hummingbird and Sabre bridges as these don't allow their config headers to be read at any width, which is an unusual behavior. - In psycho(4) take advantage of DEFINE_CLASS_0 and use more appropriate types for some softc members. MFC after: 3 days
2007-11-30 23:02:42 +00:00
/*
* The Hummingbird and Sabre bridges are picky in that they
* only allow their config space to be accessed using the
* "native" width of the respective register being accessed
* and return semi-random other content of their config space
- Use the name returned by device_get_nameunit(9) for the name of the counter-timer timecounter so the associated SYSCTL nodes don't clash on machines having multiple U2P and U2S bridges as well as establishing a clear mapping between these bridges and their timecounter device. - Don't bother setting up a "nice" name for the IOMMU, just use the name returned by device_get_nameunit(9), too. - Fix some minor style(9) bugs. - Use __FBSDID in counter.c MFC after: 1 week
2008-05-07 21:22:15 +00:00
* otherwise. Given that the PCI specs don't say anything
- Add the PCI side of the HOST-PCI bridge itself to the bus. This is required by the X.Org PCI domains code and additionally needs a workaround for Hummingbird and Sabre bridges as these don't allow their config headers to be read at any width, which is an unusual behavior. - In psycho(4) take advantage of DEFINE_CLASS_0 and use more appropriate types for some softc members. MFC after: 3 days
2007-11-30 23:02:42 +00:00
* about such a (unusual) limitation and lots of stuff expects
* to be able to access the contents of the config space at
- Use the name returned by device_get_nameunit(9) for the name of the counter-timer timecounter so the associated SYSCTL nodes don't clash on machines having multiple U2P and U2S bridges as well as establishing a clear mapping between these bridges and their timecounter device. - Don't bother setting up a "nice" name for the IOMMU, just use the name returned by device_get_nameunit(9), too. - Fix some minor style(9) bugs. - Use __FBSDID in counter.c MFC after: 1 week
2008-05-07 21:22:15 +00:00
* any width we allow just that. We do this by using a copy
- Add the PCI side of the HOST-PCI bridge itself to the bus. This is required by the X.Org PCI domains code and additionally needs a workaround for Hummingbird and Sabre bridges as these don't allow their config headers to be read at any width, which is an unusual behavior. - In psycho(4) take advantage of DEFINE_CLASS_0 and use more appropriate types for some softc members. MFC after: 3 days
2007-11-30 23:02:42 +00:00
* of the header of the bridge (the rest is all zero anyway)
* read during attach (expect for PCIR_STATUS) in order to
* simplify things.
* The Psycho bridges contain a dupe of their header at 0x80
* which we nullify that way also.
*/
if (bus == sc->sc_pci_secbus && slot == PCS_DEVICE &&
func == PCS_FUNC) {
if (offset % width != 0)
return (-1);
Fix a non-fatal off-by-one error in the previous revision.
2007-12-01 19:42:33 +00:00
if (reg >= sizeof(sc->sc_pci_hpbcfg))
- Add the PCI side of the HOST-PCI bridge itself to the bus. This is required by the X.Org PCI domains code and additionally needs a workaround for Hummingbird and Sabre bridges as these don't allow their config headers to be read at any width, which is an unusual behavior. - In psycho(4) take advantage of DEFINE_CLASS_0 and use more appropriate types for some softc members. MFC after: 3 days
2007-11-30 23:02:42 +00:00
return (0);
if ((reg < PCIR_STATUS && reg + width > PCIR_STATUS) ||
reg == PCIR_STATUS || reg == PCIR_STATUS + 1)
le16enc(&sc->sc_pci_hpbcfg[PCIR_STATUS],
bus_space_read_2(sc->sc_pci_cfgt, bh,
PSYCHO_CONF_OFF(sc->sc_pci_secbus,
PCS_DEVICE, PCS_FUNC, PCIR_STATUS)));
switch (width) {
case 1:
return (sc->sc_pci_hpbcfg[reg]);
case 2:
return (le16dec(&sc->sc_pci_hpbcfg[reg]));
case 4:
return (le32dec(&sc->sc_pci_hpbcfg[reg]));
}
}
offset = PSYCHO_CONF_OFF(bus, slot, func, reg);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
switch (width) {
case 1:
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte);
add support for peeking at pci busses on UltraSparc systems. This prevents data access errors when trying to read/write to non-existant PCI devices. fix the psycho bridge to use peek for probing devices. This no longer fakes it if the OFW node doesn't exist (and the reg == 0). Reviewed by: jake, tmm
2003-06-22 01:26:08 +00:00
r = byte;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
break;
case 2:
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt);
add support for peeking at pci busses on UltraSparc systems. This prevents data access errors when trying to read/write to non-existant PCI devices. fix the psycho bridge to use peek for probing devices. This no longer fakes it if the OFW node doesn't exist (and the reg == 0). Reviewed by: jake, tmm
2003-06-22 01:26:08 +00:00
r = shrt;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
break;
case 4:
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd);
add support for peeking at pci busses on UltraSparc systems. This prevents data access errors when trying to read/write to non-existant PCI devices. fix the psycho bridge to use peek for probing devices. This no longer fakes it if the OFW node doesn't exist (and the reg == 0). Reviewed by: jake, tmm
2003-06-22 01:26:08 +00:00
r = wrd;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
break;
default:
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
panic("%s: bad width", __func__);
cosmetic changes and style fixes
2008-08-22 20:28:19 +00:00
/* NOTREACHED */
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
}
add support for peeking at pci busses on UltraSparc systems. This prevents data access errors when trying to read/write to non-existant PCI devices. fix the psycho bridge to use peek for probing devices. This no longer fakes it if the OFW node doesn't exist (and the reg == 0). Reviewed by: jake, tmm
2003-06-22 01:26:08 +00:00
if (i) {
#ifdef PSYCHO_DEBUG
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
printf("%s: read data error reading: %d.%d.%d: 0x%x\n",
__func__, bus, slot, func, reg);
add support for peeking at pci busses on UltraSparc systems. This prevents data access errors when trying to read/write to non-existant PCI devices. fix the psycho bridge to use peek for probing devices. This no longer fakes it if the OFW node doesn't exist (and the reg == 0). Reviewed by: jake, tmm
2003-06-22 01:26:08 +00:00
#endif
r = -1;
}
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
return (r);
}
static void
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
2007-03-07 21:13:51 +00:00
uint32_t val, int width)
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
{
struct psycho_softc *sc;
bus_space_handle_t bh;
u_long offset = 0;
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
sc = device_get_softc(dev);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
offset = PSYCHO_CONF_OFF(bus, slot, func, reg);
- Move the declaration of struct upa_ranges and the UPA_RANGE_* macros from sys/sparc64/include/ofw_upa.h to sys/sparc64/pci/ofw_pci.h and rename them to struct ofw_pci_ranges and OFW_PCI_RANGE_* respectively. This ranges struct only applies to host-PCI bridges but no to other bridges found on UPA. At the same time it applies to all host-PCI bridges regardless of whether the interconnection bus is Fireplane/ Safari, JBus or UPA. - While here rename the PCI_CS_* macros in sys/sparc64/pci/ofw_pci.h to OFW_PCI_CS_* in order to be consistent and change this header to use uintXX_t instead of u_intXX_t.
2005-12-03 19:52:20 +00:00
bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
switch (width) {
case 1:
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
break;
case 2:
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
break;
case 4:
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
break;
default:
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
panic("%s: bad width", __func__);
cosmetic changes and style fixes
2008-08-22 20:28:19 +00:00
/* NOTREACHED */
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
}
}
static int
Add the new sparc64 OFW PCI framework, conditional on options OFW_NEWPCI for now. It introduces a OFW PCI bus driver and a generic OFW PCI-PCI bridge driver. By utilizing these, the PCI handling is much more elegant now. The advantages of the new approach are: - Device enumeration should hopefully be more like on Solaris now, so unit numbers should match what's printed on the box more closely. - Real interrupt routing is implemented now, so cardbus bridges etc. have at least a chance to work. - The quirk tables are gone and have been replaced by (hopefully sufficient) heuristics. - Much cleaner code. There was also a report that previously bogus interrupt assignments are fixed now, which can be attributed to the new heuristics. A pitfall, and the reason why this is not the default yet, is that it changes device enumeration, as mentioned above, which can make it necessary to change the system configuration if more than one unit of a device type is present (on a system with two hme cars, for example, it is possible that hme0 becomes hme1 and vice versa after enabling the option). Systems with multiple disk controllers may need to be booted into single user (and require manual specification of the root file system on boot) to adjust the fstab. Nevertheless, I would like to encourage users to use this option, so that it can be made the default soon. In detail, the changes are: - Introduce an OFW PCI bus driver; it inherits most methods from the generic PCI bus driver, but uses the firmware for enumeration, performs additional initialization for devices and firmware-specific interrupt routing. It also implements an OFW-specific method to allow child devices to get their firmware nodes. - Introduce an OFW PCI-PCI bridge driver; again, it inherits most of the generic PCI-PCI bridge driver; it has it's own method for interrupt routing, as well as some sparc64-specific methods (one to get the node again, and one to adjust the bridge bus range, since we need to reenumerate all PCI buses). - Convert the apb driver to the new way of handling things. - Provide a common framework for OFW bridge drivers, used be the two drivers above. - Provide a small common framework for interrupt routing (for all bridge types). - Convert the psycho driver to the new framework; this gets rid of a bunch of old kludges in pci_read_config(), and the whole preinitialization (ofw_pci_init()). - Convert the ISA MD part and the EBus driver to the new way interrupts and nodes are handled. - Introduce types for firmware interrupt properties. - Rename the old sparcbus_if to ofw_pci_if by repo copy (it is only required for PCI), and move it to a more correct location (new support methodsx were also added, and an old one was deprecated). - Fix a bunch of minor bugs, perform some cleanups. In some cases, I introduced some minor code duplication to keep the new code clean, in hopes that the old code will be unifdef'ed soon. Reviewed in part by: imp Tested by: jake, Marius Strobl <marius@alchemy.franken.de>, Sergey Mokryshev <mokr@mokr.net>, Chris Jackman <cjackNOSPAM@klatsch.org> Info on u30 firmware provided by: kris
2003-07-01 14:52:47 +00:00
psycho_route_interrupt(device_t bridge, device_t dev, int pin)
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
{
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
struct psycho_softc *sc;
Add the new sparc64 OFW PCI framework, conditional on options OFW_NEWPCI for now. It introduces a OFW PCI bus driver and a generic OFW PCI-PCI bridge driver. By utilizing these, the PCI handling is much more elegant now. The advantages of the new approach are: - Device enumeration should hopefully be more like on Solaris now, so unit numbers should match what's printed on the box more closely. - Real interrupt routing is implemented now, so cardbus bridges etc. have at least a chance to work. - The quirk tables are gone and have been replaced by (hopefully sufficient) heuristics. - Much cleaner code. There was also a report that previously bogus interrupt assignments are fixed now, which can be attributed to the new heuristics. A pitfall, and the reason why this is not the default yet, is that it changes device enumeration, as mentioned above, which can make it necessary to change the system configuration if more than one unit of a device type is present (on a system with two hme cars, for example, it is possible that hme0 becomes hme1 and vice versa after enabling the option). Systems with multiple disk controllers may need to be booted into single user (and require manual specification of the root file system on boot) to adjust the fstab. Nevertheless, I would like to encourage users to use this option, so that it can be made the default soon. In detail, the changes are: - Introduce an OFW PCI bus driver; it inherits most methods from the generic PCI bus driver, but uses the firmware for enumeration, performs additional initialization for devices and firmware-specific interrupt routing. It also implements an OFW-specific method to allow child devices to get their firmware nodes. - Introduce an OFW PCI-PCI bridge driver; again, it inherits most of the generic PCI-PCI bridge driver; it has it's own method for interrupt routing, as well as some sparc64-specific methods (one to get the node again, and one to adjust the bridge bus range, since we need to reenumerate all PCI buses). - Convert the apb driver to the new way of handling things. - Provide a common framework for OFW bridge drivers, used be the two drivers above. - Provide a small common framework for interrupt routing (for all bridge types). - Convert the psycho driver to the new framework; this gets rid of a bunch of old kludges in pci_read_config(), and the whole preinitialization (ofw_pci_init()). - Convert the ISA MD part and the EBus driver to the new way interrupts and nodes are handled. - Introduce types for firmware interrupt properties. - Rename the old sparcbus_if to ofw_pci_if by repo copy (it is only required for PCI), and move it to a more correct location (new support methodsx were also added, and an old one was deprecated). - Fix a bunch of minor bugs, perform some cleanups. In some cases, I introduced some minor code duplication to keep the new code clean, in hopes that the old code will be unifdef'ed soon. Reviewed in part by: imp Tested by: jake, Marius Strobl <marius@alchemy.franken.de>, Sergey Mokryshev <mokr@mokr.net>, Chris Jackman <cjackNOSPAM@klatsch.org> Info on u30 firmware provided by: kris
2003-07-01 14:52:47 +00:00
struct ofw_pci_register reg;
bus_addr_t intrmap;
ofw_pci_intr_t pintr, mintr;
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
uint8_t maskbuf[sizeof(reg) + sizeof(pintr)];
Add the new sparc64 OFW PCI framework, conditional on options OFW_NEWPCI for now. It introduces a OFW PCI bus driver and a generic OFW PCI-PCI bridge driver. By utilizing these, the PCI handling is much more elegant now. The advantages of the new approach are: - Device enumeration should hopefully be more like on Solaris now, so unit numbers should match what's printed on the box more closely. - Real interrupt routing is implemented now, so cardbus bridges etc. have at least a chance to work. - The quirk tables are gone and have been replaced by (hopefully sufficient) heuristics. - Much cleaner code. There was also a report that previously bogus interrupt assignments are fixed now, which can be attributed to the new heuristics. A pitfall, and the reason why this is not the default yet, is that it changes device enumeration, as mentioned above, which can make it necessary to change the system configuration if more than one unit of a device type is present (on a system with two hme cars, for example, it is possible that hme0 becomes hme1 and vice versa after enabling the option). Systems with multiple disk controllers may need to be booted into single user (and require manual specification of the root file system on boot) to adjust the fstab. Nevertheless, I would like to encourage users to use this option, so that it can be made the default soon. In detail, the changes are: - Introduce an OFW PCI bus driver; it inherits most methods from the generic PCI bus driver, but uses the firmware for enumeration, performs additional initialization for devices and firmware-specific interrupt routing. It also implements an OFW-specific method to allow child devices to get their firmware nodes. - Introduce an OFW PCI-PCI bridge driver; again, it inherits most of the generic PCI-PCI bridge driver; it has it's own method for interrupt routing, as well as some sparc64-specific methods (one to get the node again, and one to adjust the bridge bus range, since we need to reenumerate all PCI buses). - Convert the apb driver to the new way of handling things. - Provide a common framework for OFW bridge drivers, used be the two drivers above. - Provide a small common framework for interrupt routing (for all bridge types). - Convert the psycho driver to the new framework; this gets rid of a bunch of old kludges in pci_read_config(), and the whole preinitialization (ofw_pci_init()). - Convert the ISA MD part and the EBus driver to the new way interrupts and nodes are handled. - Introduce types for firmware interrupt properties. - Rename the old sparcbus_if to ofw_pci_if by repo copy (it is only required for PCI), and move it to a more correct location (new support methodsx were also added, and an old one was deprecated). - Fix a bunch of minor bugs, perform some cleanups. In some cases, I introduced some minor code duplication to keep the new code clean, in hopes that the old code will be unifdef'ed soon. Reviewed in part by: imp Tested by: jake, Marius Strobl <marius@alchemy.franken.de>, Sergey Mokryshev <mokr@mokr.net>, Chris Jackman <cjackNOSPAM@klatsch.org> Info on u30 firmware provided by: kris
2003-07-01 14:52:47 +00:00
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
sc = device_get_softc(bridge);
Add the new sparc64 OFW PCI framework, conditional on options OFW_NEWPCI for now. It introduces a OFW PCI bus driver and a generic OFW PCI-PCI bridge driver. By utilizing these, the PCI handling is much more elegant now. The advantages of the new approach are: - Device enumeration should hopefully be more like on Solaris now, so unit numbers should match what's printed on the box more closely. - Real interrupt routing is implemented now, so cardbus bridges etc. have at least a chance to work. - The quirk tables are gone and have been replaced by (hopefully sufficient) heuristics. - Much cleaner code. There was also a report that previously bogus interrupt assignments are fixed now, which can be attributed to the new heuristics. A pitfall, and the reason why this is not the default yet, is that it changes device enumeration, as mentioned above, which can make it necessary to change the system configuration if more than one unit of a device type is present (on a system with two hme cars, for example, it is possible that hme0 becomes hme1 and vice versa after enabling the option). Systems with multiple disk controllers may need to be booted into single user (and require manual specification of the root file system on boot) to adjust the fstab. Nevertheless, I would like to encourage users to use this option, so that it can be made the default soon. In detail, the changes are: - Introduce an OFW PCI bus driver; it inherits most methods from the generic PCI bus driver, but uses the firmware for enumeration, performs additional initialization for devices and firmware-specific interrupt routing. It also implements an OFW-specific method to allow child devices to get their firmware nodes. - Introduce an OFW PCI-PCI bridge driver; again, it inherits most of the generic PCI-PCI bridge driver; it has it's own method for interrupt routing, as well as some sparc64-specific methods (one to get the node again, and one to adjust the bridge bus range, since we need to reenumerate all PCI buses). - Convert the apb driver to the new way of handling things. - Provide a common framework for OFW bridge drivers, used be the two drivers above. - Provide a small common framework for interrupt routing (for all bridge types). - Convert the psycho driver to the new framework; this gets rid of a bunch of old kludges in pci_read_config(), and the whole preinitialization (ofw_pci_init()). - Convert the ISA MD part and the EBus driver to the new way interrupts and nodes are handled. - Introduce types for firmware interrupt properties. - Rename the old sparcbus_if to ofw_pci_if by repo copy (it is only required for PCI), and move it to a more correct location (new support methodsx were also added, and an old one was deprecated). - Fix a bunch of minor bugs, perform some cleanups. In some cases, I introduced some minor code duplication to keep the new code clean, in hopes that the old code will be unifdef'ed soon. Reviewed in part by: imp Tested by: jake, Marius Strobl <marius@alchemy.franken.de>, Sergey Mokryshev <mokr@mokr.net>, Chris Jackman <cjackNOSPAM@klatsch.org> Info on u30 firmware provided by: kris
2003-07-01 14:52:47 +00:00
pintr = pin;
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, &reg,
sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf))
Add the new sparc64 OFW PCI framework, conditional on options OFW_NEWPCI for now. It introduces a OFW PCI bus driver and a generic OFW PCI-PCI bridge driver. By utilizing these, the PCI handling is much more elegant now. The advantages of the new approach are: - Device enumeration should hopefully be more like on Solaris now, so unit numbers should match what's printed on the box more closely. - Real interrupt routing is implemented now, so cardbus bridges etc. have at least a chance to work. - The quirk tables are gone and have been replaced by (hopefully sufficient) heuristics. - Much cleaner code. There was also a report that previously bogus interrupt assignments are fixed now, which can be attributed to the new heuristics. A pitfall, and the reason why this is not the default yet, is that it changes device enumeration, as mentioned above, which can make it necessary to change the system configuration if more than one unit of a device type is present (on a system with two hme cars, for example, it is possible that hme0 becomes hme1 and vice versa after enabling the option). Systems with multiple disk controllers may need to be booted into single user (and require manual specification of the root file system on boot) to adjust the fstab. Nevertheless, I would like to encourage users to use this option, so that it can be made the default soon. In detail, the changes are: - Introduce an OFW PCI bus driver; it inherits most methods from the generic PCI bus driver, but uses the firmware for enumeration, performs additional initialization for devices and firmware-specific interrupt routing. It also implements an OFW-specific method to allow child devices to get their firmware nodes. - Introduce an OFW PCI-PCI bridge driver; again, it inherits most of the generic PCI-PCI bridge driver; it has it's own method for interrupt routing, as well as some sparc64-specific methods (one to get the node again, and one to adjust the bridge bus range, since we need to reenumerate all PCI buses). - Convert the apb driver to the new way of handling things. - Provide a common framework for OFW bridge drivers, used be the two drivers above. - Provide a small common framework for interrupt routing (for all bridge types). - Convert the psycho driver to the new framework; this gets rid of a bunch of old kludges in pci_read_config(), and the whole preinitialization (ofw_pci_init()). - Convert the ISA MD part and the EBus driver to the new way interrupts and nodes are handled. - Introduce types for firmware interrupt properties. - Rename the old sparcbus_if to ofw_pci_if by repo copy (it is only required for PCI), and move it to a more correct location (new support methodsx were also added, and an old one was deprecated). - Fix a bunch of minor bugs, perform some cleanups. In some cases, I introduced some minor code duplication to keep the new code clean, in hopes that the old code will be unifdef'ed soon. Reviewed in part by: imp Tested by: jake, Marius Strobl <marius@alchemy.franken.de>, Sergey Mokryshev <mokr@mokr.net>, Chris Jackman <cjackNOSPAM@klatsch.org> Info on u30 firmware provided by: kris
2003-07-01 14:52:47 +00:00
return (mintr);
/*
* If this is outside of the range for an intpin, it's likely a full
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
* INO, and no mapping is required at all; this happens on the U30,
- Use the name returned by device_get_nameunit(9) for the name of the counter-timer timecounter so the associated SYSCTL nodes don't clash on machines having multiple U2P and U2S bridges as well as establishing a clear mapping between these bridges and their timecounter device. - Don't bother setting up a "nice" name for the IOMMU, just use the name returned by device_get_nameunit(9), too. - Fix some minor style(9) bugs. - Use __FBSDID in counter.c MFC after: 1 week
2008-05-07 21:22:15 +00:00
* where there's no interrupt map at the Psycho node. Fortunately,
Add the new sparc64 OFW PCI framework, conditional on options OFW_NEWPCI for now. It introduces a OFW PCI bus driver and a generic OFW PCI-PCI bridge driver. By utilizing these, the PCI handling is much more elegant now. The advantages of the new approach are: - Device enumeration should hopefully be more like on Solaris now, so unit numbers should match what's printed on the box more closely. - Real interrupt routing is implemented now, so cardbus bridges etc. have at least a chance to work. - The quirk tables are gone and have been replaced by (hopefully sufficient) heuristics. - Much cleaner code. There was also a report that previously bogus interrupt assignments are fixed now, which can be attributed to the new heuristics. A pitfall, and the reason why this is not the default yet, is that it changes device enumeration, as mentioned above, which can make it necessary to change the system configuration if more than one unit of a device type is present (on a system with two hme cars, for example, it is possible that hme0 becomes hme1 and vice versa after enabling the option). Systems with multiple disk controllers may need to be booted into single user (and require manual specification of the root file system on boot) to adjust the fstab. Nevertheless, I would like to encourage users to use this option, so that it can be made the default soon. In detail, the changes are: - Introduce an OFW PCI bus driver; it inherits most methods from the generic PCI bus driver, but uses the firmware for enumeration, performs additional initialization for devices and firmware-specific interrupt routing. It also implements an OFW-specific method to allow child devices to get their firmware nodes. - Introduce an OFW PCI-PCI bridge driver; again, it inherits most of the generic PCI-PCI bridge driver; it has it's own method for interrupt routing, as well as some sparc64-specific methods (one to get the node again, and one to adjust the bridge bus range, since we need to reenumerate all PCI buses). - Convert the apb driver to the new way of handling things. - Provide a common framework for OFW bridge drivers, used be the two drivers above. - Provide a small common framework for interrupt routing (for all bridge types). - Convert the psycho driver to the new framework; this gets rid of a bunch of old kludges in pci_read_config(), and the whole preinitialization (ofw_pci_init()). - Convert the ISA MD part and the EBus driver to the new way interrupts and nodes are handled. - Introduce types for firmware interrupt properties. - Rename the old sparcbus_if to ofw_pci_if by repo copy (it is only required for PCI), and move it to a more correct location (new support methodsx were also added, and an old one was deprecated). - Fix a bunch of minor bugs, perform some cleanups. In some cases, I introduced some minor code duplication to keep the new code clean, in hopes that the old code will be unifdef'ed soon. Reviewed in part by: imp Tested by: jake, Marius Strobl <marius@alchemy.franken.de>, Sergey Mokryshev <mokr@mokr.net>, Chris Jackman <cjackNOSPAM@klatsch.org> Info on u30 firmware provided by: kris
2003-07-01 14:52:47 +00:00
* there seem to be no INOs in the intpin range on this boxen, so
* this easy heuristics will do.
*/
if (pin > 4)
return (pin);
/*
* Guess the INO; we always assume that this is a non-OBIO
- Use the name returned by device_get_nameunit(9) for the name of the counter-timer timecounter so the associated SYSCTL nodes don't clash on machines having multiple U2P and U2S bridges as well as establishing a clear mapping between these bridges and their timecounter device. - Don't bother setting up a "nice" name for the IOMMU, just use the name returned by device_get_nameunit(9), too. - Fix some minor style(9) bugs. - Use __FBSDID in counter.c MFC after: 1 week
2008-05-07 21:22:15 +00:00
* device, and that pin is a "real" intpin number. Determine
Add the new sparc64 OFW PCI framework, conditional on options OFW_NEWPCI for now. It introduces a OFW PCI bus driver and a generic OFW PCI-PCI bridge driver. By utilizing these, the PCI handling is much more elegant now. The advantages of the new approach are: - Device enumeration should hopefully be more like on Solaris now, so unit numbers should match what's printed on the box more closely. - Real interrupt routing is implemented now, so cardbus bridges etc. have at least a chance to work. - The quirk tables are gone and have been replaced by (hopefully sufficient) heuristics. - Much cleaner code. There was also a report that previously bogus interrupt assignments are fixed now, which can be attributed to the new heuristics. A pitfall, and the reason why this is not the default yet, is that it changes device enumeration, as mentioned above, which can make it necessary to change the system configuration if more than one unit of a device type is present (on a system with two hme cars, for example, it is possible that hme0 becomes hme1 and vice versa after enabling the option). Systems with multiple disk controllers may need to be booted into single user (and require manual specification of the root file system on boot) to adjust the fstab. Nevertheless, I would like to encourage users to use this option, so that it can be made the default soon. In detail, the changes are: - Introduce an OFW PCI bus driver; it inherits most methods from the generic PCI bus driver, but uses the firmware for enumeration, performs additional initialization for devices and firmware-specific interrupt routing. It also implements an OFW-specific method to allow child devices to get their firmware nodes. - Introduce an OFW PCI-PCI bridge driver; again, it inherits most of the generic PCI-PCI bridge driver; it has it's own method for interrupt routing, as well as some sparc64-specific methods (one to get the node again, and one to adjust the bridge bus range, since we need to reenumerate all PCI buses). - Convert the apb driver to the new way of handling things. - Provide a common framework for OFW bridge drivers, used be the two drivers above. - Provide a small common framework for interrupt routing (for all bridge types). - Convert the psycho driver to the new framework; this gets rid of a bunch of old kludges in pci_read_config(), and the whole preinitialization (ofw_pci_init()). - Convert the ISA MD part and the EBus driver to the new way interrupts and nodes are handled. - Introduce types for firmware interrupt properties. - Rename the old sparcbus_if to ofw_pci_if by repo copy (it is only required for PCI), and move it to a more correct location (new support methodsx were also added, and an old one was deprecated). - Fix a bunch of minor bugs, perform some cleanups. In some cases, I introduced some minor code duplication to keep the new code clean, in hopes that the old code will be unifdef'ed soon. Reviewed in part by: imp Tested by: jake, Marius Strobl <marius@alchemy.franken.de>, Sergey Mokryshev <mokr@mokr.net>, Chris Jackman <cjackNOSPAM@klatsch.org> Info on u30 firmware provided by: kris
2003-07-01 14:52:47 +00:00
* the mapping register to be used by the slot number.
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
* We only need to do this on E450s, it seems; here, the slot numbers
Add the new sparc64 OFW PCI framework, conditional on options OFW_NEWPCI for now. It introduces a OFW PCI bus driver and a generic OFW PCI-PCI bridge driver. By utilizing these, the PCI handling is much more elegant now. The advantages of the new approach are: - Device enumeration should hopefully be more like on Solaris now, so unit numbers should match what's printed on the box more closely. - Real interrupt routing is implemented now, so cardbus bridges etc. have at least a chance to work. - The quirk tables are gone and have been replaced by (hopefully sufficient) heuristics. - Much cleaner code. There was also a report that previously bogus interrupt assignments are fixed now, which can be attributed to the new heuristics. A pitfall, and the reason why this is not the default yet, is that it changes device enumeration, as mentioned above, which can make it necessary to change the system configuration if more than one unit of a device type is present (on a system with two hme cars, for example, it is possible that hme0 becomes hme1 and vice versa after enabling the option). Systems with multiple disk controllers may need to be booted into single user (and require manual specification of the root file system on boot) to adjust the fstab. Nevertheless, I would like to encourage users to use this option, so that it can be made the default soon. In detail, the changes are: - Introduce an OFW PCI bus driver; it inherits most methods from the generic PCI bus driver, but uses the firmware for enumeration, performs additional initialization for devices and firmware-specific interrupt routing. It also implements an OFW-specific method to allow child devices to get their firmware nodes. - Introduce an OFW PCI-PCI bridge driver; again, it inherits most of the generic PCI-PCI bridge driver; it has it's own method for interrupt routing, as well as some sparc64-specific methods (one to get the node again, and one to adjust the bridge bus range, since we need to reenumerate all PCI buses). - Convert the apb driver to the new way of handling things. - Provide a common framework for OFW bridge drivers, used be the two drivers above. - Provide a small common framework for interrupt routing (for all bridge types). - Convert the psycho driver to the new framework; this gets rid of a bunch of old kludges in pci_read_config(), and the whole preinitialization (ofw_pci_init()). - Convert the ISA MD part and the EBus driver to the new way interrupts and nodes are handled. - Introduce types for firmware interrupt properties. - Rename the old sparcbus_if to ofw_pci_if by repo copy (it is only required for PCI), and move it to a more correct location (new support methodsx were also added, and an old one was deprecated). - Fix a bunch of minor bugs, perform some cleanups. In some cases, I introduced some minor code duplication to keep the new code clean, in hopes that the old code will be unifdef'ed soon. Reviewed in part by: imp Tested by: jake, Marius Strobl <marius@alchemy.franken.de>, Sergey Mokryshev <mokr@mokr.net>, Chris Jackman <cjackNOSPAM@klatsch.org> Info on u30 firmware provided by: kris
2003-07-01 14:52:47 +00:00
* for bus A are one-based, while those for bus B seemingly have an
* offset of 2 (hence the factor of 3 below).
*/
intrmap = PSR_PCIA0_INT_MAP +
8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half);
mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1;
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
device_printf(bridge, "guessing interrupt %d for device %d.%d pin %d\n",
Add the new sparc64 OFW PCI framework, conditional on options OFW_NEWPCI for now. It introduces a OFW PCI bus driver and a generic OFW PCI-PCI bridge driver. By utilizing these, the PCI handling is much more elegant now. The advantages of the new approach are: - Device enumeration should hopefully be more like on Solaris now, so unit numbers should match what's printed on the box more closely. - Real interrupt routing is implemented now, so cardbus bridges etc. have at least a chance to work. - The quirk tables are gone and have been replaced by (hopefully sufficient) heuristics. - Much cleaner code. There was also a report that previously bogus interrupt assignments are fixed now, which can be attributed to the new heuristics. A pitfall, and the reason why this is not the default yet, is that it changes device enumeration, as mentioned above, which can make it necessary to change the system configuration if more than one unit of a device type is present (on a system with two hme cars, for example, it is possible that hme0 becomes hme1 and vice versa after enabling the option). Systems with multiple disk controllers may need to be booted into single user (and require manual specification of the root file system on boot) to adjust the fstab. Nevertheless, I would like to encourage users to use this option, so that it can be made the default soon. In detail, the changes are: - Introduce an OFW PCI bus driver; it inherits most methods from the generic PCI bus driver, but uses the firmware for enumeration, performs additional initialization for devices and firmware-specific interrupt routing. It also implements an OFW-specific method to allow child devices to get their firmware nodes. - Introduce an OFW PCI-PCI bridge driver; again, it inherits most of the generic PCI-PCI bridge driver; it has it's own method for interrupt routing, as well as some sparc64-specific methods (one to get the node again, and one to adjust the bridge bus range, since we need to reenumerate all PCI buses). - Convert the apb driver to the new way of handling things. - Provide a common framework for OFW bridge drivers, used be the two drivers above. - Provide a small common framework for interrupt routing (for all bridge types). - Convert the psycho driver to the new framework; this gets rid of a bunch of old kludges in pci_read_config(), and the whole preinitialization (ofw_pci_init()). - Convert the ISA MD part and the EBus driver to the new way interrupts and nodes are handled. - Introduce types for firmware interrupt properties. - Rename the old sparcbus_if to ofw_pci_if by repo copy (it is only required for PCI), and move it to a more correct location (new support methodsx were also added, and an old one was deprecated). - Fix a bunch of minor bugs, perform some cleanups. In some cases, I introduced some minor code duplication to keep the new code clean, in hopes that the old code will be unifdef'ed soon. Reviewed in part by: imp Tested by: jake, Marius Strobl <marius@alchemy.franken.de>, Sergey Mokryshev <mokr@mokr.net>, Chris Jackman <cjackNOSPAM@klatsch.org> Info on u30 firmware provided by: kris
2003-07-01 14:52:47 +00:00
(int)mintr, pci_get_slot(dev), pci_get_function(dev), pin);
return (mintr);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
}
static int
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
{
struct psycho_softc *sc;
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
sc = device_get_softc(dev);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
switch (which) {
Make the PCI code aware of PCI domains (aka PCI segments) so we can support machines having multiple independently numbered PCI domains and don't support reenumeration without ambiguity amongst the devices as seen by the OS and represented by PCI location strings. This includes introducing a function pci_find_dbsf(9) which works like pci_find_bsf(9) but additionally takes a domain number argument and limiting pci_find_bsf(9) to only search devices in domain 0 (the only domain in single-domain systems). Bge(4) and ofw_pcibus(4) are changed to use pci_find_dbsf(9) instead of pci_find_bsf(9) in order to no longer report false positives when searching for siblings and dupe devices in the same domain respectively. Along with this change the sole host-PCI bridge driver converted to actually make use of PCI domain support is uninorth(4), the others continue to use domain 0 only for now and need to be converted as appropriate later on. Note that this means that the format of the location strings as used by pciconf(8) has been changed and that consumers of <sys/pciio.h> potentially need to be recompiled. Suggested by: jhb Reviewed by: grehan, jhb, marcel Approved by: re (kensmith), jhb (PCI maintainer hat)
2007-09-30 11:05:18 +00:00
case PCIB_IVAR_DOMAIN:
On sparc64 machines with multiple host-PCI-bridges these bridges have separate configuration spaces so by definition they implement different PCI domains. Thus change psycho(4) to use PCI domains instead of reenumerating all PCI busses so they have globally unique bus numbers and drop support for reenumerating busses in the OFW PCI code. According to CVS history reenumeration was also required in order to get some E450 to boot but given that no other open source kernel changes the PCI bus numbers assigned by the firmware I believe the real problem was that the old code used the bus number as the device number for the PCI busses and unlike most of the other machines the firmwares of the problematic ones don't use disjoint PCI bus numbers across the host-PCI-bridges. MFC after: 1 month
2008-04-17 12:38:00 +00:00
*result = device_get_unit(dev);
Make the PCI code aware of PCI domains (aka PCI segments) so we can support machines having multiple independently numbered PCI domains and don't support reenumeration without ambiguity amongst the devices as seen by the OS and represented by PCI location strings. This includes introducing a function pci_find_dbsf(9) which works like pci_find_bsf(9) but additionally takes a domain number argument and limiting pci_find_bsf(9) to only search devices in domain 0 (the only domain in single-domain systems). Bge(4) and ofw_pcibus(4) are changed to use pci_find_dbsf(9) instead of pci_find_bsf(9) in order to no longer report false positives when searching for siblings and dupe devices in the same domain respectively. Along with this change the sole host-PCI bridge driver converted to actually make use of PCI domain support is uninorth(4), the others continue to use domain 0 only for now and need to be converted as appropriate later on. Note that this means that the format of the location strings as used by pciconf(8) has been changed and that consumers of <sys/pciio.h> potentially need to be recompiled. Suggested by: jhb Reviewed by: grehan, jhb, marcel Approved by: re (kensmith), jhb (PCI maintainer hat)
2007-09-30 11:05:18 +00:00
return (0);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
case PCIB_IVAR_BUS:
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
*result = sc->sc_pci_secbus;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
return (0);
}
return (ENOENT);
}
o break newbus api: add a new argument of type driver_filter_t to bus_setup_intr() o add an int return code to all fast handlers o retire INTR_FAST/IH_FAST For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current Reviewed by: many Approved by: re@
2007-02-23 12:19:07 +00:00
static int
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
psycho_dma_sync_stub(void *arg)
Teach the bridge wrapper how to handle the filter+ithread case. Reviewed by: marius
2007-06-06 22:19:23 +00:00
{
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
struct psycho_dma_sync *pds = arg;
Teach the bridge wrapper how to handle the filter+ithread case. Reviewed by: marius
2007-06-06 22:19:23 +00:00
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
(void)PCIB_READ_CONFIG(pds->pds_ppb, pds->pds_bus, pds->pds_slot,
pds->pds_func, PCIR_VENDOR, 2);
(void)PSYCHO_READ8(pds->pds_sc, PSR_DMA_WRITE_SYNC);
return (pds->pds_handler(pds->pds_arg));
Teach the bridge wrapper how to handle the filter+ithread case. Reviewed by: marius
2007-06-06 22:19:23 +00:00
}
static void
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
psycho_intr_enable(void *arg)
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
{
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
struct intr_vector *iv = arg;
struct psycho_icarg *pica = iv->iv_icarg;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
PSYCHO_WRITE8(pica->pica_sc, pica->pica_map,
INTMAP_ENABLE(iv->iv_vec, iv->iv_mid));
}
static void
psycho_intr_disable(void *arg)
{
struct intr_vector *iv = arg;
struct psycho_icarg *pica = iv->iv_icarg;
PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, iv->iv_vec);
}
static void
o Rename ic_eoi to ic_clear to emphasize the functions it points don't send and EOI which works like on amd64/i386 and blocks all interrupts on the relevant interrupt controller. o Replace the post_filter and post_inthread hooks registered when creating the interrupt events with just ic_clear as on sparc64 we don't need to do any disable->EOI->enable dance to unblock all but the relevant interrupt while running the filter or handler; just not clearing the interrupt already has the same effect. o Merge from amd64/i386: - Split the intr_table_lock into an sx lock used for most things, and a spin lock to protect intrcnt_index. - Add support for binding interrupts to CPUs, including for the bus_bind_intr(9) interface, a assign_cpu hook and initially shuffling interrupts arround in a round-robin fashion. Reviewed by: jhb MFC after: 1 month
2008-04-23 20:04:38 +00:00
psycho_intr_assign(void *arg)
{
struct intr_vector *iv = arg;
struct psycho_icarg *pica = iv->iv_icarg;
PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, INTMAP_TID(
PSYCHO_READ8(pica->pica_sc, pica->pica_map), iv->iv_mid));
}
static void
psycho_intr_clear(void *arg)
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
{
struct intr_vector *iv = arg;
struct psycho_icarg *pica = iv->iv_icarg;
PSYCHO_WRITE8(pica->pica_sc, pica->pica_clr, 0);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
}
static int
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
psycho_setup_intr(device_t dev, device_t child, struct resource *ires,
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
2007-03-07 21:13:51 +00:00
int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
o break newbus api: add a new argument of type driver_filter_t to bus_setup_intr() o add an int return code to all fast handlers o retire INTR_FAST/IH_FAST For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current Reviewed by: many Approved by: re@
2007-02-23 12:19:07 +00:00
void **cookiep)
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
{
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
struct {
int apb:1;
int ppb:1;
} found;
devclass_t pci_devclass;
device_t cdev, pdev, pcidev;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
struct psycho_softc *sc;
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
struct psycho_dma_sync *pds;
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
u_long vec;
int error;
o break newbus api: add a new argument of type driver_filter_t to bus_setup_intr() o add an int return code to all fast handlers o retire INTR_FAST/IH_FAST For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current Reviewed by: many Approved by: re@
2007-02-23 12:19:07 +00:00
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
sc = device_get_softc(dev);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
/*
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
* Make sure the vector is fully specified and we registered
* our interrupt controller for it.
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
*/
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
vec = rman_get_start(ires);
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
if (INTIGN(vec) != sc->sc_ign ||
intr_vectors[vec].iv_ic != &psycho_ic) {
device_printf(dev, "invalid interrupt vector 0x%lx\n", vec);
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
return (EINVAL);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
}
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
/*
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
* The Sabre-APB-combination does not automatically flush DMA
* write data for devices behind additional PCI-PCI bridges
* underneath the APB PCI-PCI bridge. The procedure for a
* manual flush is to do a PIO read on the far side of the
* farthest PCI-PCI bridge followed by a read of the PCI DMA
* write sync register of the Sabre.
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
*/
if (sc->sc_mode == PSYCHO_MODE_SABRE) {
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
pds = malloc(sizeof(*pds), M_DEVBUF, M_NOWAIT | M_ZERO);
if (pds == NULL)
return (ENOMEM);
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
pcidev = NULL;
found.apb = found.ppb = 0;
pci_devclass = devclass_find("pci");
for (cdev = child; cdev != dev; cdev = pdev) {
pdev = device_get_parent(cdev);
if (pcidev == NULL) {
if (device_get_devclass(pdev) != pci_devclass)
continue;
pcidev = cdev;
continue;
}
/*
* NB: APB would also match as PCI-PCI bridges.
*/
if (pci_get_vendor(cdev) == 0x108e &&
pci_get_device(cdev) == 0x5000) {
found.apb = 1;
break;
}
if (pci_get_class(cdev) == PCIC_BRIDGE &&
pci_get_subclass(cdev) == PCIS_BRIDGE_PCI)
found.ppb = 1;
}
if (found.apb && found.ppb && pcidev != NULL) {
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
pds->pds_sc = sc;
pds->pds_arg = arg;
pds->pds_ppb =
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
device_get_parent(device_get_parent(pcidev));
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
pds->pds_bus = pci_get_bus(pcidev);
pds->pds_slot = pci_get_slot(pcidev);
pds->pds_func = pci_get_function(pcidev);
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
if (bootverbose)
device_printf(dev, "installed DMA sync "
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
"wrapper for device %d.%d on bus %d\n",
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
pds->pds_slot, pds->pds_func,
pds->pds_bus);
if (intr == NULL) {
pds->pds_handler = filt;
error = bus_generic_setup_intr(dev, child,
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
ires, flags, psycho_dma_sync_stub, intr,
pds, cookiep);
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
} else {
pds->pds_handler = (driver_filter_t *)intr;
error = bus_generic_setup_intr(dev, child,
ires, flags, filt,
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
(driver_intr_t *)psycho_dma_sync_stub,
pds, cookiep);
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
}
} else
error = bus_generic_setup_intr(dev, child, ires,
flags, filt, intr, arg, cookiep);
if (error != 0) {
free(pds, M_DEVBUF);
return (error);
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
}
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
pds->pds_cookie = *cookiep;
*cookiep = pds;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
return (error);
}
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr,
arg, cookiep));
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
}
static int
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
psycho_teardown_intr(device_t dev, device_t child, struct resource *vec,
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
2007-03-07 21:13:51 +00:00
void *cookie)
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
{
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
struct psycho_softc *sc;
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
struct psycho_dma_sync *pds;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
int error;
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
sc = device_get_softc(dev);
if (sc->sc_mode == PSYCHO_MODE_SABRE) {
pds = cookie;
error = bus_generic_teardown_intr(dev, child, vec,
pds->pds_cookie);
if (error == 0)
free(pds, M_DEVBUF);
return (error);
}
return (bus_generic_teardown_intr(dev, child, vec, cookie));
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
}
static struct resource *
psycho_alloc_resource(device_t bus, device_t child, int type, int *rid,
u_long start, u_long end, u_long count, u_int flags)
{
struct psycho_softc *sc;
struct resource *rv;
struct rman *rm;
bus_space_tag_t bt;
bus_space_handle_t bh;
int needactivate = flags & RF_ACTIVE;
flags &= ~RF_ACTIVE;
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
sc = device_get_softc(bus);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
if (type == SYS_RES_IRQ) {
/*
* XXX: Don't accept blank ranges for now, only single
- Use the name returned by device_get_nameunit(9) for the name of the counter-timer timecounter so the associated SYSCTL nodes don't clash on machines having multiple U2P and U2S bridges as well as establishing a clear mapping between these bridges and their timecounter device. - Don't bother setting up a "nice" name for the IOMMU, just use the name returned by device_get_nameunit(9), too. - Fix some minor style(9) bugs. - Use __FBSDID in counter.c MFC after: 1 week
2008-05-07 21:22:15 +00:00
* interrupts. The other case should not happen with
* the MI PCI code...
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
* XXX: This may return a resource that is out of the
- Use the name returned by device_get_nameunit(9) for the name of the counter-timer timecounter so the associated SYSCTL nodes don't clash on machines having multiple U2P and U2S bridges as well as establishing a clear mapping between these bridges and their timecounter device. - Don't bother setting up a "nice" name for the IOMMU, just use the name returned by device_get_nameunit(9), too. - Fix some minor style(9) bugs. - Use __FBSDID in counter.c MFC after: 1 week
2008-05-07 21:22:15 +00:00
* range that was specified. Is this correct...?
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
*/
if (start != end)
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
panic("%s: XXX: interrupt range", __func__);
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
start = end = INTMAP_VEC(sc->sc_ign, end);
Some code cleanup: - Fix some comments; remove numerous superfluous or outdated ones. - Correctly pass on the requesting device when handing requests up to the parent bus. - Use the complete device name, including unit number, to build the IOMMU instance name. - Inline a function that was only used once, and was trivial.
2004-04-25 00:30:28 +00:00
return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type,
rid, start, end, count, flags));
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
}
switch (type) {
case SYS_RES_MEMORY:
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
rm = &sc->sc_pci_mem_rman;
bt = sc->sc_pci_memt;
- Move the declaration of struct upa_ranges and the UPA_RANGE_* macros from sys/sparc64/include/ofw_upa.h to sys/sparc64/pci/ofw_pci.h and rename them to struct ofw_pci_ranges and OFW_PCI_RANGE_* respectively. This ranges struct only applies to host-PCI bridges but no to other bridges found on UPA. At the same time it applies to all host-PCI bridges regardless of whether the interconnection bus is Fireplane/ Safari, JBus or UPA. - While here rename the PCI_CS_* macros in sys/sparc64/pci/ofw_pci.h to OFW_PCI_CS_* in order to be consistent and change this header to use uintXX_t instead of u_intXX_t.
2005-12-03 19:52:20 +00:00
bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32];
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
break;
case SYS_RES_IOPORT:
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
rm = &sc->sc_pci_io_rman;
bt = sc->sc_pci_iot;
- Move the declaration of struct upa_ranges and the UPA_RANGE_* macros from sys/sparc64/include/ofw_upa.h to sys/sparc64/pci/ofw_pci.h and rename them to struct ofw_pci_ranges and OFW_PCI_RANGE_* respectively. This ranges struct only applies to host-PCI bridges but no to other bridges found on UPA. At the same time it applies to all host-PCI bridges regardless of whether the interconnection bus is Fireplane/ Safari, JBus or UPA. - While here rename the PCI_CS_* macros in sys/sparc64/pci/ofw_pci.h to OFW_PCI_CS_* in order to be consistent and change this header to use uintXX_t instead of u_intXX_t.
2005-12-03 19:52:20 +00:00
bh = sc->sc_pci_bh[OFW_PCI_CS_IO];
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
break;
default:
return (NULL);
cosmetic changes and style fixes
2008-08-22 20:28:19 +00:00
/* NOTREACHED */
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
}
rv = rman_reserve_resource(rm, start, end, count, flags, child);
if (rv == NULL)
return (NULL);
Set the rid for any resource obtained from rman_reserve_resource. Reviewed by: wollman, jmg (as were the other commits fixing this problem)
2006-04-20 04:20:41 +00:00
rman_set_rid(rv, *rid);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
bh += rman_get_start(rv);
rman_set_bustag(rv, bt);
Add a workaround for quirky PCI devices that set the intpin register to 0, but use this mechanism to generate interrupts. Preserve the child device when setting up and tearing down interrupts. Some style nits.
2001-12-21 21:35:47 +00:00
rman_set_bushandle(rv, bh);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
if (needactivate) {
if (bus_activate_resource(child, type, *rid, rv)) {
rman_release_resource(rv);
return (NULL);
}
}
return (rv);
}
static int
psycho_activate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
{
Map the device memory belonging to resources of type SYS_RES_MEMORY into KVA upon activation so that rman_get_virtual() works as expected.
2002-03-24 01:51:29 +00:00
void *p;
int error;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
if (type == SYS_RES_IRQ)
Some code cleanup: - Fix some comments; remove numerous superfluous or outdated ones. - Correctly pass on the requesting device when handing requests up to the parent bus. - Use the complete device name, including unit number, to build the IOMMU instance name. - Inline a function that was only used once, and was trivial.
2004-04-25 00:30:28 +00:00
return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child,
type, rid, r));
Map the device memory belonging to resources of type SYS_RES_MEMORY into KVA upon activation so that rman_get_virtual() works as expected.
2002-03-24 01:51:29 +00:00
if (type == SYS_RES_MEMORY) {
/*
- Ensure we find no unexpected partner. - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
2009-03-19 20:52:46 +00:00
* Need to memory-map the device space, as some drivers
* depend on the virtual address being set and usable.
Map the device memory belonging to resources of type SYS_RES_MEMORY into KVA upon activation so that rman_get_virtual() works as expected.
2002-03-24 01:51:29 +00:00
*/
error = sparc64_bus_mem_map(rman_get_bustag(r),
Don't confuse NULL with 0.
2003-12-26 14:04:19 +00:00
rman_get_bushandle(r), rman_get_size(r), 0, 0, &p);
Map the device memory belonging to resources of type SYS_RES_MEMORY into KVA upon activation so that rman_get_virtual() works as expected.
2002-03-24 01:51:29 +00:00
if (error != 0)
return (error);
rman_set_virtual(r, p);
}
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
return (rman_activate_resource(r));
}
static int
psycho_deactivate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
{
Add a workaround for quirky PCI devices that set the intpin register to 0, but use this mechanism to generate interrupts. Preserve the child device when setting up and tearing down interrupts. Some style nits.
2001-12-21 21:35:47 +00:00
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
if (type == SYS_RES_IRQ)
Some code cleanup: - Fix some comments; remove numerous superfluous or outdated ones. - Correctly pass on the requesting device when handing requests up to the parent bus. - Use the complete device name, including unit number, to build the IOMMU instance name. - Inline a function that was only used once, and was trivial.
2004-04-25 00:30:28 +00:00
return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child,
type, rid, r));
Map the device memory belonging to resources of type SYS_RES_MEMORY into KVA upon activation so that rman_get_virtual() works as expected.
2002-03-24 01:51:29 +00:00
if (type == SYS_RES_MEMORY) {
sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r));
rman_set_virtual(r, NULL);
}
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
return (rman_deactivate_resource(r));
}
static int
psycho_release_resource(device_t bus, device_t child, int type, int rid,
Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs). Use explicit bus space accesses instead of mapping the device memory into kva. Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
struct resource *r)
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
{
int error;
if (type == SYS_RES_IRQ)
Some code cleanup: - Fix some comments; remove numerous superfluous or outdated ones. - Correctly pass on the requesting device when handing requests up to the parent bus. - Use the complete device name, including unit number, to build the IOMMU instance name. - Inline a function that was only used once, and was trivial.
2004-04-25 00:30:28 +00:00
return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child,
type, rid, r));
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
if (rman_get_flags(r) & RF_ACTIVE) {
error = bus_deactivate_resource(child, type, rid, r);
if (error)
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
return (error);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
}
return (rman_release_resource(r));
}
Rototill the sparc64 nexus(4) (actually this brings in the code the sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
2007-03-07 21:13:51 +00:00
static bus_dma_tag_t
psycho_get_dma_tag(device_t bus, device_t child)
{
struct psycho_softc *sc;
sc = device_get_softc(bus);
return (sc->sc_pci_dmat);
}
Add the new sparc64 OFW PCI framework, conditional on options OFW_NEWPCI for now. It introduces a OFW PCI bus driver and a generic OFW PCI-PCI bridge driver. By utilizing these, the PCI handling is much more elegant now. The advantages of the new approach are: - Device enumeration should hopefully be more like on Solaris now, so unit numbers should match what's printed on the box more closely. - Real interrupt routing is implemented now, so cardbus bridges etc. have at least a chance to work. - The quirk tables are gone and have been replaced by (hopefully sufficient) heuristics. - Much cleaner code. There was also a report that previously bogus interrupt assignments are fixed now, which can be attributed to the new heuristics. A pitfall, and the reason why this is not the default yet, is that it changes device enumeration, as mentioned above, which can make it necessary to change the system configuration if more than one unit of a device type is present (on a system with two hme cars, for example, it is possible that hme0 becomes hme1 and vice versa after enabling the option). Systems with multiple disk controllers may need to be booted into single user (and require manual specification of the root file system on boot) to adjust the fstab. Nevertheless, I would like to encourage users to use this option, so that it can be made the default soon. In detail, the changes are: - Introduce an OFW PCI bus driver; it inherits most methods from the generic PCI bus driver, but uses the firmware for enumeration, performs additional initialization for devices and firmware-specific interrupt routing. It also implements an OFW-specific method to allow child devices to get their firmware nodes. - Introduce an OFW PCI-PCI bridge driver; again, it inherits most of the generic PCI-PCI bridge driver; it has it's own method for interrupt routing, as well as some sparc64-specific methods (one to get the node again, and one to adjust the bridge bus range, since we need to reenumerate all PCI buses). - Convert the apb driver to the new way of handling things. - Provide a common framework for OFW bridge drivers, used be the two drivers above. - Provide a small common framework for interrupt routing (for all bridge types). - Convert the psycho driver to the new framework; this gets rid of a bunch of old kludges in pci_read_config(), and the whole preinitialization (ofw_pci_init()). - Convert the ISA MD part and the EBus driver to the new way interrupts and nodes are handled. - Introduce types for firmware interrupt properties. - Rename the old sparcbus_if to ofw_pci_if by repo copy (it is only required for PCI), and move it to a more correct location (new support methodsx were also added, and an old one was deprecated). - Fix a bunch of minor bugs, perform some cleanups. In some cases, I introduced some minor code duplication to keep the new code clean, in hopes that the old code will be unifdef'ed soon. Reviewed in part by: imp Tested by: jake, Marius Strobl <marius@alchemy.franken.de>, Sergey Mokryshev <mokr@mokr.net>, Chris Jackman <cjackNOSPAM@klatsch.org> Info on u30 firmware provided by: kris
2003-07-01 14:52:47 +00:00
static phandle_t
psycho_get_node(device_t bus, device_t dev)
{
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
struct psycho_softc *sc;
Add the new sparc64 OFW PCI framework, conditional on options OFW_NEWPCI for now. It introduces a OFW PCI bus driver and a generic OFW PCI-PCI bridge driver. By utilizing these, the PCI handling is much more elegant now. The advantages of the new approach are: - Device enumeration should hopefully be more like on Solaris now, so unit numbers should match what's printed on the box more closely. - Real interrupt routing is implemented now, so cardbus bridges etc. have at least a chance to work. - The quirk tables are gone and have been replaced by (hopefully sufficient) heuristics. - Much cleaner code. There was also a report that previously bogus interrupt assignments are fixed now, which can be attributed to the new heuristics. A pitfall, and the reason why this is not the default yet, is that it changes device enumeration, as mentioned above, which can make it necessary to change the system configuration if more than one unit of a device type is present (on a system with two hme cars, for example, it is possible that hme0 becomes hme1 and vice versa after enabling the option). Systems with multiple disk controllers may need to be booted into single user (and require manual specification of the root file system on boot) to adjust the fstab. Nevertheless, I would like to encourage users to use this option, so that it can be made the default soon. In detail, the changes are: - Introduce an OFW PCI bus driver; it inherits most methods from the generic PCI bus driver, but uses the firmware for enumeration, performs additional initialization for devices and firmware-specific interrupt routing. It also implements an OFW-specific method to allow child devices to get their firmware nodes. - Introduce an OFW PCI-PCI bridge driver; again, it inherits most of the generic PCI-PCI bridge driver; it has it's own method for interrupt routing, as well as some sparc64-specific methods (one to get the node again, and one to adjust the bridge bus range, since we need to reenumerate all PCI buses). - Convert the apb driver to the new way of handling things. - Provide a common framework for OFW bridge drivers, used be the two drivers above. - Provide a small common framework for interrupt routing (for all bridge types). - Convert the psycho driver to the new framework; this gets rid of a bunch of old kludges in pci_read_config(), and the whole preinitialization (ofw_pci_init()). - Convert the ISA MD part and the EBus driver to the new way interrupts and nodes are handled. - Introduce types for firmware interrupt properties. - Rename the old sparcbus_if to ofw_pci_if by repo copy (it is only required for PCI), and move it to a more correct location (new support methodsx were also added, and an old one was deprecated). - Fix a bunch of minor bugs, perform some cleanups. In some cases, I introduced some minor code duplication to keep the new code clean, in hopes that the old code will be unifdef'ed soon. Reviewed in part by: imp Tested by: jake, Marius Strobl <marius@alchemy.franken.de>, Sergey Mokryshev <mokr@mokr.net>, Chris Jackman <cjackNOSPAM@klatsch.org> Info on u30 firmware provided by: kris
2003-07-01 14:52:47 +00:00
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
sc = device_get_softc(bus);
Add the new sparc64 OFW PCI framework, conditional on options OFW_NEWPCI for now. It introduces a OFW PCI bus driver and a generic OFW PCI-PCI bridge driver. By utilizing these, the PCI handling is much more elegant now. The advantages of the new approach are: - Device enumeration should hopefully be more like on Solaris now, so unit numbers should match what's printed on the box more closely. - Real interrupt routing is implemented now, so cardbus bridges etc. have at least a chance to work. - The quirk tables are gone and have been replaced by (hopefully sufficient) heuristics. - Much cleaner code. There was also a report that previously bogus interrupt assignments are fixed now, which can be attributed to the new heuristics. A pitfall, and the reason why this is not the default yet, is that it changes device enumeration, as mentioned above, which can make it necessary to change the system configuration if more than one unit of a device type is present (on a system with two hme cars, for example, it is possible that hme0 becomes hme1 and vice versa after enabling the option). Systems with multiple disk controllers may need to be booted into single user (and require manual specification of the root file system on boot) to adjust the fstab. Nevertheless, I would like to encourage users to use this option, so that it can be made the default soon. In detail, the changes are: - Introduce an OFW PCI bus driver; it inherits most methods from the generic PCI bus driver, but uses the firmware for enumeration, performs additional initialization for devices and firmware-specific interrupt routing. It also implements an OFW-specific method to allow child devices to get their firmware nodes. - Introduce an OFW PCI-PCI bridge driver; again, it inherits most of the generic PCI-PCI bridge driver; it has it's own method for interrupt routing, as well as some sparc64-specific methods (one to get the node again, and one to adjust the bridge bus range, since we need to reenumerate all PCI buses). - Convert the apb driver to the new way of handling things. - Provide a common framework for OFW bridge drivers, used be the two drivers above. - Provide a small common framework for interrupt routing (for all bridge types). - Convert the psycho driver to the new framework; this gets rid of a bunch of old kludges in pci_read_config(), and the whole preinitialization (ofw_pci_init()). - Convert the ISA MD part and the EBus driver to the new way interrupts and nodes are handled. - Introduce types for firmware interrupt properties. - Rename the old sparcbus_if to ofw_pci_if by repo copy (it is only required for PCI), and move it to a more correct location (new support methodsx were also added, and an old one was deprecated). - Fix a bunch of minor bugs, perform some cleanups. In some cases, I introduced some minor code duplication to keep the new code clean, in hopes that the old code will be unifdef'ed soon. Reviewed in part by: imp Tested by: jake, Marius Strobl <marius@alchemy.franken.de>, Sergey Mokryshev <mokr@mokr.net>, Chris Jackman <cjackNOSPAM@klatsch.org> Info on u30 firmware provided by: kris
2003-07-01 14:52:47 +00:00
/* We only have one child, the PCI bus, which needs our own node. */
return (sc->sc_node);
}
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
static bus_space_tag_t
psycho_alloc_bus_tag(struct psycho_softc *sc, int type)
{
bus_space_tag_t bt;
o Changes to psycho_attach(): [1] - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
2007-01-08 01:26:47 +00:00
bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF, M_NOWAIT | M_ZERO);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
if (bt == NULL)
Some clean-up, style changes and changes that will reduce differences between this driver and other Host-PCI bridge drivers based on this one: - Make the code fit into 80 columns. - Make the code adhere style(9) (don't use function calls in initializers, use uintXX_t instead of u_intXX_t, add missing prototypes, ...). - Remove unused and superfluous struct declaration, softc member, casts, includes, etc. - Use FBSDID. - Sprinkle const. - Try to make comments and messages consistent in style throughout the driver. - Use convenience macros for the number of interrupts and ranges of the bridge. - Use __func__ instead of hardcoded function names in panic strings and error messages. Some of the hardcoded function names actually were outdated through moving code around. [1] - Rename softc members related to the PCI side of the bridge to sc_pci_* in order to make it clear which side of the bridge they refer to (so stuff like sc_bushandle vs. sc_bh is less confusing while reading the code). PR: 76052 [1]
2005-11-22 21:34:26 +00:00
panic("%s: out of memory", __func__);
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
Prefix the members of struct bus_space_tag and struct bus_dma_tag with a uniqifier. No functional changes.
2003-01-06 19:43:10 +00:00
bt->bst_cookie = sc;
- Use the newly introduced pcib_mtx spin lock to lock psycho_ce(), allowing it to be a filter/"fast" handler. Locking the interrupt handlers with a spin lock is mainly a requirement in schizo(4) but as we ought to register the spin lock anyway it should not hurt to take advantage of it in psycho(4). - Pass both a driver_filter_t and a driver_intr_t argument to psycho_set_intr(), allowing to get rid of the FAST interrupt flag hack. - Don't register the over-temperature interrupt handler as filter/ "fast" handler so shutdown_nice() can acquire the process lock. - Use bus_{read,write}_8() instead of bus_space_{read,write}_8() in order to get rid of sc_bushandle and sc_bustag in the softc. - Correct the debug output for adjusting the subordinate bus number. - Remove the banal and outdated above psycho_filter_stub(). - Fix some white space nits.
2007-06-16 23:46:41 +00:00
bt->bst_parent = rman_get_bustag(sc->sc_mem_res);
Prefix the members of struct bus_space_tag and struct bus_dma_tag with a uniqifier. No functional changes.
2003-01-06 19:43:10 +00:00
bt->bst_type = type;
Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware PCI support code, and a driver for the Sun APB PCI-PCI bridge. Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00
return (bt);
}
Reference in New Issue Copy Permalink