2001-07-03 17:27:13 +00:00
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/*
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* Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp>
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* Copyright (c) 2001 Cameron Grant <cg@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define PCIR_NAMBAR 0x10
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#define PCIR_NABMBAR 0x14
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2002-08-19 16:03:56 +00:00
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#define PCIR_ICH_LEGACY 0x41
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#define ICH_LEGACY_ENABLE 0x01
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2001-07-03 17:27:13 +00:00
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/* Native Audio Bus Master Control Registers */
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#define ICH_REG_X_BDBAR 0x00
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#define ICH_REG_X_CIV 0x04
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#define ICH_REG_X_LVI 0x05
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#define ICH_REG_X_SR 0x06
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#define ICH_REG_X_PICB 0x08
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#define ICH_REG_X_PIV 0x0a
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#define ICH_REG_X_CR 0x0b
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#define ICH_REG_PI_BASE 0x00
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#define ICH_REG_PO_BASE 0x10
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#define ICH_REG_MC_BASE 0x20
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#define ICH_REG_GLOB_CNT 0x2c
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#define ICH_REG_GLOB_STA 0x30
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#define ICH_REG_ACC_SEMA 0x34
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/* Status Register Values */
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#define ICH_X_SR_DCH 0x0001
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#define ICH_X_SR_CELV 0x0002
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#define ICH_X_SR_LVBCI 0x0004
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#define ICH_X_SR_BCIS 0x0008
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#define ICH_X_SR_FIFOE 0x0010
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/* Control Register Values */
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#define ICH_X_CR_RPBM 0x01
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#define ICH_X_CR_RR 0x02
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#define ICH_X_CR_LVBIE 0x04
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#define ICH_X_CR_FEIE 0x08
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#define ICH_X_CR_IOCE 0x10
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/* Global Control Register Values */
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#define ICH_GLOB_CTL_GIE 0x00000001
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#define ICH_GLOB_CTL_COLD 0x00000002 /* negate */
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#define ICH_GLOB_CTL_WARM 0x00000004
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#define ICH_GLOB_CTL_SHUT 0x00000008
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#define ICH_GLOB_CTL_PRES 0x00000010
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#define ICH_GLOB_CTL_SRES 0x00000020
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/* Global Status Register Values */
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#define ICH_GLOB_STA_GSCI 0x00000001
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#define ICH_GLOB_STA_MIINT 0x00000002
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#define ICH_GLOB_STA_MOINT 0x00000004
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#define ICH_GLOB_STA_PIINT 0x00000020
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#define ICH_GLOB_STA_POINT 0x00000040
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#define ICH_GLOB_STA_MINT 0x00000080
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#define ICH_GLOB_STA_PCR 0x00000100
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#define ICH_GLOB_STA_SCR 0x00000200
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#define ICH_GLOB_STA_PRES 0x00000400
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#define ICH_GLOB_STA_SRES 0x00000800
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#define ICH_GLOB_STA_SLOT12 0x00007000
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#define ICH_GLOB_STA_RCODEC 0x00008000
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#define ICH_GLOB_STA_AD3 0x00010000
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#define ICH_GLOB_STA_MD3 0x00020000
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#define ICH_GLOB_STA_IMASK (ICH_GLOB_STA_MIINT | ICH_GLOB_STA_MOINT | ICH_GLOB_STA_PIINT | ICH_GLOB_STA_POINT | ICH_GLOB_STA_MINT | ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)
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/* play/record buffer */
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#define ICH_BDC_IOC 0x80000000
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#define ICH_BDC_BUP 0x40000000
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