2012-04-14 13:54:10 +00:00
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//=- llvm/CodeGen/DFAPacketizer.cpp - DFA Packetizer for VLIW -*- C++ -*-=====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This class implements a deterministic finite automaton (DFA) based
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// packetizing mechanism for VLIW architectures. It provides APIs to
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// determine whether there exists a legal mapping of instructions to
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// functional unit assignments in a packet. The DFA is auto-generated from
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// the target's Schedule.td file.
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//
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// A DFA consists of 3 major elements: states, inputs, and transitions. For
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// the packetizing mechanism, the input is the set of instruction classes for
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// a target. The state models all possible combinations of functional unit
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// consumption for a given set of instructions in a packet. A transition
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// models the addition of an instruction to a packet. In the DFA constructed
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// by this class, if an instruction can be added to a packet, then a valid
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// transition exists from the corresponding state. Invalid transitions
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// indicate that the instruction cannot be added to the current packet.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/DFAPacketizer.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBundle.h"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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2012-04-14 13:54:10 +00:00
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#include "llvm/MC/MCInstrItineraries.h"
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2013-04-08 18:41:23 +00:00
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#include "llvm/Target/TargetInstrInfo.h"
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2012-04-14 13:54:10 +00:00
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using namespace llvm;
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2015-12-30 11:46:15 +00:00
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// --------------------------------------------------------------------
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// Definitions shared between DFAPacketizer.cpp and DFAPacketizerEmitter.cpp
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namespace {
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DFAInput addDFAFuncUnits(DFAInput Inp, unsigned FuncUnits) {
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return (Inp << DFA_MAX_RESOURCES) | FuncUnits;
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}
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/// Return the DFAInput for an instruction class input vector.
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/// This function is used in both DFAPacketizer.cpp and in
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/// DFAPacketizerEmitter.cpp.
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DFAInput getDFAInsnInput(const std::vector<unsigned> &InsnClass) {
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DFAInput InsnInput = 0;
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assert ((InsnClass.size() <= DFA_MAX_RESTERMS) &&
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"Exceeded maximum number of DFA terms");
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for (auto U : InsnClass)
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InsnInput = addDFAFuncUnits(InsnInput, U);
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return InsnInput;
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}
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}
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// --------------------------------------------------------------------
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DFAPacketizer::DFAPacketizer(const InstrItineraryData *I,
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const DFAStateInput (*SIT)[2],
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2012-04-14 13:54:10 +00:00
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const unsigned *SET):
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InstrItins(I), CurrentState(0), DFAStateInputTable(SIT),
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DFAStateEntryTable(SET) {
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// Make sure DFA types are large enough for the number of terms & resources.
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assert((DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <= (8 * sizeof(DFAInput))
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&& "(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAInput");
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assert((DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <= (8 * sizeof(DFAStateInput))
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&& "(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAStateInput");
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}
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//
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// ReadTable - Read the DFA transition table and update CachedTable.
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//
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// Format of the transition tables:
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// DFAStateInputTable[][2] = pairs of <Input, Transition> for all valid
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// transitions
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// DFAStateEntryTable[i] = Index of the first entry in DFAStateInputTable
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// for the ith state
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//
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void DFAPacketizer::ReadTable(unsigned int state) {
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unsigned ThisState = DFAStateEntryTable[state];
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unsigned NextStateInTable = DFAStateEntryTable[state+1];
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// Early exit in case CachedTable has already contains this
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// state's transitions.
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if (CachedTable.count(UnsignPair(state,
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DFAStateInputTable[ThisState][0])))
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return;
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for (unsigned i = ThisState; i < NextStateInTable; i++)
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CachedTable[UnsignPair(state, DFAStateInputTable[i][0])] =
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DFAStateInputTable[i][1];
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}
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//
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// getInsnInput - Return the DFAInput for an instruction class.
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//
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DFAInput DFAPacketizer::getInsnInput(unsigned InsnClass) {
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// Note: this logic must match that in DFAPacketizerDefs.h for input vectors.
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DFAInput InsnInput = 0;
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unsigned i = 0;
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for (const InstrStage *IS = InstrItins->beginStage(InsnClass),
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*IE = InstrItins->endStage(InsnClass); IS != IE; ++IS, ++i) {
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InsnInput = addDFAFuncUnits(InsnInput, IS->getUnits());
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assert ((i < DFA_MAX_RESTERMS) && "Exceeded maximum number of DFA inputs");
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}
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return InsnInput;
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}
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// getInsnInput - Return the DFAInput for an instruction class input vector.
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DFAInput DFAPacketizer::getInsnInput(const std::vector<unsigned> &InsnClass) {
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return getDFAInsnInput(InsnClass);
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}
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2012-04-14 13:54:10 +00:00
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// canReserveResources - Check if the resources occupied by a MCInstrDesc
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// are available in the current state.
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bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc *MID) {
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unsigned InsnClass = MID->getSchedClass();
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DFAInput InsnInput = getInsnInput(InsnClass);
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UnsignPair StateTrans = UnsignPair(CurrentState, InsnInput);
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ReadTable(CurrentState);
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return (CachedTable.count(StateTrans) != 0);
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}
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// reserveResources - Reserve the resources occupied by a MCInstrDesc and
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// change the current state to reflect that change.
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void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) {
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unsigned InsnClass = MID->getSchedClass();
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DFAInput InsnInput = getInsnInput(InsnClass);
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UnsignPair StateTrans = UnsignPair(CurrentState, InsnInput);
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ReadTable(CurrentState);
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assert(CachedTable.count(StateTrans) != 0);
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CurrentState = CachedTable[StateTrans];
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}
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// canReserveResources - Check if the resources occupied by a machine
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// instruction are available in the current state.
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bool DFAPacketizer::canReserveResources(llvm::MachineInstr *MI) {
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const llvm::MCInstrDesc &MID = MI->getDesc();
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return canReserveResources(&MID);
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}
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// reserveResources - Reserve the resources occupied by a machine
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// instruction and change the current state to reflect that change.
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void DFAPacketizer::reserveResources(llvm::MachineInstr *MI) {
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const llvm::MCInstrDesc &MID = MI->getDesc();
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reserveResources(&MID);
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}
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2012-08-15 19:34:23 +00:00
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namespace llvm {
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// DefaultVLIWScheduler - This class extends ScheduleDAGInstrs and overrides
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// Schedule method to build the dependence graph.
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class DefaultVLIWScheduler : public ScheduleDAGInstrs {
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private:
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AliasAnalysis *AA;
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public:
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DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI,
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AliasAnalysis *AA);
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// Schedule - Actual scheduling work.
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void schedule() override;
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};
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2015-07-05 14:21:36 +00:00
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}
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2015-01-18 16:17:27 +00:00
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DefaultVLIWScheduler::DefaultVLIWScheduler(MachineFunction &MF,
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MachineLoopInfo &MLI,
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AliasAnalysis *AA)
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: ScheduleDAGInstrs(MF, &MLI), AA(AA) {
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CanHandleTerminators = true;
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}
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void DefaultVLIWScheduler::schedule() {
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// Build the scheduling graph.
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buildSchedGraph(AA);
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}
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// VLIWPacketizerList Ctor
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VLIWPacketizerList::VLIWPacketizerList(MachineFunction &MF,
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MachineLoopInfo &MLI, AliasAnalysis *AA)
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: MF(MF), AA(AA) {
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TII = MF.getSubtarget().getInstrInfo();
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ResourceTracker = TII->CreateTargetScheduleState(MF.getSubtarget());
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VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, AA);
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}
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// VLIWPacketizerList Dtor
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VLIWPacketizerList::~VLIWPacketizerList() {
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2012-08-15 19:34:23 +00:00
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if (VLIWScheduler)
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delete VLIWScheduler;
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2012-04-14 13:54:10 +00:00
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2012-08-15 19:34:23 +00:00
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if (ResourceTracker)
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delete ResourceTracker;
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2012-04-14 13:54:10 +00:00
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}
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// endPacket - End the current packet, bundle packet instructions and reset
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// DFA state.
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void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB,
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MachineInstr *MI) {
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2012-04-14 13:54:10 +00:00
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if (CurrentPacketMIs.size() > 1) {
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MachineInstr *MIFirst = CurrentPacketMIs.front();
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finalizeBundle(*MBB, MIFirst->getIterator(), MI->getIterator());
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}
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CurrentPacketMIs.clear();
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ResourceTracker->clearResources();
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}
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// PacketizeMIs - Bundle machine instructions into packets.
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void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator BeginItr,
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MachineBasicBlock::iterator EndItr) {
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assert(VLIWScheduler && "VLIW Scheduler is not initialized!");
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VLIWScheduler->startBlock(MBB);
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2013-12-22 00:04:03 +00:00
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VLIWScheduler->enterRegion(MBB, BeginItr, EndItr,
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std::distance(BeginItr, EndItr));
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VLIWScheduler->schedule();
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// Generate MI -> SU map.
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MIToSUnit.clear();
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for (unsigned i = 0, e = VLIWScheduler->SUnits.size(); i != e; ++i) {
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SUnit *SU = &VLIWScheduler->SUnits[i];
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MIToSUnit[SU->getInstr()] = SU;
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}
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// The main packetizer loop.
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for (; BeginItr != EndItr; ++BeginItr) {
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MachineInstr *MI = BeginItr;
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this->initPacketizerState();
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// End the current packet if needed.
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if (this->isSoloInstruction(MI)) {
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endPacket(MBB, MI);
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continue;
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}
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2012-08-15 19:34:23 +00:00
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// Ignore pseudo instructions.
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if (this->ignorePseudoInstruction(MI, MBB))
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continue;
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SUnit *SUI = MIToSUnit[MI];
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assert(SUI && "Missing SUnit Info!");
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// Ask DFA if machine resource is available for MI.
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bool ResourceAvail = ResourceTracker->canReserveResources(MI);
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if (ResourceAvail && shouldAddToPacket(MI)) {
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2012-04-14 13:54:10 +00:00
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// Dependency check for MI with instructions in CurrentPacketMIs.
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for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
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VE = CurrentPacketMIs.end(); VI != VE; ++VI) {
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MachineInstr *MJ = *VI;
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SUnit *SUJ = MIToSUnit[MJ];
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assert(SUJ && "Missing SUnit Info!");
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// Is it legal to packetize SUI and SUJ together.
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if (!this->isLegalToPacketizeTogether(SUI, SUJ)) {
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// Allow packetization if dependency can be pruned.
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if (!this->isLegalToPruneDependencies(SUI, SUJ)) {
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2012-04-14 13:54:10 +00:00
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// End the packet if dependency cannot be pruned.
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endPacket(MBB, MI);
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break;
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} // !isLegalToPruneDependencies.
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} // !isLegalToPacketizeTogether.
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} // For all instructions in CurrentPacketMIs.
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} else {
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// End the packet if resource is not available, or if the instruction
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// shoud not be added to the current packet.
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2012-04-14 13:54:10 +00:00
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endPacket(MBB, MI);
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}
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// Add MI to the current packet.
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BeginItr = this->addToPacket(MI);
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} // For all instructions in BB.
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// End any packet left behind.
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endPacket(MBB, EndItr);
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2012-08-15 19:34:23 +00:00
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VLIWScheduler->exitRegion();
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VLIWScheduler->finishBlock();
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}
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