310 lines
7.7 KiB
C
310 lines
7.7 KiB
C
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/*-
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* Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com>
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* Copyright (c) 2012-2015 Robert N. M. Watson
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* Copyright (c) 2013 SRI International
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/smp.h>
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#include <machine/hwfunc.h>
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#include <machine/smp.h>
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#include <mips/beri/beri_mp.h>
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#include <dev/fdt/fdt_common.h>
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struct spin_entry {
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uint64_t entry_addr;
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uint64_t a0;
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uint32_t rsvd1;
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uint32_t pir;
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uint64_t rsvd2;
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};
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static phandle_t cpu_of_nodes[MAXCPU];
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static device_t picmap[MAXCPU];
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int
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platform_processor_id(void)
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{
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int cpu;
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cpu = beri_get_cpu();
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return (cpu);
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}
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void
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platform_cpu_mask(cpuset_t *mask)
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{
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int ncores, ncpus, nthreads;
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phandle_t cpus, cpu;
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pcell_t reg;
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char prop[16];
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struct spin_entry *se;
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ncores = beri_get_ncores();
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nthreads = beri_get_nthreads();
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KASSERT(ncores <= 0x10000, ("%s: too many cores %d", __func__, ncores));
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KASSERT(nthreads <= 0x10000, ("%s: too many threads %d", __func__,
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nthreads));
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KASSERT(ncores < 0xffff || nthreads < 0xffff,
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("%s: cores x thread (%d x %d) would overflow", __func__, ncores,
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nthreads));
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ncpus = ncores * nthreads;
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if (MAXCPU > 1 && ncpus > MAXCPU)
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printf("%s: Hardware supports more CPUs (%d) than kernel (%d)\n",
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__func__, ncpus, MAXCPU);
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printf("%s: hardware has %d cores with %d threads each\n", __func__,
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ncores, nthreads);
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if ((cpus = OF_finddevice("/cpus")) <= 0) {
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printf("%s: no \"/cpus\" device found in FDT\n", __func__);
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goto error;
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}
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if ((cpu = OF_child(cpus)) <= 0) {
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printf("%s: no children of \"/cpus\" found in FDT\n", __func__);
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goto error;
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}
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CPU_ZERO(mask);
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do {
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if (OF_getprop(cpu, "reg", ®, sizeof(reg)) <= 0) {
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printf("%s: cpu device with no reg property\n",
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__func__);
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goto error;
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}
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if (reg > MAXCPU) {
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printf("%s: cpu ID too large (%d > %d)\n", __func__,
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reg, MAXCPU);
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continue;
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}
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cpu_of_nodes[reg] = cpu;
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if (reg != 0) {
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if (OF_getprop(cpu, "enable-method", &prop,
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sizeof(prop)) <= 0 && OF_getprop(OF_parent(cpu),
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"enable-method", &prop, sizeof(prop)) <= 0) {
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printf("%s: CPU %d has no enable-method "
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"property\n", __func__, reg);
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continue;
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}
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if (strcmp("spin-table", prop) != 0) {
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printf("%s: CPU %d enable-method is '%s' not "
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"'spin-table'\n", __func__, reg, prop);
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continue;
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}
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if (OF_getprop(cpu, "cpu-release-addr", &se,
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sizeof(se)) <= 0) {
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printf("%s: CPU %d has missing or invalid "
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"cpu-release-addr\n", __func__, reg);
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continue;
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}
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if (se->entry_addr != 1) {
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printf("%s: CPU %d has uninitalized spin "
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"entry\n", __func__, reg);
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continue;
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}
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}
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CPU_SET(reg, mask);
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} while ((cpu = OF_peer(cpu)) > 0);
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return;
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error:
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/*
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* If we run into any problems determining the CPU layout,
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* fall back to UP.
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*
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* XXX: panic instead?
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*/
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CPU_ZERO(mask);
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CPU_SET(0, mask);
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}
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void
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platform_init_secondary(int cpuid)
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{
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device_t ic;
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int ipi;
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ipi = platform_ipi_hardintr_num();
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ic = devclass_get_device(devclass_find("beripic"), cpuid);
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picmap[cpuid] = ic;
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beripic_setup_ipi(ic, cpuid, ipi);
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/* Unmask the interrupt */
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if (cpuid != 0) {
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mips_wr_status(mips_rd_status() | (((1 << ipi) << 8) << 2));
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}
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}
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void
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platform_ipi_send(int cpuid)
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{
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mips_sync(); /* Ordering, liveness. */
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beripic_send_ipi(picmap[cpuid], cpuid);
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}
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void
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platform_ipi_clear(void)
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{
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int cpuid;
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cpuid = platform_processor_id();
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beripic_clear_ipi(picmap[cpuid], cpuid);
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}
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/*
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* XXXBED: Set via FDT?
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*/
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int
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platform_ipi_hardintr_num(void)
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{
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return (4);
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}
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int
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platform_ipi_softintr_num(void)
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{
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return (-1);
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}
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/*
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* XXXBED: Fine for MT, will need something better for multi-core.
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*/
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struct cpu_group *
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platform_smp_topo(void)
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{
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return (smp_topo_none());
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}
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void
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platform_init_ap(int cpuid)
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{
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uint32_t status;
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u_int clock_int_mask;
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KASSERT(cpuid < MAXCPU, ("%s: invalid CPU id %d", __func__, cpuid));
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/* Make sure coprocessors are enabled. */
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status = mips_rd_status();
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status |= (MIPS_SR_COP_0_BIT | MIPS_SR_COP_1_BIT);
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#if defined(CPU_CHERI)
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status |= MIPS_SR_COP_2_BIT;
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#endif
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mips_wr_status(status);
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#if 0
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register_t hwrena;
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/* Enable HDWRD instruction in userspace. Also enables statcounters. */
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hwrena = mips_rd_hwrena();
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hwrena |= (MIPS_HWRENA_CC | MIPS_HWRENA_CCRES | MIPS_HWRENA_CPUNUM |
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MIPS_HWRENA_BERI_STATCOUNTERS_MASK);
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mips_wr_hwrena(hwrena);
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#endif
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/*
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* Enable per-thread timer.
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*/
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clock_int_mask = hard_int_mask(5);
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set_intr_mask(clock_int_mask);
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}
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/*
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* BERI startup conforms to the spin-table start method defined in the
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* ePAPR 1.0 spec. The initial spin waiting for an address is started
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* by the CPU firmware.
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*/
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int
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platform_start_ap(int cpuid)
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{
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phandle_t cpu;
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char prop[16];
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struct spin_entry *se;
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KASSERT(cpuid != 0, ("%s: can't start CPU 0!\n", __func__));
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KASSERT((cpuid > 0 && cpuid < MAXCPU),
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("%s: invalid CPU id %d", __func__, cpuid));
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cpu = cpu_of_nodes[cpuid];
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if (OF_getprop(cpu, "status", &prop, sizeof(prop)) <= 0) {
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if (bootverbose)
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printf("%s: CPU %d has no status property, "
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"trying parent\n", __func__, cpuid);
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if (OF_getprop(OF_parent(cpu), "status", &prop,
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sizeof(prop)) <= 0)
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panic("%s: CPU %d has no status property", __func__,
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cpuid);
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}
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if (strcmp("disabled", prop) != 0)
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panic("%s: CPU %d status is '%s' not 'disabled'",
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__func__, cpuid, prop);
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if (OF_getprop(cpu, "enable-method", &prop, sizeof(prop)) <= 0) {
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if (bootverbose)
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printf("%s: CPU %d has no enable-method, "
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"trying parent\n", __func__, cpuid);
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if (OF_getprop(OF_parent(cpu), "enable-method", &prop,
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sizeof(prop)) <= 0)
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panic("%s: CPU %d has no enable-method property",
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__func__, cpuid);
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}
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if (strcmp("spin-table", prop) != 0)
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panic("%s: CPU %d enable-method is '%s' not "
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"'spin-table'", __func__, cpuid, prop);
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if (OF_getprop(cpu, "cpu-release-addr", &se, sizeof(se)) <= 0)
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panic("%s: CPU %d has missing or invalid cpu-release-addr",
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__func__, cpuid);
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se->pir = cpuid;
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if (bootverbose)
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printf("%s: writing %p to %p\n", __func__, mpentry,
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&se->entry_addr);
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mips_sync(); /* Ordering. */
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se->entry_addr = (intptr_t)mpentry;
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mips_sync(); /* Liveness. */
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return (0);
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}
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