292 lines
9.0 KiB
C
292 lines
9.0 KiB
C
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/******************************************************************************
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Copyright (c) 2001-2010, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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/*$FreeBSD$*/
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#ifndef _E1000_VF_H_
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#define _E1000_VF_H_
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#include "e1000_osdep.h"
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#include "e1000_regs.h"
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#include "e1000_defines.h"
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struct e1000_hw;
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#define E1000_DEV_ID_82576_VF 0x10CA
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#define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
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/* Additional Descriptor Control definitions */
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#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
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#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
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/* SRRCTL bit definitions */
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#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
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#define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00
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#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
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#define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000
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#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
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#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
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#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
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#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000
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#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
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#define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000
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#define E1000_SRRCTL_DROP_EN 0x80000000
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#define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F
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#define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00
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/* Interrupt Defines */
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#define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
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#define E1000_EITR(_n) (0x01680 + ((_n) << 2))
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#define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */
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#define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
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#define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
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#define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
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#define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
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#define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */
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#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
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#define E1000_IVAR_VALID 0x80
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/* Receive Descriptor - Advanced */
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union e1000_adv_rx_desc {
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struct {
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u64 pkt_addr; /* Packet buffer address */
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u64 hdr_addr; /* Header buffer address */
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} read;
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struct {
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struct {
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union {
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u32 data;
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struct {
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u16 pkt_info; /* RSS type, Packet type */
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u16 hdr_info; /* Split Header,
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* header buffer length */
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} hs_rss;
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} lo_dword;
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union {
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u32 rss; /* RSS Hash */
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struct {
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u16 ip_id; /* IP id */
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u16 csum; /* Packet Checksum */
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} csum_ip;
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} hi_dword;
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} lower;
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struct {
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u32 status_error; /* ext status/error */
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u16 length; /* Packet length */
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u16 vlan; /* VLAN tag */
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} upper;
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} wb; /* writeback */
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};
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#define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
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#define E1000_RXDADV_HDRBUFLEN_SHIFT 5
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/* Transmit Descriptor - Advanced */
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union e1000_adv_tx_desc {
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struct {
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u64 buffer_addr; /* Address of descriptor's data buf */
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u32 cmd_type_len;
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u32 olinfo_status;
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} read;
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struct {
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u64 rsvd; /* Reserved */
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u32 nxtseq_seed;
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u32 status;
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} wb;
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};
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/* Adv Transmit Descriptor Config Masks */
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#define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
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#define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
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#define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
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#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
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#define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
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#define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
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#define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
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#define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
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#define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
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/* Context descriptors */
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struct e1000_adv_tx_context_desc {
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u32 vlan_macip_lens;
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u32 seqnum_seed;
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u32 type_tucmd_mlhl;
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u32 mss_l4len_idx;
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};
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#define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
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#define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
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#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
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#define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
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#define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
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enum e1000_mac_type {
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e1000_undefined = 0,
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e1000_vfadapt,
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e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */
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};
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struct e1000_vf_stats {
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u64 base_gprc;
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u64 base_gptc;
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u64 base_gorc;
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u64 base_gotc;
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u64 base_mprc;
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u64 base_gotlbc;
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u64 base_gptlbc;
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u64 base_gorlbc;
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u64 base_gprlbc;
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u32 last_gprc;
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u32 last_gptc;
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u32 last_gorc;
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u32 last_gotc;
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u32 last_mprc;
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u32 last_gotlbc;
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u32 last_gptlbc;
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u32 last_gorlbc;
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u32 last_gprlbc;
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u64 gprc;
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u64 gptc;
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u64 gorc;
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u64 gotc;
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u64 mprc;
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u64 gotlbc;
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u64 gptlbc;
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u64 gorlbc;
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u64 gprlbc;
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};
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#include "e1000_mbx.h"
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struct e1000_mac_operations {
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/* Function pointers for the MAC. */
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s32 (*init_params)(struct e1000_hw *);
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s32 (*check_for_link)(struct e1000_hw *);
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void (*clear_vfta)(struct e1000_hw *);
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s32 (*get_bus_info)(struct e1000_hw *);
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s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
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void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
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s32 (*reset_hw)(struct e1000_hw *);
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s32 (*init_hw)(struct e1000_hw *);
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s32 (*setup_link)(struct e1000_hw *);
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void (*write_vfta)(struct e1000_hw *, u32, u32);
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void (*rar_set)(struct e1000_hw *, u8*, u32);
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s32 (*read_mac_addr)(struct e1000_hw *);
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};
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struct e1000_mac_info {
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struct e1000_mac_operations ops;
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u8 addr[6];
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u8 perm_addr[6];
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enum e1000_mac_type type;
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u16 mta_reg_count;
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u16 rar_entry_count;
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bool get_link_status;
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};
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struct e1000_mbx_operations {
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s32 (*init_params)(struct e1000_hw *hw);
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s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
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s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
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s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
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s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
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s32 (*check_for_msg)(struct e1000_hw *, u16);
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s32 (*check_for_ack)(struct e1000_hw *, u16);
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s32 (*check_for_rst)(struct e1000_hw *, u16);
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};
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struct e1000_mbx_stats {
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u32 msgs_tx;
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u32 msgs_rx;
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u32 acks;
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u32 reqs;
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u32 rsts;
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};
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struct e1000_mbx_info {
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struct e1000_mbx_operations ops;
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struct e1000_mbx_stats stats;
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u32 timeout;
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u32 usec_delay;
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u16 size;
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};
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struct e1000_dev_spec_vf {
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u32 vf_number;
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u32 v2p_mailbox;
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};
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struct e1000_hw {
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void *back;
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u8 *hw_addr;
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u8 *flash_address;
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unsigned long io_base;
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struct e1000_mac_info mac;
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struct e1000_mbx_info mbx;
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union {
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struct e1000_dev_spec_vf vf;
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} dev_spec;
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u16 device_id;
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u16 subsystem_vendor_id;
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u16 subsystem_device_id;
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u16 vendor_id;
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u8 revision_id;
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};
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enum e1000_promisc_type {
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e1000_promisc_disabled = 0, /* all promisc modes disabled */
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e1000_promisc_unicast = 1, /* unicast promiscuous enabled */
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e1000_promisc_multicast = 2, /* multicast promiscuous enabled */
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e1000_promisc_enabled = 3, /* both uni and multicast promisc */
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e1000_num_promisc_types
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};
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/* These functions must be implemented by drivers */
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s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
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void e1000_vfta_set_vf(struct e1000_hw *, u16, bool);
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void e1000_rlpml_set_vf(struct e1000_hw *, u16);
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s32 e1000_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type);
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#endif /* _E1000_VF_H_ */
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