117 lines
3.5 KiB
C
117 lines
3.5 KiB
C
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/*-
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* Copyright (c) 2014 M. Warner Losh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef ARM_AT91_AT91_SMC_H
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#define ARM_AT91_AT91_SMC_H
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/* Registers */
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#define SMC_SETUP 0x00
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#define SMC_PULSE 0x04
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#define SMC_CYCLE 0x08
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#define SMC_MODE 0x0C
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#define SMC_CS_OFF(cs) (0x10 * (cs))
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/* Setup */
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#define SMC_SETUP_NCS_RD_SETUP(x) ((x) << 24)
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#define SMC_SETUP_NRD_SETUP(x) ((x) << 16)
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#define SMC_SETUP_NCS_WR_SETUP(x) ((x) << 8)
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#define SMC_SETUP_NWE_SETUP(x) (x)
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/* Pulse */
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#define SMC_PULSE_NCS_RD_PULSE(x) ((x) << 24)
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#define SMC_PULSE_NRD_PULSE(x) ((x) << 16)
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#define SMC_PULSE_NCS_WR_PULSE(x) ((x) << 8)
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#define SMC_PULSE_NWE_PULSE(x) (x)
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/* Cycle */
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#define SMC_CYCLE_NRD_CYCLE(x) ((x) << 16)
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#define SMC_CYCLE_NWE_CYCLE(x) (x)
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/* Mode */
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#define SMC_MODE_READ (1 << 0)
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#define SMC_MODE_WRITE (1 << 1)
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#define SMC_MODE_EXNW_DISABLED (0 << 4)
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#define SMC_MODE_EXNW_FROZEN_MODE (2 << 4)
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#define SMC_MODE_EXNW_READY_MODE (3 << 4)
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#define SMC_MODE_BAT (1 << 8)
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#define SMC_MODE_DBW_8BIT (0 << 12)
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#define SMC_MODE_DBW_16BIT (1 << 12)
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#define SMC_MODE_DBW_32_BIT (2 << 12)
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#define SMC_MODE_TDF_CYCLES(x) ((x) << 16)
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#define SMC_MODE_TDF_MODE (1 << 20)
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#define SMC_MODE_PMEN (1 << 24)
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#define SMC_PS_4BYTE (0 << 28)
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#define SMC_PS_8BYTE (1 << 28)
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#define SMC_PS_16BYTE (2 << 28)
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#define SMC_PS_32BYTE (3 << 28)
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/*
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* structure to ease init. See the SMC chapter in the datasheet for
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* the appropriate SoC you are using for details.
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*/
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struct at91_smc_init
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{
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/* Setup register */
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uint8_t ncs_rd_setup;
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uint8_t nrd_setup;
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uint8_t ncs_wr_setup;
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uint8_t nwe_setup;
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/* Pulse register */
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uint8_t ncs_rd_pulse;
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uint8_t nrd_pulse;
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uint8_t ncs_wr_pulse;
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uint8_t nwe_pulse;
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/* Cycle register */
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uint16_t nrd_cycle;
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uint16_t nwe_cycle;
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/* Mode register */
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uint8_t mode; /* Combo of READ/WRITE/EXNW fields */
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uint8_t bat;
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uint8_t dwb;
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uint8_t tdf_cycles;
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uint8_t tdf_mode;
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uint8_t pmen;
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uint8_t ps;
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};
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/*
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* Convenience routine to fill in SMC registers for a given chip select.
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*/
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void at91_smc_setup(int id, int cs, const struct at91_smc_init *smc);
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/*
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* Disable/Enable different External Bus Interfaces (EBI)
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*/
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void at91_ebi_enable(int cs);
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void at91_ebi_disable(int cs);
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#endif /* ARM_AT91_AT91_SMC_H */
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