632 lines
18 KiB
C
632 lines
18 KiB
C
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND 4-Clause-BSD
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*
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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* Copyright (C) 1995, 1996 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
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*/
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/*-
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* Copyright (C) 2001 Benno Rice.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Native 64-bit page table operations for running without a hypervisor.
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*/
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/ktr.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/proc.h>
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#include <sys/sched.h>
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#include <sys/sysctl.h>
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#include <sys/systm.h>
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#include <sys/rwlock.h>
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#include <sys/endian.h>
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#include <sys/kdb.h>
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#include <vm/vm.h>
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#include <vm/vm_param.h>
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#include <vm/vm_kern.h>
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#include <vm/vm_page.h>
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#include <vm/vm_map.h>
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#include <vm/vm_object.h>
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#include <vm/vm_extern.h>
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#include <vm/vm_pageout.h>
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#include <machine/cpu.h>
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#include <machine/hid.h>
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#include <machine/md_var.h>
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#include <machine/mmuvar.h>
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#include "mmu_oea64.h"
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#include "mmu_if.h"
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#include "moea64_if.h"
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#define PTESYNC() __asm __volatile("ptesync");
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#define TLBSYNC() __asm __volatile("tlbsync; ptesync");
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#define SYNC() __asm __volatile("sync");
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#define EIEIO() __asm __volatile("eieio");
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#define VSID_HASH_MASK 0x0000007fffffffffULL
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/* POWER9 only permits a 64k partition table size. */
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#define PART_SIZE 0x10000
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static __inline void
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TLBIE(uint64_t vpn)
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{
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vpn <<= ADDR_PIDX_SHFT;
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__asm __volatile("tlbie %0" :: "r"(vpn) : "memory");
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__asm __volatile("eieio; tlbsync; ptesync" ::: "memory");
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}
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#define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR)
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#define ENABLE_TRANS(msr) mtmsr(msr)
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/*
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* PTEG data.
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*/
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static volatile struct pate *isa3_part_table;
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static volatile struct lpte *isa3_hashtb_pteg_table;
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static struct rwlock isa3_hashtb_eviction_lock;
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/*
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* PTE calls.
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*/
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static int isa3_hashtb_pte_insert(mmu_t, struct pvo_entry *);
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static int64_t isa3_hashtb_pte_synch(mmu_t, struct pvo_entry *);
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static int64_t isa3_hashtb_pte_clear(mmu_t, struct pvo_entry *, uint64_t);
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static int64_t isa3_hashtb_pte_replace(mmu_t, struct pvo_entry *, int);
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static int64_t isa3_hashtb_pte_unset(mmu_t mmu, struct pvo_entry *);
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/*
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* Utility routines.
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*/
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static void isa3_hashtb_bootstrap(mmu_t mmup,
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vm_offset_t kernelstart, vm_offset_t kernelend);
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static void isa3_hashtb_cpu_bootstrap(mmu_t, int ap);
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static void tlbia(void);
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static mmu_method_t isa3_hashtb_methods[] = {
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/* Internal interfaces */
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MMUMETHOD(mmu_bootstrap, isa3_hashtb_bootstrap),
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MMUMETHOD(mmu_cpu_bootstrap, isa3_hashtb_cpu_bootstrap),
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MMUMETHOD(moea64_pte_synch, isa3_hashtb_pte_synch),
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MMUMETHOD(moea64_pte_clear, isa3_hashtb_pte_clear),
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MMUMETHOD(moea64_pte_unset, isa3_hashtb_pte_unset),
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MMUMETHOD(moea64_pte_replace, isa3_hashtb_pte_replace),
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MMUMETHOD(moea64_pte_insert, isa3_hashtb_pte_insert),
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{ 0, 0 }
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};
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MMU_DEF_INHERIT(isa3_mmu_native, MMU_TYPE_P9H, isa3_hashtb_methods,
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0, oea64_mmu);
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static int64_t
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isa3_hashtb_pte_synch(mmu_t mmu, struct pvo_entry *pvo)
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{
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volatile struct lpte *pt = isa3_hashtb_pteg_table + pvo->pvo_pte.slot;
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struct lpte properpt;
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uint64_t ptelo;
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PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
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moea64_pte_from_pvo(pvo, &properpt);
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rw_rlock(&isa3_hashtb_eviction_lock);
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if ((be64toh(pt->pte_hi) & LPTE_AVPN_MASK) !=
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(properpt.pte_hi & LPTE_AVPN_MASK)) {
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/* Evicted */
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rw_runlock(&isa3_hashtb_eviction_lock);
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return (-1);
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}
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PTESYNC();
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ptelo = be64toh(pt->pte_lo);
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rw_runlock(&isa3_hashtb_eviction_lock);
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return (ptelo & (LPTE_REF | LPTE_CHG));
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}
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static int64_t
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isa3_hashtb_pte_clear(mmu_t mmu, struct pvo_entry *pvo, uint64_t ptebit)
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{
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volatile struct lpte *pt = isa3_hashtb_pteg_table + pvo->pvo_pte.slot;
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struct lpte properpt;
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uint64_t ptelo;
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PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
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moea64_pte_from_pvo(pvo, &properpt);
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rw_rlock(&isa3_hashtb_eviction_lock);
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if ((be64toh(pt->pte_hi) & LPTE_AVPN_MASK) !=
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(properpt.pte_hi & LPTE_AVPN_MASK)) {
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/* Evicted */
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rw_runlock(&isa3_hashtb_eviction_lock);
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return (-1);
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}
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if (ptebit == LPTE_REF) {
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/* See "Resetting the Reference Bit" in arch manual */
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PTESYNC();
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/* 2-step here safe: precision is not guaranteed */
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ptelo = be64toh(pt->pte_lo);
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/* One-byte store to avoid touching the C bit */
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((volatile uint8_t *)(&pt->pte_lo))[6] =
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#if BYTE_ORDER == BIG_ENDIAN
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((uint8_t *)(&properpt.pte_lo))[6];
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#else
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((uint8_t *)(&properpt.pte_lo))[1];
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#endif
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rw_runlock(&isa3_hashtb_eviction_lock);
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critical_enter();
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TLBIE(pvo->pvo_vpn);
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critical_exit();
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} else {
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rw_runlock(&isa3_hashtb_eviction_lock);
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ptelo = isa3_hashtb_pte_unset(mmu, pvo);
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isa3_hashtb_pte_insert(mmu, pvo);
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}
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return (ptelo & (LPTE_REF | LPTE_CHG));
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}
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static int64_t
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isa3_hashtb_pte_unset(mmu_t mmu, struct pvo_entry *pvo)
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{
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volatile struct lpte *pt = isa3_hashtb_pteg_table + pvo->pvo_pte.slot;
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struct lpte properpt;
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uint64_t ptelo;
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moea64_pte_from_pvo(pvo, &properpt);
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rw_rlock(&isa3_hashtb_eviction_lock);
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if ((be64toh(pt->pte_hi & LPTE_AVPN_MASK)) !=
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(properpt.pte_hi & LPTE_AVPN_MASK)) {
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/* Evicted */
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moea64_pte_overflow--;
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rw_runlock(&isa3_hashtb_eviction_lock);
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return (-1);
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}
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/*
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* Invalidate the pte, briefly locking it to collect RC bits. No
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* atomics needed since this is protected against eviction by the lock.
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*/
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isync();
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critical_enter();
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pt->pte_hi = be64toh((pt->pte_hi & ~LPTE_VALID) | LPTE_LOCKED);
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PTESYNC();
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TLBIE(pvo->pvo_vpn);
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ptelo = be64toh(pt->pte_lo);
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*((volatile int32_t *)(&pt->pte_hi) + 1) = 0; /* Release lock */
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critical_exit();
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rw_runlock(&isa3_hashtb_eviction_lock);
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/* Keep statistics */
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moea64_pte_valid--;
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return (ptelo & (LPTE_CHG | LPTE_REF));
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}
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static int64_t
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isa3_hashtb_pte_replace(mmu_t mmu, struct pvo_entry *pvo, int flags)
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{
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volatile struct lpte *pt = isa3_hashtb_pteg_table + pvo->pvo_pte.slot;
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struct lpte properpt;
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int64_t ptelo;
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if (flags == 0) {
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/* Just some software bits changing. */
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moea64_pte_from_pvo(pvo, &properpt);
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rw_rlock(&isa3_hashtb_eviction_lock);
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if ((be64toh(pt->pte_hi) & LPTE_AVPN_MASK) !=
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(properpt.pte_hi & LPTE_AVPN_MASK)) {
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rw_runlock(&isa3_hashtb_eviction_lock);
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return (-1);
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}
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pt->pte_hi = htobe64(properpt.pte_hi);
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ptelo = be64toh(pt->pte_lo);
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rw_runlock(&isa3_hashtb_eviction_lock);
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} else {
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/* Otherwise, need reinsertion and deletion */
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ptelo = isa3_hashtb_pte_unset(mmu, pvo);
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isa3_hashtb_pte_insert(mmu, pvo);
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}
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return (ptelo);
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}
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static void
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isa3_hashtb_cpu_bootstrap(mmu_t mmup, int ap)
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{
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int i = 0;
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struct slb *slb = PCPU_GET(aim.slb);
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register_t seg0;
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/*
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* Initialize segment registers and MMU
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*/
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||
|
|
|
||
|
|
mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR);
|
||
|
|
|
||
|
|
switch (mfpvr() >> 16) {
|
||
|
|
case IBMPOWER9:
|
||
|
|
mtspr(SPR_HID0, mfspr(SPR_HID0) & ~HID0_RADIX);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Install kernel SLB entries
|
||
|
|
*/
|
||
|
|
|
||
|
|
__asm __volatile ("slbia");
|
||
|
|
__asm __volatile ("slbmfee %0,%1; slbie %0;" : "=r"(seg0) :
|
||
|
|
"r"(0));
|
||
|
|
|
||
|
|
for (i = 0; i < n_slbs; i++) {
|
||
|
|
if (!(slb[i].slbe & SLBE_VALID))
|
||
|
|
continue;
|
||
|
|
|
||
|
|
__asm __volatile ("slbmte %0, %1" ::
|
||
|
|
"r"(slb[i].slbv), "r"(slb[i].slbe));
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Install page table
|
||
|
|
*/
|
||
|
|
|
||
|
|
mtspr(SPR_PTCR,
|
||
|
|
((uintptr_t)isa3_part_table & ~DMAP_BASE_ADDRESS) |
|
||
|
|
flsl((PART_SIZE >> 12) - 1));
|
||
|
|
tlbia();
|
||
|
|
}
|
||
|
|
|
||
|
|
static void
|
||
|
|
isa3_hashtb_bootstrap(mmu_t mmup, vm_offset_t kernelstart,
|
||
|
|
vm_offset_t kernelend)
|
||
|
|
{
|
||
|
|
vm_size_t size;
|
||
|
|
vm_offset_t off;
|
||
|
|
vm_paddr_t pa;
|
||
|
|
register_t msr;
|
||
|
|
|
||
|
|
moea64_early_bootstrap(mmup, kernelstart, kernelend);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Allocate PTEG table.
|
||
|
|
*/
|
||
|
|
|
||
|
|
size = moea64_pteg_count * sizeof(struct lpteg);
|
||
|
|
CTR2(KTR_PMAP, "moea64_bootstrap: %d PTEGs, %lu bytes",
|
||
|
|
moea64_pteg_count, size);
|
||
|
|
rw_init(&isa3_hashtb_eviction_lock, "pte eviction");
|
||
|
|
|
||
|
|
/*
|
||
|
|
* We now need to allocate memory. This memory, to be allocated,
|
||
|
|
* has to reside in a page table. The page table we are about to
|
||
|
|
* allocate. We don't have BAT. So drop to data real mode for a minute
|
||
|
|
* as a measure of last resort. We do this a couple times.
|
||
|
|
*/
|
||
|
|
|
||
|
|
isa3_part_table =
|
||
|
|
(struct pate *)moea64_bootstrap_alloc(PART_SIZE, PART_SIZE);
|
||
|
|
if (hw_direct_map)
|
||
|
|
isa3_part_table = (struct pate *)PHYS_TO_DMAP(
|
||
|
|
(vm_offset_t)isa3_part_table);
|
||
|
|
/*
|
||
|
|
* PTEG table must be aligned on a 256k boundary, but can be placed
|
||
|
|
* anywhere with that alignment on POWER ISA 3+ systems.
|
||
|
|
*/
|
||
|
|
isa3_hashtb_pteg_table = (struct lpte *)moea64_bootstrap_alloc(size,
|
||
|
|
MAX(256*1024, size));
|
||
|
|
if (hw_direct_map)
|
||
|
|
isa3_hashtb_pteg_table =
|
||
|
|
(struct lpte *)PHYS_TO_DMAP((vm_offset_t)isa3_hashtb_pteg_table);
|
||
|
|
DISABLE_TRANS(msr);
|
||
|
|
bzero(__DEVOLATILE(void *, isa3_part_table), PART_SIZE);
|
||
|
|
isa3_part_table[0].pagetab =
|
||
|
|
((uintptr_t)isa3_hashtb_pteg_table & ~DMAP_BASE_ADDRESS) |
|
||
|
|
(uintptr_t)(flsl((moea64_pteg_count - 1) >> 11));
|
||
|
|
bzero(__DEVOLATILE(void *, isa3_hashtb_pteg_table), moea64_pteg_count *
|
||
|
|
sizeof(struct lpteg));
|
||
|
|
ENABLE_TRANS(msr);
|
||
|
|
|
||
|
|
CTR1(KTR_PMAP, "moea64_bootstrap: PTEG table at %p", isa3_hashtb_pteg_table);
|
||
|
|
|
||
|
|
moea64_mid_bootstrap(mmup, kernelstart, kernelend);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Add a mapping for the page table itself if there is no direct map.
|
||
|
|
*/
|
||
|
|
if (!hw_direct_map) {
|
||
|
|
size = moea64_pteg_count * sizeof(struct lpteg);
|
||
|
|
off = (vm_offset_t)(isa3_hashtb_pteg_table);
|
||
|
|
DISABLE_TRANS(msr);
|
||
|
|
for (pa = off; pa < off + size; pa += PAGE_SIZE)
|
||
|
|
pmap_kenter(pa, pa);
|
||
|
|
ENABLE_TRANS(msr);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Bring up virtual memory */
|
||
|
|
moea64_late_bootstrap(mmup, kernelstart, kernelend);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void
|
||
|
|
tlbia(void)
|
||
|
|
{
|
||
|
|
vm_offset_t i;
|
||
|
|
|
||
|
|
i = 0xc00; /* IS = 11 */
|
||
|
|
|
||
|
|
TLBSYNC();
|
||
|
|
|
||
|
|
for (; i < 0x200000; i += 0x00001000) {
|
||
|
|
__asm __volatile("tlbiel %0" :: "r"(i));
|
||
|
|
}
|
||
|
|
|
||
|
|
EIEIO();
|
||
|
|
TLBSYNC();
|
||
|
|
}
|
||
|
|
|
||
|
|
static int
|
||
|
|
atomic_pte_lock(volatile struct lpte *pte, uint64_t bitmask, uint64_t *oldhi)
|
||
|
|
{
|
||
|
|
int ret;
|
||
|
|
uint32_t oldhihalf;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Note: in principle, if just the locked bit were set here, we
|
||
|
|
* could avoid needing the eviction lock. However, eviction occurs
|
||
|
|
* so rarely that it isn't worth bothering about in practice.
|
||
|
|
*/
|
||
|
|
|
||
|
|
__asm __volatile (
|
||
|
|
"1:\tlwarx %1, 0, %3\n\t" /* load old value */
|
||
|
|
"and. %0,%1,%4\n\t" /* check if any bits set */
|
||
|
|
"bne 2f\n\t" /* exit if any set */
|
||
|
|
"stwcx. %5, 0, %3\n\t" /* attempt to store */
|
||
|
|
"bne- 1b\n\t" /* spin if failed */
|
||
|
|
"li %0, 1\n\t" /* success - retval = 1 */
|
||
|
|
"b 3f\n\t" /* we've succeeded */
|
||
|
|
"2:\n\t"
|
||
|
|
"stwcx. %1, 0, %3\n\t" /* clear reservation (74xx) */
|
||
|
|
"li %0, 0\n\t" /* failure - retval = 0 */
|
||
|
|
"3:\n\t"
|
||
|
|
: "=&r" (ret), "=&r"(oldhihalf), "=m" (pte->pte_hi)
|
||
|
|
: "r" ((volatile char *)&pte->pte_hi + 4),
|
||
|
|
"r" ((uint32_t)bitmask), "r" ((uint32_t)LPTE_LOCKED),
|
||
|
|
"m" (pte->pte_hi)
|
||
|
|
: "cr0", "cr1", "cr2", "memory");
|
||
|
|
|
||
|
|
*oldhi = (pte->pte_hi & 0xffffffff00000000ULL) | oldhihalf;
|
||
|
|
|
||
|
|
return (ret);
|
||
|
|
}
|
||
|
|
|
||
|
|
static uintptr_t
|
||
|
|
isa3_hashtb_insert_to_pteg(struct lpte *pvo_pt, uintptr_t slotbase,
|
||
|
|
uint64_t mask)
|
||
|
|
{
|
||
|
|
volatile struct lpte *pt;
|
||
|
|
uint64_t oldptehi, va;
|
||
|
|
uintptr_t k;
|
||
|
|
int i, j;
|
||
|
|
|
||
|
|
/* Start at a random slot */
|
||
|
|
i = mftb() % 8;
|
||
|
|
for (j = 0; j < 8; j++) {
|
||
|
|
k = slotbase + (i + j) % 8;
|
||
|
|
pt = &isa3_hashtb_pteg_table[k];
|
||
|
|
/* Invalidate and seize lock only if no bits in mask set */
|
||
|
|
if (atomic_pte_lock(pt, mask, &oldptehi)) /* Lock obtained */
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (j == 8)
|
||
|
|
return (-1);
|
||
|
|
|
||
|
|
if (oldptehi & LPTE_VALID) {
|
||
|
|
KASSERT(!(oldptehi & LPTE_WIRED), ("Unmapped wired entry"));
|
||
|
|
/*
|
||
|
|
* Need to invalidate old entry completely: see
|
||
|
|
* "Modifying a Page Table Entry". Need to reconstruct
|
||
|
|
* the virtual address for the outgoing entry to do that.
|
||
|
|
*/
|
||
|
|
if (oldptehi & LPTE_BIG)
|
||
|
|
va = oldptehi >> moea64_large_page_shift;
|
||
|
|
else
|
||
|
|
va = oldptehi >> ADDR_PIDX_SHFT;
|
||
|
|
if (oldptehi & LPTE_HID)
|
||
|
|
va = (((k >> 3) ^ moea64_pteg_mask) ^ va) &
|
||
|
|
VSID_HASH_MASK;
|
||
|
|
else
|
||
|
|
va = ((k >> 3) ^ va) & VSID_HASH_MASK;
|
||
|
|
va |= (oldptehi & LPTE_AVPN_MASK) <<
|
||
|
|
(ADDR_API_SHFT64 - ADDR_PIDX_SHFT);
|
||
|
|
PTESYNC();
|
||
|
|
TLBIE(va);
|
||
|
|
moea64_pte_valid--;
|
||
|
|
moea64_pte_overflow++;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Update the PTE as per "Adding a Page Table Entry". Lock is released
|
||
|
|
* by setting the high doubleworld.
|
||
|
|
*/
|
||
|
|
pt->pte_lo = htobe64(pvo_pt->pte_lo);
|
||
|
|
EIEIO();
|
||
|
|
pt->pte_hi = htobe64(pvo_pt->pte_hi);
|
||
|
|
PTESYNC();
|
||
|
|
|
||
|
|
/* Keep statistics */
|
||
|
|
moea64_pte_valid++;
|
||
|
|
|
||
|
|
return (k);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int
|
||
|
|
isa3_hashtb_pte_insert(mmu_t mmu, struct pvo_entry *pvo)
|
||
|
|
{
|
||
|
|
struct lpte insertpt;
|
||
|
|
uintptr_t slot;
|
||
|
|
|
||
|
|
/* Initialize PTE */
|
||
|
|
moea64_pte_from_pvo(pvo, &insertpt);
|
||
|
|
|
||
|
|
/* Make sure further insertion is locked out during evictions */
|
||
|
|
rw_rlock(&isa3_hashtb_eviction_lock);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* First try primary hash.
|
||
|
|
*/
|
||
|
|
pvo->pvo_pte.slot &= ~7ULL; /* Base slot address */
|
||
|
|
slot = isa3_hashtb_insert_to_pteg(&insertpt, pvo->pvo_pte.slot,
|
||
|
|
LPTE_VALID | LPTE_WIRED | LPTE_LOCKED);
|
||
|
|
if (slot != -1) {
|
||
|
|
rw_runlock(&isa3_hashtb_eviction_lock);
|
||
|
|
pvo->pvo_pte.slot = slot;
|
||
|
|
return (0);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Now try secondary hash.
|
||
|
|
*/
|
||
|
|
pvo->pvo_vaddr ^= PVO_HID;
|
||
|
|
insertpt.pte_hi ^= LPTE_HID;
|
||
|
|
pvo->pvo_pte.slot ^= (moea64_pteg_mask << 3);
|
||
|
|
slot = isa3_hashtb_insert_to_pteg(&insertpt, pvo->pvo_pte.slot,
|
||
|
|
LPTE_VALID | LPTE_WIRED | LPTE_LOCKED);
|
||
|
|
if (slot != -1) {
|
||
|
|
rw_runlock(&isa3_hashtb_eviction_lock);
|
||
|
|
pvo->pvo_pte.slot = slot;
|
||
|
|
return (0);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Out of luck. Find a PTE to sacrifice.
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Lock out all insertions for a bit */
|
||
|
|
if (!rw_try_upgrade(&isa3_hashtb_eviction_lock)) {
|
||
|
|
rw_runlock(&isa3_hashtb_eviction_lock);
|
||
|
|
rw_wlock(&isa3_hashtb_eviction_lock);
|
||
|
|
}
|
||
|
|
|
||
|
|
slot = isa3_hashtb_insert_to_pteg(&insertpt, pvo->pvo_pte.slot,
|
||
|
|
LPTE_WIRED | LPTE_LOCKED);
|
||
|
|
if (slot != -1) {
|
||
|
|
rw_wunlock(&isa3_hashtb_eviction_lock);
|
||
|
|
pvo->pvo_pte.slot = slot;
|
||
|
|
return (0);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Try other hash table. Now we're getting desperate... */
|
||
|
|
pvo->pvo_vaddr ^= PVO_HID;
|
||
|
|
insertpt.pte_hi ^= LPTE_HID;
|
||
|
|
pvo->pvo_pte.slot ^= (moea64_pteg_mask << 3);
|
||
|
|
slot = isa3_hashtb_insert_to_pteg(&insertpt, pvo->pvo_pte.slot,
|
||
|
|
LPTE_WIRED | LPTE_LOCKED);
|
||
|
|
if (slot != -1) {
|
||
|
|
rw_wunlock(&isa3_hashtb_eviction_lock);
|
||
|
|
pvo->pvo_pte.slot = slot;
|
||
|
|
return (0);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* No freeable slots in either PTEG? We're hosed. */
|
||
|
|
rw_wunlock(&isa3_hashtb_eviction_lock);
|
||
|
|
panic("moea64_pte_insert: overflow");
|
||
|
|
return (-1);
|
||
|
|
}
|
||
|
|
|