2000-05-01 09:05:19 +00:00
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/*-
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* Copyright (c) 1996, Javier Mart^mn Rueda (jmrueda@diatel.upm.es)
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* All rights reserved.
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*
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* Copyright (c) 2000 Matthew N. Dodd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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struct ex_softc {
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2005-06-10 16:49:24 +00:00
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struct ifnet *ifp;
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2000-05-01 09:05:19 +00:00
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struct ifmedia ifmedia;
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2005-06-10 16:49:24 +00:00
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u_char enaddr[6];
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2000-05-01 09:05:19 +00:00
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device_t dev;
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struct resource *ioport;
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int ioport_rid;
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struct resource *irq;
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int irq_rid;
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void * ih;
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u_short irq_no; /* IRQ number. */
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char * irq2ee; /* irq <-> internal */
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u_char * ee2irq; /* representation conversion */
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u_int mem_size; /* Total memory size, in bytes. */
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u_int rx_mem_size; /* Rx memory size (by default, */
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/* first 3/4 of total memory). */
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u_int rx_lower_limit; /* Lower and upper limits of */
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u_int rx_upper_limit; /* receive buffer. */
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u_int rx_head; /* Head of receive ring buffer. */
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u_int tx_mem_size; /* Tx memory size (by default, */
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/* last quarter of total memory).*/
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u_int tx_lower_limit; /* Lower and upper limits of */
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u_int tx_upper_limit; /* transmit buffer. */
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u_int tx_head; /* Head and tail of */
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u_int tx_tail; /* transmit ring buffer. */
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u_int tx_last; /* Pointer to beginning of last */
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/* frame in the chain. */
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2008-06-13 12:14:22 +00:00
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struct mtx lock;
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struct callout timer;
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int tx_timeout;
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2008-08-24 00:22:42 +00:00
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int flags;
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#define HAS_INT_NO_REG 1
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2000-05-01 09:05:19 +00:00
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};
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2003-03-29 15:38:53 +00:00
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extern devclass_t ex_devclass;
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2000-05-01 09:05:19 +00:00
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extern char irq2eemap[];
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extern u_char ee2irqmap[];
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extern char plus_irq2eemap[];
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extern u_char plus_ee2irqmap[];
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2004-06-27 13:10:20 +00:00
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int ex_alloc_resources(device_t);
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void ex_release_resources(device_t);
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int ex_attach(device_t);
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int ex_detach(device_t);
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2000-05-01 09:05:19 +00:00
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driver_intr_t ex_intr;
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2004-06-27 13:10:20 +00:00
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u_int16_t ex_eeprom_read(struct ex_softc *, int);
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void ex_get_address(struct ex_softc *, u_char *);
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int ex_card_type(u_char *);
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void ex_stop(struct ex_softc *);
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2008-06-13 12:14:22 +00:00
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#define CSR_READ_1(sc, off) (bus_read_1((sc)->ioport, off))
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#define CSR_READ_2(sc, off) (bus_read_2((sc)->ioport, off))
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2004-06-27 13:10:20 +00:00
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#define CSR_WRITE_1(sc, off, val) \
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2008-06-13 12:14:22 +00:00
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bus_write_1((sc)->ioport, off, val)
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2004-06-27 13:10:20 +00:00
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#define CSR_WRITE_2(sc, off, val) \
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2008-06-13 12:14:22 +00:00
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bus_write_2((sc)->ioport, off, val)
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2004-06-27 13:10:20 +00:00
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#define CSR_WRITE_MULTI_1(sc, off, addr, count) \
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2008-06-13 12:14:22 +00:00
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bus_write_multi_1((sc)->ioport, off, addr, count)
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2004-06-27 13:10:20 +00:00
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#define CSR_WRITE_MULTI_2(sc, off, addr, count) \
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2008-06-13 12:14:22 +00:00
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bus_write_multi_2((sc)->ioport, off, addr, count)
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2004-06-27 13:10:20 +00:00
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#define CSR_WRITE_MULTI_4(sc, off, addr, count) \
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2008-06-13 12:14:22 +00:00
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bus_write_multi_4((sc)->ioport, off, addr, count)
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2004-06-27 13:10:20 +00:00
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#define CSR_READ_MULTI_1(sc, off, addr, count) \
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2008-06-13 12:14:22 +00:00
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bus_read_multi_1((sc)->ioport, off, addr, count)
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2004-06-27 13:10:20 +00:00
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#define CSR_READ_MULTI_2(sc, off, addr, count) \
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2008-06-13 12:14:22 +00:00
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bus_read_multi_2((sc)->ioport, off, addr, count)
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2004-06-27 13:10:20 +00:00
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#define CSR_READ_MULTI_4(sc, off, addr, count) \
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2008-06-13 12:14:22 +00:00
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bus_read_multi_4((sc)->ioport, off, addr, count)
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#define EX_LOCK(sc) mtx_lock(&(sc)->lock)
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#define EX_UNLOCK(sc) mtx_unlock(&(sc)->lock)
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#define EX_ASSERT_LOCKED(sc) mtx_assert(&(sc)->lock, MA_OWNED)
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