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freebsd-dev/sys/mips/cavium/uart_cpu_octeonusart.c

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Import Cavium's FreeBSD port, or the Octeon specific pieces, verbatim. Yes, this puts things in the wrong place, doesn't compile and is woefully incomplete. However, it will allow us to more easily track against the upstream sources without needing to import the entire Cavium tree under vendor. This port is based on FreeBSD 7.0 as of April 2007 and the pre-import MIPS tree (aka mips2), so much work is necessary here.
2009-06-14 02:46:07 +00:00
/*-
sys/mips: further adoption of SPDX licensing ID tags. Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
2017-11-27 15:07:26 +00:00
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
Regularize my copyright notice o Remove All Rights Reserved from my notices o imp@FreeBSD.org everywhere o regularize punctiation, eliminate date ranges o Make sure that it's clear that I don't claim All Rights reserved by listing All Rights Reserved on same line as other copyright holders (but not me). Other such holders are also listed last where it's clear.
2019-12-04 16:56:11 +00:00
* Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org> All rights reserved.
Rewrite to try to be more sane: o Introduce a uart bus space so that we don't have to hack dev/uart to do 8 byte reads. This also handles the shift properly, so reset the shift we want dev/uart doing to 0. In effect, this bus space makes the octeon registers have an interface to dev/uart that looks just like the old ISA bus, but does the necessary 64-bit read/write to the bus. We only support read/write operations. We do all the widths, but likely could get away with only 64-bit and 8-bit given the restricted nature of use of this bus. o use bus_space_map to set the .bsh rather than a direct assignment. o Minor cleanup of uart_cpu_getdev to make it conform more to the other implementations. o Add some coments for future work. # with these changes, we now make it through cninit, but there's still some # problem that's preventing output, as well as another problem that causes # us to call panic just after we return from cninit() in platform_start.
2009-11-24 07:50:19 +00:00
* Copyright (c) 2009 M. Warner Losh <imp@FreeBSD.org>
Import Cavium's FreeBSD port, or the Octeon specific pieces, verbatim. Yes, this puts things in the wrong place, doesn't compile and is woefully incomplete. However, it will allow us to more easily track against the upstream sources without needing to import the entire Cavium tree under vendor. This port is based on FreeBSD 7.0 as of April 2007 and the pre-import MIPS tree (aka mips2), so much work is necessary here.
2009-06-14 02:46:07 +00:00
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id$
*/
#include "opt_uart.h"
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/cons.h>
#include <machine/bus.h>
#include <dev/uart/uart.h>
#include <dev/uart/uart_cpu.h>
Cope with the move and if_timer going way.
2010-01-11 04:29:26 +00:00
#include <mips/cavium/octeon_pcmap_regs.h>
Import Cavium's FreeBSD port, or the Octeon specific pieces, verbatim. Yes, this puts things in the wrong place, doesn't compile and is woefully incomplete. However, it will allow us to more easily track against the upstream sources without needing to import the entire Cavium tree under vendor. This port is based on FreeBSD 7.0 as of April 2007 and the pre-import MIPS tree (aka mips2), so much work is necessary here.
2009-06-14 02:46:07 +00:00
Update the port of FreeBSD to Cavium Octeon to use the Cavium Simple Executive library: o) Increase inline unit / large function growth limits for MIPS to accommodate the needs of the Simple Executive, which uses a shocking amount of inlining. o) Remove TARGET_OCTEON and use CPU_CNMIPS to do things required by cnMIPS and the Octeon SoC. o) Add OCTEON_VENDOR_LANNER to use Lanner's allocation of vendor-specific board numbers, specifically to support the MR320. o) Add OCTEON_BOARD_CAPK_0100ND to hard-wire configuration for the CAPK-0100nd, which improperly uses an evaluation board's board number and breaks board detection at runtime. This board is sold by Portwell as the CAM-0100. o) Add support for the RTC available on some Octeon boards. o) Add support for the Octeon PCI bus. Note that rman_[sg]et_virtual for IO ports can not work unless building for n64. o) Clean up the CompactFlash driver to use Simple Executive macros and structures where possible (it would be advisable to use the Simple Executive API to set the PIO mode, too, but that is not done presently.) Also use structures from FreeBSD's ATA layer rather than structures copied from Linux. o) Print available Octeon SoC features on boot. o) Add support for the Octeon timecounter. o) Use the Simple Executive's routines rather than local copies for doing reads and writes to 64-bit addresses and use its macros for various device addresses rather than using local copies. o) Rename octeon_board_real to octeon_is_simulation to reduce differences with Cavium-provided code originally written for Linux. Also make it use the same simplified test that the Simple Executive and Linux both use rather than our complex one. o) Add support for the Octeon CIU, which is the main interrupt unit, as a bus to use normal interrupt allocation and setup routines. o) Use the Simple Executive's bootmem facility to allocate physical memory for the kernel, rather than assuming we know which addresses we can steal. NB: This may reduce the amount of RAM the kernel reports you as having if you are leaving large temporary allocations made by U-Boot allocated when starting FreeBSD. o) Add a port of the Cavium-provided Ethernet driver for Linux. This changes Ethernet interface naming from rgmxN to octeN. The new driver has vast improvements over the old one, both in performance and functionality, but does still have some features which have not been ported entirely and there may be unimplemented code that can be hit in everyday use. I will make every effort to correct those as they are reported. o) Support loading the kernel on non-contiguous cores. o) Add very conservative support for harvesting randomness from the Octeon random number device. o) Turn SMP on by default. o) Clean up the style of the Octeon kernel configurations a little and make them compile with -march=octeon. o) Add support for the Lanner MR320 and the CAPK-0100nd to the Simple Executive. o) Modify the Simple Executive to build on FreeBSD and to build without executive-config.h or cvmx-config.h. In the future we may want to revert part of these changes and supply executive-config.h and cvmx-config.h and access to the options contained in those files via kernel configuration files. o) Modify the Simple Executive USB routines to support getting and setting of the USB PID.
2010-07-20 19:25:11 +00:00
#include <contrib/octeon-sdk/cvmx.h>
The UART device infrasturcture wants these defined. Define them just like we do in Malta. We may want to look at consolidating things because *ALL* mips will *ALWAYS* be memory mapped. The only wrinkle is that the tag may need to be a custom one (see endian issues with the Atheros port for one example).
2009-08-15 19:48:14 +00:00
bus_space_tag_t uart_bus_space_io;
bus_space_tag_t uart_bus_space_mem;
Rewrite to try to be more sane: o Introduce a uart bus space so that we don't have to hack dev/uart to do 8 byte reads. This also handles the shift properly, so reset the shift we want dev/uart doing to 0. In effect, this bus space makes the octeon registers have an interface to dev/uart that looks just like the old ISA bus, but does the necessary 64-bit read/write to the bus. We only support read/write operations. We do all the widths, but likely could get away with only 64-bit and 8-bit given the restricted nature of use of this bus. o use bus_space_map to set the .bsh rather than a direct assignment. o Minor cleanup of uart_cpu_getdev to make it conform more to the other implementations. o Add some coments for future work. # with these changes, we now make it through cninit, but there's still some # problem that's preventing output, as well as another problem that causes # us to call panic just after we return from cninit() in platform_start.
2009-11-24 07:50:19 +00:00
/*
* Specailized uart bus space. We present a 1 apart byte oriented
* bus to the outside world, but internally translate to/from the 8-apart
* 64-bit word bus that's on the octeon. We only support simple read/write
* in this space. Everything else is undefined.
*/
static uint8_t
ou_bs_r_1(void *t, bus_space_handle_t handle, bus_size_t offset)
{
Remove oct_read64 and oct_write64 and use their equivalents from the Simple Executive, which are used everywhere else in the Octeon port. While here, remove other unused things from octeon_pcmap_regs.h.
2012-10-30 06:29:17 +00:00
return (cvmx_read64_uint64(handle + offset));
Rewrite to try to be more sane: o Introduce a uart bus space so that we don't have to hack dev/uart to do 8 byte reads. This also handles the shift properly, so reset the shift we want dev/uart doing to 0. In effect, this bus space makes the octeon registers have an interface to dev/uart that looks just like the old ISA bus, but does the necessary 64-bit read/write to the bus. We only support read/write operations. We do all the widths, but likely could get away with only 64-bit and 8-bit given the restricted nature of use of this bus. o use bus_space_map to set the .bsh rather than a direct assignment. o Minor cleanup of uart_cpu_getdev to make it conform more to the other implementations. o Add some coments for future work. # with these changes, we now make it through cninit, but there's still some # problem that's preventing output, as well as another problem that causes # us to call panic just after we return from cninit() in platform_start.
2009-11-24 07:50:19 +00:00
}
static uint16_t
ou_bs_r_2(void *t, bus_space_handle_t handle, bus_size_t offset)
{
Remove oct_read64 and oct_write64 and use their equivalents from the Simple Executive, which are used everywhere else in the Octeon port. While here, remove other unused things from octeon_pcmap_regs.h.
2012-10-30 06:29:17 +00:00
return (cvmx_read64_uint64(handle + offset));
Rewrite to try to be more sane: o Introduce a uart bus space so that we don't have to hack dev/uart to do 8 byte reads. This also handles the shift properly, so reset the shift we want dev/uart doing to 0. In effect, this bus space makes the octeon registers have an interface to dev/uart that looks just like the old ISA bus, but does the necessary 64-bit read/write to the bus. We only support read/write operations. We do all the widths, but likely could get away with only 64-bit and 8-bit given the restricted nature of use of this bus. o use bus_space_map to set the .bsh rather than a direct assignment. o Minor cleanup of uart_cpu_getdev to make it conform more to the other implementations. o Add some coments for future work. # with these changes, we now make it through cninit, but there's still some # problem that's preventing output, as well as another problem that causes # us to call panic just after we return from cninit() in platform_start.
2009-11-24 07:50:19 +00:00
}
static uint32_t
ou_bs_r_4(void *t, bus_space_handle_t handle, bus_size_t offset)
{
Remove oct_read64 and oct_write64 and use their equivalents from the Simple Executive, which are used everywhere else in the Octeon port. While here, remove other unused things from octeon_pcmap_regs.h.
2012-10-30 06:29:17 +00:00
return (cvmx_read64_uint64(handle + offset));
Rewrite to try to be more sane: o Introduce a uart bus space so that we don't have to hack dev/uart to do 8 byte reads. This also handles the shift properly, so reset the shift we want dev/uart doing to 0. In effect, this bus space makes the octeon registers have an interface to dev/uart that looks just like the old ISA bus, but does the necessary 64-bit read/write to the bus. We only support read/write operations. We do all the widths, but likely could get away with only 64-bit and 8-bit given the restricted nature of use of this bus. o use bus_space_map to set the .bsh rather than a direct assignment. o Minor cleanup of uart_cpu_getdev to make it conform more to the other implementations. o Add some coments for future work. # with these changes, we now make it through cninit, but there's still some # problem that's preventing output, as well as another problem that causes # us to call panic just after we return from cninit() in platform_start.
2009-11-24 07:50:19 +00:00
}
static uint64_t
ou_bs_r_8(void *t, bus_space_handle_t handle, bus_size_t offset)
{
Remove oct_read64 and oct_write64 and use their equivalents from the Simple Executive, which are used everywhere else in the Octeon port. While here, remove other unused things from octeon_pcmap_regs.h.
2012-10-30 06:29:17 +00:00
return (cvmx_read64_uint64(handle + offset));
Rewrite to try to be more sane: o Introduce a uart bus space so that we don't have to hack dev/uart to do 8 byte reads. This also handles the shift properly, so reset the shift we want dev/uart doing to 0. In effect, this bus space makes the octeon registers have an interface to dev/uart that looks just like the old ISA bus, but does the necessary 64-bit read/write to the bus. We only support read/write operations. We do all the widths, but likely could get away with only 64-bit and 8-bit given the restricted nature of use of this bus. o use bus_space_map to set the .bsh rather than a direct assignment. o Minor cleanup of uart_cpu_getdev to make it conform more to the other implementations. o Add some coments for future work. # with these changes, we now make it through cninit, but there's still some # problem that's preventing output, as well as another problem that causes # us to call panic just after we return from cninit() in platform_start.
2009-11-24 07:50:19 +00:00
}
static void
ou_bs_w_1(void *t, bus_space_handle_t bsh, bus_size_t offset, uint8_t value)
{
Remove oct_read64 and oct_write64 and use their equivalents from the Simple Executive, which are used everywhere else in the Octeon port. While here, remove other unused things from octeon_pcmap_regs.h.
2012-10-30 06:29:17 +00:00
cvmx_write64_uint64(bsh + offset, value);
Rewrite to try to be more sane: o Introduce a uart bus space so that we don't have to hack dev/uart to do 8 byte reads. This also handles the shift properly, so reset the shift we want dev/uart doing to 0. In effect, this bus space makes the octeon registers have an interface to dev/uart that looks just like the old ISA bus, but does the necessary 64-bit read/write to the bus. We only support read/write operations. We do all the widths, but likely could get away with only 64-bit and 8-bit given the restricted nature of use of this bus. o use bus_space_map to set the .bsh rather than a direct assignment. o Minor cleanup of uart_cpu_getdev to make it conform more to the other implementations. o Add some coments for future work. # with these changes, we now make it through cninit, but there's still some # problem that's preventing output, as well as another problem that causes # us to call panic just after we return from cninit() in platform_start.
2009-11-24 07:50:19 +00:00
}
static void
ou_bs_w_2(void *t, bus_space_handle_t bsh, bus_size_t offset, uint16_t value)
{
Remove oct_read64 and oct_write64 and use their equivalents from the Simple Executive, which are used everywhere else in the Octeon port. While here, remove other unused things from octeon_pcmap_regs.h.
2012-10-30 06:29:17 +00:00
cvmx_write64_uint64(bsh + offset, value);
Rewrite to try to be more sane: o Introduce a uart bus space so that we don't have to hack dev/uart to do 8 byte reads. This also handles the shift properly, so reset the shift we want dev/uart doing to 0. In effect, this bus space makes the octeon registers have an interface to dev/uart that looks just like the old ISA bus, but does the necessary 64-bit read/write to the bus. We only support read/write operations. We do all the widths, but likely could get away with only 64-bit and 8-bit given the restricted nature of use of this bus. o use bus_space_map to set the .bsh rather than a direct assignment. o Minor cleanup of uart_cpu_getdev to make it conform more to the other implementations. o Add some coments for future work. # with these changes, we now make it through cninit, but there's still some # problem that's preventing output, as well as another problem that causes # us to call panic just after we return from cninit() in platform_start.
2009-11-24 07:50:19 +00:00
}
static void
ou_bs_w_4(void *t, bus_space_handle_t bsh, bus_size_t offset, uint32_t value)
{
Remove oct_read64 and oct_write64 and use their equivalents from the Simple Executive, which are used everywhere else in the Octeon port. While here, remove other unused things from octeon_pcmap_regs.h.
2012-10-30 06:29:17 +00:00
cvmx_write64_uint64(bsh + offset, value);
Rewrite to try to be more sane: o Introduce a uart bus space so that we don't have to hack dev/uart to do 8 byte reads. This also handles the shift properly, so reset the shift we want dev/uart doing to 0. In effect, this bus space makes the octeon registers have an interface to dev/uart that looks just like the old ISA bus, but does the necessary 64-bit read/write to the bus. We only support read/write operations. We do all the widths, but likely could get away with only 64-bit and 8-bit given the restricted nature of use of this bus. o use bus_space_map to set the .bsh rather than a direct assignment. o Minor cleanup of uart_cpu_getdev to make it conform more to the other implementations. o Add some coments for future work. # with these changes, we now make it through cninit, but there's still some # problem that's preventing output, as well as another problem that causes # us to call panic just after we return from cninit() in platform_start.
2009-11-24 07:50:19 +00:00
}
static void
ou_bs_w_8(void *t, bus_space_handle_t bsh, bus_size_t offset, uint64_t value)
{
Remove oct_read64 and oct_write64 and use their equivalents from the Simple Executive, which are used everywhere else in the Octeon port. While here, remove other unused things from octeon_pcmap_regs.h.
2012-10-30 06:29:17 +00:00
cvmx_write64_uint64(bsh + offset, value);
Rewrite to try to be more sane: o Introduce a uart bus space so that we don't have to hack dev/uart to do 8 byte reads. This also handles the shift properly, so reset the shift we want dev/uart doing to 0. In effect, this bus space makes the octeon registers have an interface to dev/uart that looks just like the old ISA bus, but does the necessary 64-bit read/write to the bus. We only support read/write operations. We do all the widths, but likely could get away with only 64-bit and 8-bit given the restricted nature of use of this bus. o use bus_space_map to set the .bsh rather than a direct assignment. o Minor cleanup of uart_cpu_getdev to make it conform more to the other implementations. o Add some coments for future work. # with these changes, we now make it through cninit, but there's still some # problem that's preventing output, as well as another problem that causes # us to call panic just after we return from cninit() in platform_start.
2009-11-24 07:50:19 +00:00
}
Export knowledge of the special bus space we use for the console to obio. Take advantage of the fact that obio only really supports uart at the moment to use the uart bus tag always for IOPORT allocations. # this needs to be redone to conform to FreeBSD standards and allow for # additional drivers for SoC hardware to attach
2010-01-25 19:27:20 +00:00
struct bus_space octeon_uart_tag = {
Rewrite to try to be more sane: o Introduce a uart bus space so that we don't have to hack dev/uart to do 8 byte reads. This also handles the shift properly, so reset the shift we want dev/uart doing to 0. In effect, this bus space makes the octeon registers have an interface to dev/uart that looks just like the old ISA bus, but does the necessary 64-bit read/write to the bus. We only support read/write operations. We do all the widths, but likely could get away with only 64-bit and 8-bit given the restricted nature of use of this bus. o use bus_space_map to set the .bsh rather than a direct assignment. o Minor cleanup of uart_cpu_getdev to make it conform more to the other implementations. o Add some coments for future work. # with these changes, we now make it through cninit, but there's still some # problem that's preventing output, as well as another problem that causes # us to call panic just after we return from cninit() in platform_start.
2009-11-24 07:50:19 +00:00
.bs_map = generic_bs_map,
.bs_unmap = generic_bs_unmap,
.bs_subregion = generic_bs_subregion,
.bs_barrier = generic_bs_barrier,
.bs_r_1 = ou_bs_r_1,
.bs_r_2 = ou_bs_r_2,
.bs_r_4 = ou_bs_r_4,
.bs_r_8 = ou_bs_r_8,
.bs_w_1 = ou_bs_w_1,
.bs_w_2 = ou_bs_w_2,
.bs_w_4 = ou_bs_w_4,
.bs_w_8 = ou_bs_w_8,
};
Minor formatting changes. Also, elimiante a couple of unused variables.
2009-06-14 07:01:22 +00:00
extern struct uart_class uart_oct16550_class;
Import Cavium's FreeBSD port, or the Octeon specific pieces, verbatim. Yes, this puts things in the wrong place, doesn't compile and is woefully incomplete. However, it will allow us to more easily track against the upstream sources without needing to import the entire Cavium tree under vendor. This port is based on FreeBSD 7.0 as of April 2007 and the pre-import MIPS tree (aka mips2), so much work is necessary here.
2009-06-14 02:46:07 +00:00
int
uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
{
Rewrite to try to be more sane: o Introduce a uart bus space so that we don't have to hack dev/uart to do 8 byte reads. This also handles the shift properly, so reset the shift we want dev/uart doing to 0. In effect, this bus space makes the octeon registers have an interface to dev/uart that looks just like the old ISA bus, but does the necessary 64-bit read/write to the bus. We only support read/write operations. We do all the widths, but likely could get away with only 64-bit and 8-bit given the restricted nature of use of this bus. o use bus_space_map to set the .bsh rather than a direct assignment. o Minor cleanup of uart_cpu_getdev to make it conform more to the other implementations. o Add some coments for future work. # with these changes, we now make it through cninit, but there's still some # problem that's preventing output, as well as another problem that causes # us to call panic just after we return from cninit() in platform_start.
2009-11-24 07:50:19 +00:00
Import Cavium's FreeBSD port, or the Octeon specific pieces, verbatim. Yes, this puts things in the wrong place, doesn't compile and is woefully incomplete. However, it will allow us to more easily track against the upstream sources without needing to import the entire Cavium tree under vendor. This port is based on FreeBSD 7.0 as of April 2007 and the pre-import MIPS tree (aka mips2), so much work is necessary here.
2009-06-14 02:46:07 +00:00
return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
}
int
uart_cpu_getdev(int devtype, struct uart_devinfo *di)
{
Rewrite to try to be more sane: o Introduce a uart bus space so that we don't have to hack dev/uart to do 8 byte reads. This also handles the shift properly, so reset the shift we want dev/uart doing to 0. In effect, this bus space makes the octeon registers have an interface to dev/uart that looks just like the old ISA bus, but does the necessary 64-bit read/write to the bus. We only support read/write operations. We do all the widths, but likely could get away with only 64-bit and 8-bit given the restricted nature of use of this bus. o use bus_space_map to set the .bsh rather than a direct assignment. o Minor cleanup of uart_cpu_getdev to make it conform more to the other implementations. o Add some coments for future work. # with these changes, we now make it through cninit, but there's still some # problem that's preventing output, as well as another problem that causes # us to call panic just after we return from cninit() in platform_start.
2009-11-24 07:50:19 +00:00
struct uart_class *class = &uart_oct16550_class;
Minor formatting changes. Also, elimiante a couple of unused variables.
2009-06-14 07:01:22 +00:00
Rewrite to try to be more sane: o Introduce a uart bus space so that we don't have to hack dev/uart to do 8 byte reads. This also handles the shift properly, so reset the shift we want dev/uart doing to 0. In effect, this bus space makes the octeon registers have an interface to dev/uart that looks just like the old ISA bus, but does the necessary 64-bit read/write to the bus. We only support read/write operations. We do all the widths, but likely could get away with only 64-bit and 8-bit given the restricted nature of use of this bus. o use bus_space_map to set the .bsh rather than a direct assignment. o Minor cleanup of uart_cpu_getdev to make it conform more to the other implementations. o Add some coments for future work. # with these changes, we now make it through cninit, but there's still some # problem that's preventing output, as well as another problem that causes # us to call panic just after we return from cninit() in platform_start.
2009-11-24 07:50:19 +00:00
/*
* These fields need to be setup corretly for uart_getenv to
* work in all cases.
*/
uart_bus_space_io = NULL; /* No io map for this device */
uart_bus_space_mem = &octeon_uart_tag;
di->bas.bst = uart_bus_space_mem;
/*
* If env specification for UART exists it takes precedence:
* hw.uart.console="mm:0xf1012000" or similar
*/
if (uart_getenv(devtype, di, class) == 0)
return (0);
/*
* Fallback to UART0 for console.
*/
Minor formatting changes. Also, elimiante a couple of unused variables.
2009-06-14 07:01:22 +00:00
di->ops = uart_getops(class);
di->bas.chan = 0;
Update the port of FreeBSD to Cavium Octeon to use the Cavium Simple Executive library: o) Increase inline unit / large function growth limits for MIPS to accommodate the needs of the Simple Executive, which uses a shocking amount of inlining. o) Remove TARGET_OCTEON and use CPU_CNMIPS to do things required by cnMIPS and the Octeon SoC. o) Add OCTEON_VENDOR_LANNER to use Lanner's allocation of vendor-specific board numbers, specifically to support the MR320. o) Add OCTEON_BOARD_CAPK_0100ND to hard-wire configuration for the CAPK-0100nd, which improperly uses an evaluation board's board number and breaks board detection at runtime. This board is sold by Portwell as the CAM-0100. o) Add support for the RTC available on some Octeon boards. o) Add support for the Octeon PCI bus. Note that rman_[sg]et_virtual for IO ports can not work unless building for n64. o) Clean up the CompactFlash driver to use Simple Executive macros and structures where possible (it would be advisable to use the Simple Executive API to set the PIO mode, too, but that is not done presently.) Also use structures from FreeBSD's ATA layer rather than structures copied from Linux. o) Print available Octeon SoC features on boot. o) Add support for the Octeon timecounter. o) Use the Simple Executive's routines rather than local copies for doing reads and writes to 64-bit addresses and use its macros for various device addresses rather than using local copies. o) Rename octeon_board_real to octeon_is_simulation to reduce differences with Cavium-provided code originally written for Linux. Also make it use the same simplified test that the Simple Executive and Linux both use rather than our complex one. o) Add support for the Octeon CIU, which is the main interrupt unit, as a bus to use normal interrupt allocation and setup routines. o) Use the Simple Executive's bootmem facility to allocate physical memory for the kernel, rather than assuming we know which addresses we can steal. NB: This may reduce the amount of RAM the kernel reports you as having if you are leaving large temporary allocations made by U-Boot allocated when starting FreeBSD. o) Add a port of the Cavium-provided Ethernet driver for Linux. This changes Ethernet interface naming from rgmxN to octeN. The new driver has vast improvements over the old one, both in performance and functionality, but does still have some features which have not been ported entirely and there may be unimplemented code that can be hit in everyday use. I will make every effort to correct those as they are reported. o) Support loading the kernel on non-contiguous cores. o) Add very conservative support for harvesting randomness from the Octeon random number device. o) Turn SMP on by default. o) Clean up the style of the Octeon kernel configurations a little and make them compile with -march=octeon. o) Add support for the Lanner MR320 and the CAPK-0100nd to the Simple Executive. o) Modify the Simple Executive to build on FreeBSD and to build without executive-config.h or cvmx-config.h. In the future we may want to revert part of these changes and supply executive-config.h and cvmx-config.h and access to the options contained in those files via kernel configuration files. o) Modify the Simple Executive USB routines to support getting and setting of the USB PID.
2010-07-20 19:25:11 +00:00
/* XXX */
Rather than shifting offsets by three, set register offset to 3. All our bus interface does that's special here now is to use a 64-bit register size. In theory, uart(4) ought to support a regsz as well as regshft and support 64-bit registers directly. Also use the UART class's range rather than a hand-coded 1024 for the address range.
2010-10-02 05:38:45 +00:00
if (bus_space_map(di->bas.bst, CVMX_MIO_UARTX_RBR(0),
uart_getrange(class), 0, &di->bas.bsh) != 0)
Rewrite to try to be more sane: o Introduce a uart bus space so that we don't have to hack dev/uart to do 8 byte reads. This also handles the shift properly, so reset the shift we want dev/uart doing to 0. In effect, this bus space makes the octeon registers have an interface to dev/uart that looks just like the old ISA bus, but does the necessary 64-bit read/write to the bus. We only support read/write operations. We do all the widths, but likely could get away with only 64-bit and 8-bit given the restricted nature of use of this bus. o use bus_space_map to set the .bsh rather than a direct assignment. o Minor cleanup of uart_cpu_getdev to make it conform more to the other implementations. o Add some coments for future work. # with these changes, we now make it through cninit, but there's still some # problem that's preventing output, as well as another problem that causes # us to call panic just after we return from cninit() in platform_start.
2009-11-24 07:50:19 +00:00
return (ENXIO);
Rather than shifting offsets by three, set register offset to 3. All our bus interface does that's special here now is to use a 64-bit register size. In theory, uart(4) ought to support a regsz as well as regshft and support 64-bit registers directly. Also use the UART class's range rather than a hand-coded 1024 for the address range.
2010-10-02 05:38:45 +00:00
di->bas.regshft = 3;
Import Cavium's FreeBSD port, or the Octeon specific pieces, verbatim. Yes, this puts things in the wrong place, doesn't compile and is woefully incomplete. However, it will allow us to more easily track against the upstream sources without needing to import the entire Cavium tree under vendor. This port is based on FreeBSD 7.0 as of April 2007 and the pre-import MIPS tree (aka mips2), so much work is necessary here.
2009-06-14 02:46:07 +00:00
di->bas.rclk = 0;
di->baudrate = 115200;
di->databits = 8;
di->stopbits = 1;
di->parity = UART_PARITY_NONE;
return (0);
}
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