2001-08-05 03:47:02 +00:00
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/*-
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* Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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2001-08-10 04:51:19 +00:00
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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2001-08-05 03:47:02 +00:00
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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2001-08-10 04:51:19 +00:00
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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2001-08-05 03:47:02 +00:00
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_FP_H_
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#define _MACHINE_FP_H_
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#define FPRS_DL (1 << 0)
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#define FPRS_DU (1 << 1)
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#define FPRS_FEF (1 << 2)
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#define FSR_CEXC_NX (1 << 0)
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#define FSR_CEXC_DZ (1 << 1)
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#define FSR_CEXC_UF (1 << 2)
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#define FSR_CEXC_OF (1 << 3)
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#define FSR_CEXC_NV (1 << 4)
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#define FSR_AEXC_NX (1 << 5)
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#define FSR_AEXC_DZ (1 << 6)
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#define FSR_AEXC_UF (1 << 7)
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#define FSR_AEXC_OF (1 << 8)
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#define FSR_AEXC_NV (1 << 9)
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#define FSR_QNE (1 << 13)
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#define FSR_NS (1 << 22)
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#define FSR_TEM_NX (1 << 23)
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#define FSR_TEM_DZ (1 << 24)
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#define FSR_TEM_UF (1 << 25)
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#define FSR_TEM_OF (1 << 26)
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#define FSR_TEM_NV (1 << 27)
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#define FSR_FCC0_SHIFT 10
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#define FSR_FCC0(x) (((x) >> FSR_FCC0_SHIFT) & 3)
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#define FSR_FTT_SHIFT 14
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#define FSR_FTT(x) (((x) >> FSR_FTT_SHIFT) & 7)
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#define FSR_VER_SHIFT 17
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#define FSR_VER(x) (((x) >> FSR_VER_SHIFT) & 7)
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#define FSR_RD_SHIFT 30
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#define FSR_RD(x) (((x) >> FSR_RD_SHIFT) & 3)
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#define FSR_FCC1_SHIFT 32
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#define FSR_FCC1(x) (((x) >> FSR_FCC1_SHIFT) & 3)
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#define FSR_FCC2_SHIFT 34
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#define FSR_FCC2(x) (((x) >> FSR_FCC2_SHIFT) & 3)
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#define FSR_FCC3_SHIFT 36
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#define FSR_FCC3(x) (((x) >> FSR_FCC3_SHIFT) & 3)
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/* A block of 8 double-precision (16 single-precision) FP registers. */
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struct fpblock {
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u_long fpq_l[8];
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};
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struct fpstate {
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struct fpblock fp_fb[4];
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u_long fp_fsr;
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u_long fp_fprs;
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};
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void fp_init_pcb(struct pcb *);
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int fp_enable_proc(struct proc *);
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/*
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* Note: The pointers passed to the next two functions must be aligned on
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* 64 byte boundaries.
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*/
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void savefpctx(struct fpstate *);
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void restorefpctx(struct fpstate *);
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#endif /* !_MACHINE_FP_H_ */
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