564 lines
11 KiB
INI
564 lines
11 KiB
INI
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/*********************************************************************
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*
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* Copyright 2003-2006 Raza Microelectronics, Inc. (RMI). All rights
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* reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Raza Microelectronics, Inc. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES, LOSS OF USE, DATA, OR PROFITS, OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* *****************************RMI_2**********************************/
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/*
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* This file defines the message ring configuration for XLS two core. It tries to allow
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* many different point-point communications between the message stations on the message ring
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* and as result is _not_ the best configuration for performance
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*
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* The message ring on phoenix family of processors connects the cpus, gmacs, xgmac/spi4,
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* security engine and the general purpose DMA engines. It provides a high bandwidth,
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* low latency communication links. On traditional processors, this communication goes through
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* which inherently does not scale very well with increasing number of cpus.
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*
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* Message ring has an in-built flow control mechanism. Every agent/station on the ring has to
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* have software configured credits to send messages to any agent. Every receiving agent on the
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* ring has a 256 entry FIFO that can divided into "buckets". All addressing on the ring is
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* in terms of buckets. There are a total 128 buckets on the ring. The total number of credits
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* across all sending agents should not exceed the bucket size.
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*
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* Below are the receiving agents and the max number of buckets they can have
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* CPU 0 : 8 buckets
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* CPU 1 : 8 buckets
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*
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* GMAC : 8 buckets
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*
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* SEC : 8 buckets
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*
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* DMA : 8 buckets
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*
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* CMP : Currently disabled.
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*
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* The bucket size of a bucket should be aligned to the bucket's starting index in that
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* receiving station's FIFO. For example, if sizes of bucket0 and bucket1 of a station
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* are 32 and 32, bucket2's size has to be 64. bucket size 0 is valid.
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*
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* The format of the file is pretty straight forward. Each bucket definition has the size
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* and the list of sending agents to that bucket with the number of credits to send.
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*
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* Undefined buckets have a size of 0 and Tx stations have 0 credits to send to that bucket.
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*
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* Following are the currently supported bucket names
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* cpu_0_0
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* cpu_0_1
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* cpu_0_2
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* cpu_0_3
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* cpu_0_4
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* cpu_0_5
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* cpu_0_6
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* cpu_0_7
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*
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* cpu_1_0
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* cpu_1_1
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* cpu_1_2
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* cpu_1_3
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* cpu_1_4
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* cpu_1_5
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* cpu_1_6
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* cpu_1_7
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*
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* enabled only for xls-b0
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* cpu_2_0
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* cpu_2_1
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* cpu_2_2
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* cpu_2_3
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* cpu_2_4
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* cpu_2_5
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* cpu_2_6
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* cpu_2_7
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*
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* enabled only for xls-b0
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* cpu_3_0
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* cpu_3_1
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* cpu_3_2
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* cpu_3_3
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* cpu_3_4
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* cpu_3_5
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* cpu_3_6
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* cpu_3_7
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*
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* gmac0_rfr
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* gmac0_tx_0
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* gmac0_tx_1
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* gmac0_tx_2
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* gmac0_tx_3
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*
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* gmac1_rfr
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* gmac1_tx_0
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* gmac1_tx_1
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* gmac1_tx_2
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* gmac1_tx_3
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*
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* sec_pipe_0
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* sec_rsa
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*
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* Following are the currently supported Tx Agent/Station names
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*
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* tx_stn_cpu_0
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* tx_stn_cpu_1
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*
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* tx_stn_gmac0
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* tx_stn_gmac1
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*
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* tx_stn_dma
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*
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* tx_stn_sec
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*
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*
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*/
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/*************************************************************/
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// CPU_0 Message Station
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bucket "cpu_0_0" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_sec" 6;
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"tx_stn_dma" 4;
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"tx_stn_cmp" 4;
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"tx_stn_cpu_0" 1;
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"tx_stn_cpu_1" 1; /* NEEDED BY RMIOS IPSEC */
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}
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bucket "cpu_0_1" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_sec" 8;
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"tx_stn_dma" 4;
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"tx_stn_cmp" 4;
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}
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bucket "cpu_0_2" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_sec" 8;
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"tx_stn_dma" 4;
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"tx_stn_cmp" 4;
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}
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bucket "cpu_0_3" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_sec" 8;
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"tx_stn_dma" 4;
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"tx_stn_cmp" 4;
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}
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bucket "cpu_0_4" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_dma" 4;
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"tx_stn_cmp" 4;
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}
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bucket "cpu_0_5" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_dma" 4;
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"tx_stn_cmp" 4;
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}
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bucket "cpu_0_6" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_dma" 4;
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"tx_stn_cmp" 4;
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}
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bucket "cpu_0_7" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_dma" 4;
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"tx_stn_cmp" 4;
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}
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/*************************************************************/
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// CPU_1 Message Station
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bucket "cpu_1_0" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_sec" 8;
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"tx_stn_dma" 4;
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"tx_stn_cmp" 4;
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}
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bucket "cpu_1_1" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_sec" 8;
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"tx_stn_dma" 4;
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"tx_stn_cmp" 4;
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}
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bucket "cpu_1_2" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_sec" 8;
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"tx_stn_dma" 4;
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"tx_stn_cmp" 4;
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}
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bucket "cpu_1_3" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_sec" 4;
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"tx_stn_cpu_0" 8; /* NEEDED BY RMIOS IPSEC */
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"tx_stn_dma" 2;
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"tx_stn_cmp" 2;
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}
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bucket "cpu_1_4" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_dma" 4;
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"tx_stn_cmp" 4;
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}
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bucket "cpu_1_5" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_dma" 4;
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"tx_stn_cmp" 4;
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}
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bucket "cpu_1_6" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_dma" 4;
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"tx_stn_cmp" 4;
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}
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bucket "cpu_1_7" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_dma" 4;
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"tx_stn_cmp" 4;
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}
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/*************************************************************/
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// CPU_2 Message Station
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bucket "cpu_2_0" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_sec" 8;
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"tx_stn_dma" 4;
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"tx_stn_cmp" 4;
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}
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bucket "cpu_2_1" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_sec" 8;
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"tx_stn_dma" 4;
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"tx_stn_cmp" 4;
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}
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bucket "cpu_2_2" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_sec" 8;
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"tx_stn_dma" 4;
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"tx_stn_cmp" 4;
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}
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bucket "cpu_2_3" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_sec" 4;
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"tx_stn_cpu_0" 8; /* NEEDED BY RMIOS IPSEC */
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"tx_stn_dma" 2;
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"tx_stn_cmp" 2;
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}
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bucket "cpu_2_4" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_dma" 4;
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"tx_stn_cmp" 4;
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}
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bucket "cpu_2_5" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_dma" 4;
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"tx_stn_cmp" 4;
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}
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bucket "cpu_2_6" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_dma" 4;
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"tx_stn_cmp" 4;
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}
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bucket "cpu_2_7" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_dma" 4;
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"tx_stn_cmp" 4;
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}
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/*************************************************************/
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// CPU_3 Message Station
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bucket "cpu_3_0" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_sec" 8;
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"tx_stn_dma" 4;
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"tx_stn_cmp" 4;
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}
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bucket "cpu_3_1" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_sec" 8;
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"tx_stn_dma" 4;
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"tx_stn_cmp" 4;
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}
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bucket "cpu_3_2" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_sec" 8;
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"tx_stn_dma" 4;
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"tx_stn_cmp" 4;
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}
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bucket "cpu_3_3" {
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size 32;
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"tx_stn_gmac0" 8;
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"tx_stn_gmac1" 8;
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"tx_stn_sec" 4;
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"tx_stn_cpu_0" 8; /* NEEDED BY RMIOS IPSEC */
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"tx_stn_dma" 2;
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"tx_stn_cmp" 2;
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}
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bucket "cpu_3_4" {
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size 32;
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|
|
"tx_stn_gmac0" 8;
|
||
|
|
"tx_stn_gmac1" 8;
|
||
|
|
"tx_stn_dma" 4;
|
||
|
|
"tx_stn_cmp" 4;
|
||
|
|
}
|
||
|
|
bucket "cpu_3_5" {
|
||
|
|
size 32;
|
||
|
|
"tx_stn_gmac0" 8;
|
||
|
|
"tx_stn_gmac1" 8;
|
||
|
|
"tx_stn_dma" 4;
|
||
|
|
"tx_stn_cmp" 4;
|
||
|
|
}
|
||
|
|
bucket "cpu_3_6" {
|
||
|
|
size 32;
|
||
|
|
"tx_stn_gmac0" 8;
|
||
|
|
"tx_stn_gmac1" 8;
|
||
|
|
"tx_stn_dma" 4;
|
||
|
|
"tx_stn_cmp" 4;
|
||
|
|
}
|
||
|
|
bucket "cpu_3_7" {
|
||
|
|
size 32;
|
||
|
|
"tx_stn_gmac0" 8;
|
||
|
|
"tx_stn_gmac1" 8;
|
||
|
|
"tx_stn_dma" 4;
|
||
|
|
"tx_stn_cmp" 4;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*************************************************************/
|
||
|
|
|
||
|
|
// GMAC Message Station
|
||
|
|
|
||
|
|
bucket "gmac0_rfr" {
|
||
|
|
size 32;
|
||
|
|
"tx_stn_cpu_0" 4;
|
||
|
|
"tx_stn_cpu_1" 4;
|
||
|
|
"tx_stn_cpu_2" 4;
|
||
|
|
"tx_stn_cpu_3" 4;
|
||
|
|
"tx_stn_gmac0" 8;
|
||
|
|
"tx_stn_gmac1" 8;
|
||
|
|
}
|
||
|
|
|
||
|
|
bucket "gmac0_tx_0" {
|
||
|
|
size 32;
|
||
|
|
"tx_stn_cpu_0" 8;
|
||
|
|
"tx_stn_cpu_1" 8;
|
||
|
|
"tx_stn_cpu_2" 8;
|
||
|
|
"tx_stn_cpu_3" 8;
|
||
|
|
}
|
||
|
|
|
||
|
|
bucket "gmac0_tx_1" {
|
||
|
|
size 32;
|
||
|
|
"tx_stn_cpu_0" 8;
|
||
|
|
"tx_stn_cpu_1" 8;
|
||
|
|
"tx_stn_cpu_2" 8;
|
||
|
|
"tx_stn_cpu_3" 8;
|
||
|
|
}
|
||
|
|
|
||
|
|
bucket "gmac0_tx_2" {
|
||
|
|
size 32;
|
||
|
|
"tx_stn_cpu_0" 8;
|
||
|
|
"tx_stn_cpu_1" 8;
|
||
|
|
"tx_stn_cpu_2" 8;
|
||
|
|
"tx_stn_cpu_3" 8;
|
||
|
|
}
|
||
|
|
|
||
|
|
bucket "gmac0_tx_3" {
|
||
|
|
size 32;
|
||
|
|
"tx_stn_cpu_0" 8;
|
||
|
|
"tx_stn_cpu_1" 8;
|
||
|
|
"tx_stn_cpu_2" 8;
|
||
|
|
"tx_stn_cpu_3" 8;
|
||
|
|
}
|
||
|
|
|
||
|
|
bucket "gmac1_rfr" {
|
||
|
|
size 32;
|
||
|
|
"tx_stn_cpu_0" 4;
|
||
|
|
"tx_stn_cpu_1" 4;
|
||
|
|
"tx_stn_cpu_2" 4;
|
||
|
|
"tx_stn_cpu_3" 4;
|
||
|
|
"tx_stn_gmac0" 8;
|
||
|
|
"tx_stn_gmac1" 8;
|
||
|
|
}
|
||
|
|
|
||
|
|
bucket "gmac1_tx_0" {
|
||
|
|
size 32;
|
||
|
|
"tx_stn_cpu_0" 8;
|
||
|
|
"tx_stn_cpu_1" 8;
|
||
|
|
"tx_stn_cpu_2" 8;
|
||
|
|
"tx_stn_cpu_3" 8;
|
||
|
|
}
|
||
|
|
|
||
|
|
bucket "gmac1_tx_1" {
|
||
|
|
size 32;
|
||
|
|
"tx_stn_cpu_0" 8;
|
||
|
|
"tx_stn_cpu_1" 8;
|
||
|
|
"tx_stn_cpu_2" 8;
|
||
|
|
"tx_stn_cpu_3" 8;
|
||
|
|
}
|
||
|
|
|
||
|
|
bucket "gmac1_tx_2" {
|
||
|
|
size 32;
|
||
|
|
"tx_stn_cpu_0" 8;
|
||
|
|
"tx_stn_cpu_1" 8;
|
||
|
|
"tx_stn_cpu_2" 8;
|
||
|
|
"tx_stn_cpu_3" 8;
|
||
|
|
}
|
||
|
|
|
||
|
|
bucket "gmac1_tx_3" {
|
||
|
|
size 32;
|
||
|
|
"tx_stn_cpu_0" 8;
|
||
|
|
"tx_stn_cpu_1" 8;
|
||
|
|
"tx_stn_cpu_2" 8;
|
||
|
|
"tx_stn_cpu_3" 8;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*************************************************************/
|
||
|
|
// Security Message Station
|
||
|
|
|
||
|
|
bucket "sec_pipe_0" {
|
||
|
|
size 128;
|
||
|
|
"tx_stn_cpu_0" 32;
|
||
|
|
"tx_stn_cpu_1" 32;
|
||
|
|
"tx_stn_cpu_2" 32;
|
||
|
|
"tx_stn_cpu_3" 32;
|
||
|
|
}
|
||
|
|
|
||
|
|
bucket "sec_rsa_ecc" {
|
||
|
|
size 128;
|
||
|
|
"tx_stn_cpu_0" 32;
|
||
|
|
"tx_stn_cpu_1" 32;
|
||
|
|
"tx_stn_cpu_2" 32;
|
||
|
|
"tx_stn_cpu_3" 32;
|
||
|
|
}
|
||
|
|
|
||
|
|
bucket "dma_rsvd_0" {
|
||
|
|
size 64;
|
||
|
|
"tx_stn_cpu_0" 16;
|
||
|
|
"tx_stn_cpu_1" 16;
|
||
|
|
"tx_stn_cpu_2" 16;
|
||
|
|
"tx_stn_cpu_3" 16;
|
||
|
|
}
|
||
|
|
bucket "dma_rsvd_1" {
|
||
|
|
size 64;
|
||
|
|
"tx_stn_cpu_0" 16;
|
||
|
|
"tx_stn_cpu_1" 16;
|
||
|
|
"tx_stn_cpu_2" 16;
|
||
|
|
"tx_stn_cpu_3" 16;
|
||
|
|
}
|
||
|
|
|
||
|
|
bucket "dma_rsvd_2" {
|
||
|
|
size 64;
|
||
|
|
"tx_stn_cpu_0" 16;
|
||
|
|
"tx_stn_cpu_1" 16;
|
||
|
|
"tx_stn_cpu_2" 16;
|
||
|
|
"tx_stn_cpu_3" 16;
|
||
|
|
}
|
||
|
|
|
||
|
|
bucket "dma_rsvd_3" {
|
||
|
|
size 64;
|
||
|
|
"tx_stn_cpu_0" 16;
|
||
|
|
"tx_stn_cpu_1" 16;
|
||
|
|
"tx_stn_cpu_2" 16;
|
||
|
|
"tx_stn_cpu_3" 16;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*************************************************************/
|
||
|
|
// Compression Message Station
|
||
|
|
|
||
|
|
bucket "cmp_0" {
|
||
|
|
size 32;
|
||
|
|
"tx_stn_cpu_0" 16;
|
||
|
|
"tx_stn_cpu_1" 16;
|
||
|
|
}
|
||
|
|
|
||
|
|
bucket "cmp_1" {
|
||
|
|
size 32;
|
||
|
|
"tx_stn_cpu_0" 16;
|
||
|
|
"tx_stn_cpu_1" 16;
|
||
|
|
}
|
||
|
|
|
||
|
|
bucket "cmp_2" {
|
||
|
|
size 32;
|
||
|
|
"tx_stn_cpu_0" 16;
|
||
|
|
"tx_stn_cpu_1" 16;
|
||
|
|
}
|
||
|
|
|
||
|
|
bucket "cmp_3" {
|
||
|
|
size 32;
|
||
|
|
"tx_stn_cpu_0" 16;
|
||
|
|
"tx_stn_cpu_1" 16;
|
||
|
|
}
|
||
|
|
|