2000-05-07 04:53:04 +00:00
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/* $FreeBSD$ */
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2005-01-05 20:05:52 +00:00
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/*-
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2000-05-07 04:53:04 +00:00
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* Copyright (c) 1998, 2000 by Matthew Jacob
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* 'Register' definitions for the MCBUS main
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* system bus found on AlphaServer 4100 systems.
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*/
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/*
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* Information gathered from:"
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*
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* "Rawhide System Programmer's Manual, revision 1.4".
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*/
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/*
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* There are 7 possible MC bus modules (architecture says 10, but
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* the address map details say otherwise), 1 though 7.
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* Their uses are defined as follows:
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*
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* MID Module
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* ---- ------
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* 1 Memory
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* 2 CPU
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* 3 CPU
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* 4 CPU, PCI
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* 5 CPU, PCI
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* 6 CPU, PCI
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* 7 CPU, PCI
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*
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*/
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#define MCBUS_MID_MAX 7
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/*
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* For this architecture, bit 39 of a 40 bit address controls whether
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* you access I/O or Memory space. Further, there *could* be multiple
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* MC busses (but only one specified for now).
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*/
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#define MCBUS_IOSPACE 0x0000008000000000L
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#define MCBUS_GID_MASK 0x0000007000000000L
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#define MCBUS_GID_SHIFT 36
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#define MCBUS_MID_MASK 0x0000000E00000000L
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#define MCBUS_MID_SHIFT 33
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#define MAX_MC_BUS 8
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2001-02-13 22:45:53 +00:00
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#define MCPCIA_PER_MCBUS 4
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#define MCPCIA_PCI_MIDMIN 4
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2000-05-07 04:53:04 +00:00
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/*
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* This is something of a layering violation, but it makes probing cleaner.
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*/
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/* the MCPCIA bridge CSR addresses, offset zero, is a good thing to probe for */
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#define MCPCIA_BRIDGE_ADDR(gid, mid) \
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(MCBUS_IOSPACE | 0x1E0000000LL | \
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(((unsigned long) gid) << MCBUS_GID_SHIFT) | \
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(((unsigned long) mid) << MCBUS_MID_SHIFT))
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