338 lines
12 KiB
C
338 lines
12 KiB
C
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/***********************license start***************
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* Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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*
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
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* OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
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* RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
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* REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
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* DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
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* OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
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* PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
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* POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
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* OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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*
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*
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* For any questions regarding licensing please contact marketing@caviumnetworks.com
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*
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***********************license end**************************************/
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/**
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* @file
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*
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* Fixes and workaround for Octeon chip errata. This file
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* contains functions called by cvmx-helper to workaround known
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* chip errata. For the most part, code doesn't need to call
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* these functions directly.
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*
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* <hr>$Revision: 42150 $<hr>
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*/
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#include "cvmx.h"
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#include "cvmx-fpa.h"
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#include "cvmx-pip.h"
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#include "cvmx-pko.h"
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#include "cvmx-ipd.h"
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#include "cvmx-asx.h"
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#include "cvmx-gmx.h"
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#include "cvmx-spi.h"
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#include "cvmx-pow.h"
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#include "cvmx-sysinfo.h"
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#include "cvmx-helper.h"
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#include "cvmx-helper-util.h"
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#ifdef CVMX_ENABLE_PKO_FUNCTIONS
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/**
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* @INTERNAL
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* Function to adjust internal IPD pointer alignments
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*
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* @return 0 on success
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* !0 on failure
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*/
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int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
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{
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#define FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES (CVMX_FPA_PACKET_POOL_SIZE-8-CVMX_HELPER_FIRST_MBUFF_SKIP)
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#define FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES (CVMX_FPA_PACKET_POOL_SIZE-8-CVMX_HELPER_NOT_FIRST_MBUFF_SKIP)
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#define FIX_IPD_OUTPORT 0
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#define INTERFACE(port) (port >> 4) /* Ports 0-15 are interface 0, 16-31 are interface 1 */
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#define INDEX(port) (port & 0xf)
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uint64_t *p64;
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cvmx_pko_command_word0_t pko_command;
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cvmx_buf_ptr_t g_buffer, pkt_buffer;
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cvmx_wqe_t *work;
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int size, num_segs = 0, wqe_pcnt, pkt_pcnt;
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cvmx_gmxx_prtx_cfg_t gmx_cfg;
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int retry_cnt;
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int retry_loop_cnt;
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int mtu;
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int i;
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cvmx_helper_link_info_t link_info;
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/* Save values for restore at end */
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uint64_t prtx_cfg = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
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uint64_t tx_ptr_en = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)));
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uint64_t rx_ptr_en = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)));
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uint64_t rxx_jabber = cvmx_read_csr(CVMX_GMXX_RXX_JABBER(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
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uint64_t frame_max = cvmx_read_csr(CVMX_GMXX_RXX_FRM_MAX(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
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/* Configure port to gig FDX as required for loopback mode */
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cvmx_helper_rgmii_internal_loopback(FIX_IPD_OUTPORT);
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/* Disable reception on all ports so if traffic is present it will not interfere. */
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cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 0);
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cvmx_wait(100000000ull);
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for (retry_loop_cnt = 0;retry_loop_cnt < 10;retry_loop_cnt++)
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{
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retry_cnt = 100000;
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wqe_pcnt = cvmx_read_csr(CVMX_IPD_PTR_COUNT);
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pkt_pcnt = (wqe_pcnt >> 7) & 0x7f;
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wqe_pcnt &= 0x7f;
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num_segs = (2 + pkt_pcnt - wqe_pcnt) & 3;
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if (num_segs == 0)
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goto fix_ipd_exit;
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num_segs += 1;
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size = FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES + ((num_segs-1)*FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES) -
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(FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES / 2);
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cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), 1 << INDEX(FIX_IPD_OUTPORT));
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CVMX_SYNC;
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g_buffer.u64 = 0;
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g_buffer.s.addr = cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_WQE_POOL));
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if (g_buffer.s.addr == 0) {
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cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT buffer allocation failure.\n");
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goto fix_ipd_exit;
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}
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g_buffer.s.pool = CVMX_FPA_WQE_POOL;
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g_buffer.s.size = num_segs;
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pkt_buffer.u64 = 0;
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pkt_buffer.s.addr = cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_PACKET_POOL));
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if (pkt_buffer.s.addr == 0) {
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cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT buffer allocation failure.\n");
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goto fix_ipd_exit;
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}
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pkt_buffer.s.i = 1;
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pkt_buffer.s.pool = CVMX_FPA_PACKET_POOL;
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pkt_buffer.s.size = FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES;
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p64 = (uint64_t*) cvmx_phys_to_ptr(pkt_buffer.s.addr);
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p64[0] = 0xffffffffffff0000ull;
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p64[1] = 0x08004510ull;
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p64[2] = ((uint64_t)(size-14) << 48) | 0x5ae740004000ull;
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p64[3] = 0x3a5fc0a81073c0a8ull;
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for (i=0;i<num_segs;i++)
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{
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if (i>0)
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pkt_buffer.s.size = FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES;
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if (i==(num_segs-1))
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pkt_buffer.s.i = 0;
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*(uint64_t*)cvmx_phys_to_ptr(g_buffer.s.addr + 8*i) = pkt_buffer.u64;
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}
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/* Build the PKO command */
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pko_command.u64 = 0;
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pko_command.s.segs = num_segs;
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pko_command.s.total_bytes = size;
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pko_command.s.dontfree = 0;
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pko_command.s.gather = 1;
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gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
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gmx_cfg.s.en = 1;
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cvmx_write_csr(CVMX_GMXX_PRTX_CFG(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), gmx_cfg.u64);
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cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 1 << INDEX(FIX_IPD_OUTPORT));
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cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 1 << INDEX(FIX_IPD_OUTPORT));
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mtu = cvmx_read_csr(CVMX_GMXX_RXX_JABBER(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
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cvmx_write_csr(CVMX_GMXX_RXX_JABBER(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), 65392-14-4);
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cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), 65392-14-4);
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cvmx_pko_send_packet_prepare(FIX_IPD_OUTPORT, cvmx_pko_get_base_queue(FIX_IPD_OUTPORT), CVMX_PKO_LOCK_CMD_QUEUE);
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cvmx_pko_send_packet_finish(FIX_IPD_OUTPORT, cvmx_pko_get_base_queue(FIX_IPD_OUTPORT), pko_command, g_buffer, CVMX_PKO_LOCK_CMD_QUEUE);
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CVMX_SYNC;
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do {
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work = cvmx_pow_work_request_sync(CVMX_POW_WAIT);
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retry_cnt--;
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} while ((work == NULL) && (retry_cnt > 0));
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if (!retry_cnt)
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cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT get_work() timeout occured.\n");
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/* Free packet */
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if (work)
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cvmx_helper_free_packet_data(work);
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}
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fix_ipd_exit:
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/* Return CSR configs to saved values */
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cvmx_write_csr(CVMX_GMXX_PRTX_CFG(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), prtx_cfg);
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cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), tx_ptr_en);
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cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), rx_ptr_en);
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cvmx_write_csr(CVMX_GMXX_RXX_JABBER(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), rxx_jabber);
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cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), frame_max);
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cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), 0);
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link_info.u64 = 0; /* Set link to down so autonegotiation will set it up again */
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cvmx_helper_link_set(FIX_IPD_OUTPORT, link_info);
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/* Bring the link back up as autonegotiation is not done in user applications. */
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cvmx_helper_link_autoconf(FIX_IPD_OUTPORT);
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CVMX_SYNC;
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if (num_segs)
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cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT failed.\n");
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return(!!num_segs);
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}
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/**
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* @INTERNAL
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* Workaround ASX setup errata with CN38XX pass1
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*
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* @param interface Interface to setup
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* @param port Port to setup (0..3)
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* @param cpu_clock_hz
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* Chip frequency in Hertz
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*
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* @return Zero on success, negative on failure
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*/
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int __cvmx_helper_errata_asx_pass1(int interface, int port, int cpu_clock_hz)
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{
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/* Set hi water mark as per errata GMX-4 */
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if (cpu_clock_hz >= 325000000 && cpu_clock_hz < 375000000)
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cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 12);
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else if (cpu_clock_hz >= 375000000 && cpu_clock_hz < 437000000)
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cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 11);
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else if (cpu_clock_hz >= 437000000 && cpu_clock_hz < 550000000)
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cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 10);
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else if (cpu_clock_hz >= 550000000 && cpu_clock_hz < 687000000)
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cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 9);
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else
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cvmx_dprintf("Illegal clock frequency (%d). CVMX_ASXX_TX_HI_WATERX not set\n", cpu_clock_hz);
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return 0;
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}
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/**
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* This function needs to be called on all Octeon chips with
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* errata PKI-100.
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*
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* The Size field is 8 too large in WQE and next pointers
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*
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* The Size field generated by IPD is 8 larger than it should
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* be. The Size field is <55:40> of both:
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* - WORD3 in the work queue entry, and
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* - the next buffer pointer (which precedes the packet data
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* in each buffer).
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*
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* @param work Work queue entry to fix
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* @return Zero on success. Negative on failure
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*/
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int cvmx_helper_fix_ipd_packet_chain(cvmx_wqe_t *work)
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{
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uint64_t number_buffers = work->word2.s.bufs;
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/* We only need to do this if the work has buffers */
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if (number_buffers)
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{
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cvmx_buf_ptr_t buffer_ptr = work->packet_ptr;
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/* Check for errata PKI-100 */
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if ( (buffer_ptr.s.pool == 0) && (((uint64_t)buffer_ptr.s.size +
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((uint64_t)buffer_ptr.s.back << 7) + ((uint64_t)buffer_ptr.s.addr & 0x7F))
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!= (CVMX_FPA_PACKET_POOL_SIZE+8))) {
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/* fix is not needed */
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return 0;
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}
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/* Decrement the work packet pointer */
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buffer_ptr.s.size -= 8;
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work->packet_ptr = buffer_ptr;
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/* Now loop through decrementing the size for each additional buffer */
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while (--number_buffers)
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{
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/* Chain pointers are 8 bytes before the data */
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cvmx_buf_ptr_t *ptr = (cvmx_buf_ptr_t*)cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
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buffer_ptr = *ptr;
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buffer_ptr.s.size -= 8;
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*ptr = buffer_ptr;
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}
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}
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/* Make sure that these write go out before other operations such as FPA frees */
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CVMX_SYNCWS;
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return 0;
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}
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#endif /* CVMX_ENABLE_PKO_FUNCTIONS */
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/**
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||
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* Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
|
||
|
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* 1 doesn't work properly. The following code disables 2nd order
|
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|
|
* CDR for the specified QLM.
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||
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|
*
|
||
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* @param qlm QLM to disable 2nd order CDR for.
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||
|
|
*/
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||
|
|
void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm)
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||
|
|
{
|
||
|
|
int lane;
|
||
|
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cvmx_helper_qlm_jtag_init();
|
||
|
|
/* We need to load all four lanes of the QLM, a total of 1072 bits */
|
||
|
|
for (lane=0; lane<4; lane++)
|
||
|
|
{
|
||
|
|
/* Each lane has 268 bits. We need to set cfg_cdr_incx<67:64>=3 and
|
||
|
|
cfg_cdr_secord<77>=1. All other bits are zero. Bits go in LSB
|
||
|
|
first, so start off with the zeros for bits <63:0> */
|
||
|
|
cvmx_helper_qlm_jtag_shift_zeros(qlm, 63 - 0 + 1);
|
||
|
|
/* cfg_cdr_incx<67:64>=3 */
|
||
|
|
cvmx_helper_qlm_jtag_shift(qlm, 67 - 64 + 1, 3);
|
||
|
|
/* Zeros for bits <76:68> */
|
||
|
|
cvmx_helper_qlm_jtag_shift_zeros(qlm, 76 - 68 + 1);
|
||
|
|
/* cfg_cdr_secord<77>=1 */
|
||
|
|
cvmx_helper_qlm_jtag_shift(qlm, 77 - 77 + 1, 1);
|
||
|
|
/* Zeros for bits <267:78> */
|
||
|
|
cvmx_helper_qlm_jtag_shift_zeros(qlm, 267 - 78 + 1);
|
||
|
|
}
|
||
|
|
cvmx_helper_qlm_jtag_update(qlm);
|
||
|
|
}
|
||
|
|
|