2011-11-16 17:11:13 +00:00
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/*-
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* Copyright 2009 Solarflare Communications Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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2011-11-28 17:19:05 +00:00
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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2011-11-16 17:11:13 +00:00
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#include "efsys.h"
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#include "efx.h"
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#include "efx_impl.h"
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#if EFSYS_OPT_SIENA
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void
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siena_sram_init(
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__in efx_nic_t *enp)
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{
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efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
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efx_oword_t oword;
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uint32_t rx_base, tx_base;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA);
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rx_base = encp->enc_buftbl_limit;
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tx_base = rx_base + (encp->enc_rxq_limit * 64);
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/* Initialize the transmit descriptor cache */
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EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_TX_DC_BASE_ADR, tx_base);
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EFX_BAR_WRITEO(enp, FR_AZ_SRM_TX_DC_CFG_REG, &oword);
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EFX_POPULATE_OWORD_1(oword, FRF_AZ_TX_DC_SIZE, 1); /* 16 descriptors */
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EFX_BAR_WRITEO(enp, FR_AZ_TX_DC_CFG_REG, &oword);
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/* Initialize the receive descriptor cache */
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EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_RX_DC_BASE_ADR, rx_base);
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EFX_BAR_WRITEO(enp, FR_AZ_SRM_RX_DC_CFG_REG, &oword);
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EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_SIZE, 3); /* 64 descriptors */
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EFX_BAR_WRITEO(enp, FR_AZ_RX_DC_CFG_REG, &oword);
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/* Set receive descriptor pre-fetch low water mark */
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EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_PF_LWM, 56);
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EFX_BAR_WRITEO(enp, FR_AZ_RX_DC_PF_WM_REG, &oword);
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/* Set the event queue to use for SRAM updates */
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EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_UPD_EVQ_ID, 0);
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EFX_BAR_WRITEO(enp, FR_AZ_SRM_UPD_EVQ_REG, &oword);
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}
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#if EFSYS_OPT_DIAG
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__checkReturn int
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siena_sram_test(
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__in efx_nic_t *enp,
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__in efx_sram_pattern_fn_t func)
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{
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efx_oword_t oword;
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efx_qword_t qword;
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efx_qword_t verify;
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size_t rows;
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unsigned int wptr;
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unsigned int rptr;
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int rc;
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EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA);
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/* Reconfigure into HALF buffer table mode */
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EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 0);
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EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);
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/*
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* Move the descriptor caches up to the top of SRAM, and test
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* all of SRAM below them. We only miss out one row here.
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*/
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rows = SIENA_SRAM_ROWS - 1;
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EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_RX_DC_BASE_ADR, rows);
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EFX_BAR_WRITEO(enp, FR_AZ_SRM_RX_DC_CFG_REG, &oword);
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EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_TX_DC_BASE_ADR, rows + 1);
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EFX_BAR_WRITEO(enp, FR_AZ_SRM_TX_DC_CFG_REG, &oword);
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/*
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* Write the pattern through BUF_HALF_TBL. Write
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* in 64 entry batches, waiting 1us in between each batch
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* to guarantee not to overflow the SRAM fifo
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*/
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for (wptr = 0, rptr = 0; wptr < rows; ++wptr) {
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func(wptr, B_FALSE, &qword);
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EFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_HALF_TBL, wptr, &qword);
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if ((wptr - rptr) < 64 && wptr < rows - 1)
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continue;
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EFSYS_SPIN(1);
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for (; rptr <= wptr; ++rptr) {
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func(rptr, B_FALSE, &qword);
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EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_HALF_TBL, rptr,
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&verify);
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if (!EFX_QWORD_IS_EQUAL(verify, qword)) {
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rc = EFAULT;
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goto fail1;
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}
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}
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}
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/* And do the same negated */
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for (wptr = 0, rptr = 0; wptr < rows; ++wptr) {
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func(wptr, B_TRUE, &qword);
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EFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_HALF_TBL, wptr, &qword);
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if ((wptr - rptr) < 64 && wptr < rows - 1)
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continue;
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EFSYS_SPIN(1);
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for (; rptr <= wptr; ++rptr) {
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func(rptr, B_TRUE, &qword);
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EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_HALF_TBL, rptr,
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&verify);
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if (!EFX_QWORD_IS_EQUAL(verify, qword)) {
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rc = EFAULT;
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goto fail2;
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}
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}
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}
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/* Restore back to FULL buffer table mode */
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EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 1);
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EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);
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/*
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* We don't need to reconfigure SRAM again because the API
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* requires efx_nic_fini() to be called after an sram test.
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*/
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return (0);
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fail2:
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EFSYS_PROBE(fail2);
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fail1:
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EFSYS_PROBE1(fail1, int, rc);
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/* Restore back to FULL buffer table mode */
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EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 1);
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EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);
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return (rc);
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}
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#endif /* EFSYS_OPT_DIAG */
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#endif /* EFSYS_OPT_SIENA */
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