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freebsd-dev/sys/powerpc/aim/trap_subr.S

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Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
/* $FreeBSD$ */
/* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */
/* -> /*- for license, minor formatting changes
2005-01-07 02:29:27 +00:00
/*-
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
* Copyright (C) 1995, 1996 Wolfgang Solfrank.
* Copyright (C) 1995, 1996 TooLs GmbH.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by TooLs GmbH.
* 4. The name of TooLs GmbH may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* NOTICE: This is not a standalone file. to use it, #include it in
* your port's locore.S, like so:
*
* #include <powerpc/powerpc/trap_subr.S>
*/
/*
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
* Save/restore segment registers
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
*/
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
#define RESTORE_SRS(pmap,sr) mtsr 0,sr; \
lwz sr,1*4(pmap); mtsr 1,sr; \
lwz sr,2*4(pmap); mtsr 2,sr; \
lwz sr,3*4(pmap); mtsr 3,sr; \
lwz sr,4*4(pmap); mtsr 4,sr; \
lwz sr,5*4(pmap); mtsr 5,sr; \
lwz sr,6*4(pmap); mtsr 6,sr; \
lwz sr,7*4(pmap); mtsr 7,sr; \
lwz sr,8*4(pmap); mtsr 8,sr; \
lwz sr,9*4(pmap); mtsr 9,sr; \
lwz sr,10*4(pmap); mtsr 10,sr; \
lwz sr,11*4(pmap); mtsr 11,sr; \
lwz sr,12*4(pmap); mtsr 12,sr; \
lwz sr,13*4(pmap); mtsr 13,sr; \
lwz sr,14*4(pmap); mtsr 14,sr; \
lwz sr,15*4(pmap); mtsr 15,sr; isync;
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
/*
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
* User SRs are loaded through a pointer to the current pmap.
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
*/
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
#define RESTORE_USER_SRS(pmap,sr) \
GET_CPUINFO(pmap); \
lwz pmap,PC_CURPMAP(pmap); \
lwzu sr,PM_SR(pmap); \
RESTORE_SRS(pmap,sr)
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
/*
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
* Kernel SRs are loaded directly from kernel_pmap_
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
*/
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
#define RESTORE_KERN_SRS(pmap,sr) \
lis pmap,CNAME(kernel_pmap_store)@ha; \
lwzu sr,CNAME(kernel_pmap_store)+PM_SR@l(pmap); \
RESTORE_SRS(pmap,sr)
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
/*
* FRAME_SETUP assumes:
* SPRG1 SP (1)
* savearea r28-r31,DAR,DSISR (DAR & DSISR only for DSI traps)
* r28 LR
* r29 CR
* r30 scratch
* r31 scratch
* r1 kernel stack
* LR trap type (from calling address, mask with 0xff00)
* SRR0/1 as at start of trap
*/
#define FRAME_SETUP(savearea) \
/* Have to enable translation to allow access of kernel stack: */ \
GET_CPUINFO(%r31); \
mfsrr0 %r30; \
stw %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \
mfsrr1 %r30; \
stw %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \
mfmsr %r30; \
ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \
mtmsr %r30; /* stack can now be accessed */ \
isync; \
mfsprg1 %r31; /* get saved SP */ \
stwu %r31,-FRAMELEN(%r1); /* save it in the callframe */ \
stw %r0, FRAME_0+8(%r1); /* save r0 in the trapframe */ \
stw %r31,FRAME_1+8(%r1); /* save SP " " */ \
stw %r2, FRAME_2+8(%r1); /* save r2 " " */ \
stw %r28,FRAME_LR+8(%r1); /* save LR " " */ \
stw %r29,FRAME_CR+8(%r1); /* save CR " " */ \
GET_CPUINFO(%r2); \
lwz %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \
lwz %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \
lwz %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \
lwz %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \
stw %r3, FRAME_3+8(%r1); /* save r3-r31 */ \
stw %r4, FRAME_4+8(%r1); \
stw %r5, FRAME_5+8(%r1); \
stw %r6, FRAME_6+8(%r1); \
stw %r7, FRAME_7+8(%r1); \
stw %r8, FRAME_8+8(%r1); \
stw %r9, FRAME_9+8(%r1); \
stw %r10, FRAME_10+8(%r1); \
stw %r11, FRAME_11+8(%r1); \
stw %r12, FRAME_12+8(%r1); \
stw %r13, FRAME_13+8(%r1); \
stw %r14, FRAME_14+8(%r1); \
stw %r15, FRAME_15+8(%r1); \
stw %r16, FRAME_16+8(%r1); \
stw %r17, FRAME_17+8(%r1); \
stw %r18, FRAME_18+8(%r1); \
stw %r19, FRAME_19+8(%r1); \
stw %r20, FRAME_20+8(%r1); \
stw %r21, FRAME_21+8(%r1); \
stw %r22, FRAME_22+8(%r1); \
stw %r23, FRAME_23+8(%r1); \
stw %r24, FRAME_24+8(%r1); \
stw %r25, FRAME_25+8(%r1); \
stw %r26, FRAME_26+8(%r1); \
stw %r27, FRAME_27+8(%r1); \
stw %r28, FRAME_28+8(%r1); \
stw %r29, FRAME_29+8(%r1); \
stw %r30, FRAME_30+8(%r1); \
stw %r31, FRAME_31+8(%r1); \
lwz %r28,(savearea+CPUSAVE_DAR)(%r2); /* saved DAR */ \
lwz %r29,(savearea+CPUSAVE_DSISR)(%r2);/* saved DSISR */ \
lwz %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \
lwz %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \
mfxer %r3; \
mfctr %r4; \
mflr %r5; \
andi. %r5,%r5,0xff00; /* convert LR to exc # */ \
stw %r3, FRAME_XER+8(1); /* save xer/ctr/exc */ \
stw %r4, FRAME_CTR+8(1); \
stw %r5, FRAME_EXC+8(1); \
stw %r28,FRAME_DAR+8(1); \
stw %r29,FRAME_DSISR+8(1); /* save dsisr/srr0/srr1 */ \
stw %r30,FRAME_SRR0+8(1); \
stw %r31,FRAME_SRR1+8(1)
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
#define FRAME_LEAVE(savearea) \
/* Now restore regs: */ \
lwz %r2,FRAME_SRR0+8(%r1); \
lwz %r3,FRAME_SRR1+8(%r1); \
lwz %r4,FRAME_CTR+8(%r1); \
lwz %r5,FRAME_XER+8(%r1); \
lwz %r6,FRAME_LR+8(%r1); \
GET_CPUINFO(%r7); \
stw %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \
stw %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \
lwz %r7,FRAME_CR+8(%r1); \
mtctr %r4; \
mtxer %r5; \
mtlr %r6; \
mtsprg1 %r7; /* save cr */ \
lwz %r31,FRAME_31+8(%r1); /* restore r0-31 */ \
lwz %r30,FRAME_30+8(%r1); \
lwz %r29,FRAME_29+8(%r1); \
lwz %r28,FRAME_28+8(%r1); \
lwz %r27,FRAME_27+8(%r1); \
lwz %r26,FRAME_26+8(%r1); \
lwz %r25,FRAME_25+8(%r1); \
lwz %r24,FRAME_24+8(%r1); \
lwz %r23,FRAME_23+8(%r1); \
lwz %r22,FRAME_22+8(%r1); \
lwz %r21,FRAME_21+8(%r1); \
lwz %r20,FRAME_20+8(%r1); \
lwz %r19,FRAME_19+8(%r1); \
lwz %r18,FRAME_18+8(%r1); \
lwz %r17,FRAME_17+8(%r1); \
lwz %r16,FRAME_16+8(%r1); \
lwz %r15,FRAME_15+8(%r1); \
lwz %r14,FRAME_14+8(%r1); \
lwz %r13,FRAME_13+8(%r1); \
lwz %r12,FRAME_12+8(%r1); \
lwz %r11,FRAME_11+8(%r1); \
lwz %r10,FRAME_10+8(%r1); \
lwz %r9, FRAME_9+8(%r1); \
lwz %r8, FRAME_8+8(%r1); \
lwz %r7, FRAME_7+8(%r1); \
lwz %r6, FRAME_6+8(%r1); \
lwz %r5, FRAME_5+8(%r1); \
lwz %r4, FRAME_4+8(%r1); \
lwz %r3, FRAME_3+8(%r1); \
lwz %r2, FRAME_2+8(%r1); \
lwz %r0, FRAME_0+8(%r1); \
lwz %r1, FRAME_1+8(%r1); \
/* Can't touch %r1 from here on */ \
mtsprg2 %r2; /* save r2 & r3 */ \
mtsprg3 %r3; \
/* Disable translation, machine check and recoverability: */ \
mfmsr %r2; \
andi. %r2,%r2,~(PSL_DR|PSL_IR|PSL_EE|PSL_ME|PSL_RI)@l; \
mtmsr %r2; \
isync; \
/* Decide whether we return to user mode: */ \
GET_CPUINFO(%r2); \
lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); \
mtcr %r3; \
bf 17,1f; /* branch if PSL_PR is false */ \
/* Restore user SRs */ \
RESTORE_USER_SRS(%r2,%r3); \
1: mfsprg1 %r2; /* restore cr */ \
mtcr %r2; \
GET_CPUINFO(%r2); \
lwz %r3,(savearea+CPUSAVE_SRR0)(%r2); /* restore srr0 */ \
mtsrr0 %r3; \
lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); /* restore srr1 */ \
mtsrr1 %r3; \
mfsprg2 %r2; /* restore r2 & r3 */ \
mfsprg3 %r3
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
Detect kernel stack excursion into guard pages. Drop into KDB with a wired stack if this is found. Mostly obtained from: NetBSD
2004-07-23 05:33:24 +00:00
#ifdef KDB
/*
* Define the kdb debugger stack
*/
.data
GLOBAL(dbstk)
.space INTSTK+8 /* kdb stack */
#endif
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
/*
* This code gets copied to all the trap vectors
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
* (except ISI/DSI, ALI, and the interrupts)
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
*/
.text
- Rename the _C_LABEL macro to CNAME. - Rename the _ASM_LABEL macro to ASMNAME. - Add the HIDENAME macro which is used in libc's syscall stuff.
2002-05-17 01:44:55 +00:00
.globl CNAME(trapcode),CNAME(trapsize)
CNAME(trapcode):
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
mtsprg1 %r1 /* save SP */
GET_CPUINFO(%r1)
stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */
stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
mfsprg1 %r1 /* restore SP, in case of branch */
mflr %r28 /* save LR */
mfcr %r29 /* save CR */
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
/* Test whether we already had PR set */
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
mfsrr1 %r31
mtcr %r31
bla s_trap /* LR & 0xff00 is exception # */
- Rename the _C_LABEL macro to CNAME. - Rename the _ASM_LABEL macro to ASMNAME. - Add the HIDENAME macro which is used in libc's syscall stuff.
2002-05-17 01:44:55 +00:00
CNAME(trapsize) = .-CNAME(trapcode)
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
/*
* For ALI: has to save DSISR and DAR
*/
- Rename the _C_LABEL macro to CNAME. - Rename the _ASM_LABEL macro to ASMNAME. - Add the HIDENAME macro which is used in libc's syscall stuff.
2002-05-17 01:44:55 +00:00
.globl CNAME(alitrap),CNAME(alisize)
CNAME(alitrap):
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
mtsprg1 %r1 /* save SP */
GET_CPUINFO(%r1)
stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */
stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
mfdar %r30
mfdsisr %r31
stw %r30,(PC_TEMPSAVE+CPUSAVE_DAR)(%r1)
stw %r31,(PC_TEMPSAVE+CPUSAVE_DSISR)(%r1)
mfsprg1 %r1 /* restore SP, in case of branch */
mflr %r28 /* save LR */
mfcr %r29 /* save CR */
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
/* Test whether we already had PR set */
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
mfsrr1 %r31
mtcr %r31
bla s_trap /* LR & 0xff00 is exception # */
- Rename the _C_LABEL macro to CNAME. - Rename the _ASM_LABEL macro to ASMNAME. - Add the HIDENAME macro which is used in libc's syscall stuff.
2002-05-17 01:44:55 +00:00
CNAME(alisize) = .-CNAME(alitrap)
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
/*
* Similar to the above for DSI
* Has to handle BAT spills
* and standard pagetable spills
*/
- Rename the _C_LABEL macro to CNAME. - Rename the _ASM_LABEL macro to ASMNAME. - Add the HIDENAME macro which is used in libc's syscall stuff.
2002-05-17 01:44:55 +00:00
.globl CNAME(dsitrap),CNAME(dsisize)
CNAME(dsitrap):
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
mtsprg1 %r1 /* save SP */
GET_CPUINFO(%r1)
stw %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */
stw %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1)
stw %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
stw %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
mfsprg1 %r1 /* restore SP */
mfcr %r29 /* save CR */
mfxer %r30 /* save XER */
mtsprg2 %r30 /* in SPRG2 */
mfsrr1 %r31 /* test kernel mode */
mtcr %r31
bt 17,1f /* branch if PSL_PR is set */
mfdar %r31 /* get fault address */
rlwinm %r31,%r31,7,25,28 /* get segment * 8 */
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
/* get batu */
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
addis %r31,%r31,CNAME(battable)@ha
lwz %r30,CNAME(battable)@l(31)
mtcr %r30
bf 30,1f /* branch if supervisor valid is
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
false */
/* get batl */
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
lwz %r31,CNAME(battable)+4@l(31)
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
/* We randomly use the highest two bat registers here */
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
mftb %r28
andi. %r28,%r28,1
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
bne 2f
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
mtdbatu 2,%r30
mtdbatl 2,%r31
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
b 3f
2:
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
mtdbatu 3,%r30
mtdbatl 3,%r31
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
3:
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
mfsprg2 %r30 /* restore XER */
mtxer %r30
mtcr %r29 /* restore CR */
mtsprg1 %r1
GET_CPUINFO(%r1)
lwz %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* restore r28-r31 */
lwz %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1)
lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
mfsprg1 %r1
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
rfi /* return to trapped code */
1:
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
mflr %r28 /* save LR (SP already saved) */
bla disitrap
- Rename the _C_LABEL macro to CNAME. - Rename the _ASM_LABEL macro to ASMNAME. - Add the HIDENAME macro which is used in libc's syscall stuff.
2002-05-17 01:44:55 +00:00
CNAME(dsisize) = .-CNAME(dsitrap)
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
/*
* Preamble code for DSI/ISI traps
*/
disitrap:
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
GET_CPUINFO(%r1)
lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1)
stw %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1)
stw %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
mfdar %r30
mfdsisr %r31
stw %r30,(PC_TEMPSAVE+CPUSAVE_DAR)(%r1)
stw %r31,(PC_TEMPSAVE+CPUSAVE_DSISR)(%r1)
Detect kernel stack excursion into guard pages. Drop into KDB with a wired stack if this is found. Mostly obtained from: NetBSD
2004-07-23 05:33:24 +00:00
#ifdef KDB
/* Try and detect a kernel stack overflow */
mfsrr1 %r31
mtcr %r31
bt 17,realtrap /* branch is user mode */
mfsprg1 %r31 /* get old SP */
sub. %r30,%r31,%r30 /* SP - DAR */
bge 1f
neg %r30,%r30 /* modulo value */
1: cmplwi %cr0,%r30,4096 /* is DAR within a page of SP? */
bge %cr0,realtrap /* no, too far away. */
/* Now convert this DSI into a DDB trap. */
GET_CPUINFO(%r1)
Save DAR/DSISR in DDB regsave area when stack overflow detected. It's hard to work out where the problem was without these.
2004-07-27 03:46:34 +00:00
lwz %r30,(PC_TEMPSAVE+CPUSAVE_DAR)(%r1) /* get DAR */
stw %r30,(PC_DBSAVE +CPUSAVE_DAR)(%r1) /* save DAR */
lwz %r30,(PC_TEMPSAVE+CPUSAVE_DSISR)(%r1) /* get DSISR */
lwz %r30,(PC_DBSAVE +CPUSAVE_DSISR)(%r1) /* save DSISR */
Detect kernel stack excursion into guard pages. Drop into KDB with a wired stack if this is found. Mostly obtained from: NetBSD
2004-07-23 05:33:24 +00:00
lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */
stw %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */
lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */
stw %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */
lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */
stw %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */
lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */
stw %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */
lis %r1,dbstk+INTSTK@ha /* get new SP */
addi %r1,%r1,dbstk+INTSTK@l
b dbtrap
#endif
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
/* XXX need stack probe here */
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
realtrap:
/* Test whether we already had PR set */
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
mfsrr1 %r1
mtcr %r1
mfsprg1 %r1 /* restore SP (might have been
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
overwritten) */
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
s_trap:
bf 17,k_trap /* branch if PSL_PR is false */
GET_CPUINFO(%r1)
u_trap:
lwz %r1,PC_CURPCB(%r1)
RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
/*
* Now the common trap catching code.
*/
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
k_trap:
FRAME_SETUP(PC_TEMPSAVE)
Many fixes to low-level trap and interrupt handling: - Tidy up clock code. Don't repeatedly call hardclock(). - Remove intrnames, decrnest and intrcnt from locore.s - Coalesce all trap handling into a single stub that then calls a dispatch function. Submitted by: Peter Grehan <peterg@ptree32.com.au>
2002-06-29 09:28:21 +00:00
/* Call C interrupt dispatcher: */
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
trapagain:
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
addi %r3,%r1,8
Many fixes to low-level trap and interrupt handling: - Tidy up clock code. Don't repeatedly call hardclock(). - Remove intrnames, decrnest and intrcnt from locore.s - Coalesce all trap handling into a single stub that then calls a dispatch function. Submitted by: Peter Grehan <peterg@ptree32.com.au>
2002-06-29 09:28:21 +00:00
bl CNAME(powerpc_interrupt)
Rename low-level code ddb -> db. Use KDB instead of DDB. Fix bug in setup of stack frame where 8 bytes wasn't being saved for the callee's frame pointer and saved LR.
2004-07-12 22:32:08 +00:00
.globl CNAME(trapexit) /* backtrace code sentinel */
- Rename the _C_LABEL macro to CNAME. - Rename the _ASM_LABEL macro to ASMNAME. - Add the HIDENAME macro which is used in libc's syscall stuff.
2002-05-17 01:44:55 +00:00
CNAME(trapexit):
Many fixes to low-level trap and interrupt handling: - Tidy up clock code. Don't repeatedly call hardclock(). - Remove intrnames, decrnest and intrcnt from locore.s - Coalesce all trap handling into a single stub that then calls a dispatch function. Submitted by: Peter Grehan <peterg@ptree32.com.au>
2002-06-29 09:28:21 +00:00
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
/* Disable interrupts: */
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
mfmsr %r3
andi. %r3,%r3,~PSL_EE@l
mtmsr %r3
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
/* Test AST pending: */
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
lwz %r5,FRAME_SRR1+8(%r1)
mtcr %r5
bf 17,1f /* branch if PSL_PR is false */
GET_CPUINFO(%r3) /* get per-CPU pointer */
lwz %r4, PC_CURTHREAD(%r3) /* deref to get curthread */
lwz %r4, TD_FLAGS(%r4) /* get thread flags value */
lis %r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@h
ori %r5,%r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@l
and. %r4,%r4,%r5
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
beq 1f
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
mfmsr %r3 /* re-enable interrupts */
ori %r3,%r3,PSL_EE@l
mtmsr %r3
Many fixes to low-level trap and interrupt handling: - Tidy up clock code. Don't repeatedly call hardclock(). - Remove intrnames, decrnest and intrcnt from locore.s - Coalesce all trap handling into a single stub that then calls a dispatch function. Submitted by: Peter Grehan <peterg@ptree32.com.au>
2002-06-29 09:28:21 +00:00
isync
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
addi %r3,%r1,8
- make sure recoverable interrupts are re-enabled in the trap handler - turn on ast() loop to enable signal delivery Approved by: benno
2002-09-19 04:39:04 +00:00
bl CNAME(ast)
Mark the return address of the call to ast() in the generic trap handling code so the stack trace unwinders don't start trying to go into user-space. Found by trying to create core dumps with a KTR_COMPILE/KTR_GEOM kernel, which results in a stack_save() call in the ast() coredump path - this created a panic, and then calling 'trace' in ddb resulted in the black screen of death after printing out most of the backtrace.
2005-12-23 13:05:27 +00:00
.globl CNAME(asttrapexit) /* backtrace code sentinel #2 */
CNAME(asttrapexit):
Many fixes to low-level trap and interrupt handling: - Tidy up clock code. Don't repeatedly call hardclock(). - Remove intrnames, decrnest and intrcnt from locore.s - Coalesce all trap handling into a single stub that then calls a dispatch function. Submitted by: Peter Grehan <peterg@ptree32.com.au>
2002-06-29 09:28:21 +00:00
b trapexit /* test ast ret value ? */
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
1:
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
FRAME_LEAVE(PC_TEMPSAVE)
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
rfi
Temporary band-aid to fix hang when a process exec's Altivec instructions. trap_subr.S: declare a stub for the a-unavailable trap that does an absolute jump to the vector-assist trap. This is due to the fact that the vec-unavail trap doesn't start at a 256-byte boundary, so the trick of masking the bottom 8 bits of the link register to identify the interrupt doesn't work, so let the vec-assist case handle Altivec-disabled for the time being. Note that this will be fixed in the future with a much smaller vector code-stub (< 16 bytes) that will allow use of strange vector offsets that are also present in 4xx processors, and also allow smaller differences in vector codepaths on the G5. trap.c: Treat altivec-unavailable/assist process traps as SIGILL. Not quite correct, since altivec-assist should really be a panic, but it is fine for the moment due to the above measure. machdep.c Install the stub code for the altivec-unavailable trap, and the standard trap code at the altivec-assist. Reported by: Andreas Tobler <toa at pop agri ch> MFC after: 3 days
2005-07-30 11:14:31 +00:00
/*
* Temporary: vector-unavailable traps are directed to vector-assist traps
*/
.globl CNAME(vectrap),CNAME(vectrapsize)
CNAME(vectrap):
ba EXC_VECAST
CNAME(vectrapsize) = .-CNAME(vectrap)
Rename low-level code ddb -> db. Use KDB instead of DDB. Fix bug in setup of stack frame where 8 bytes wasn't being saved for the callee's frame pointer and saved LR.
2004-07-12 22:32:08 +00:00
#if defined(KDB)
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
/*
Rename low-level code ddb -> db. Use KDB instead of DDB. Fix bug in setup of stack frame where 8 bytes wasn't being saved for the callee's frame pointer and saved LR.
2004-07-12 22:32:08 +00:00
* Deliberate entry to dbtrap
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
*/
Rename low-level code ddb -> db. Use KDB instead of DDB. Fix bug in setup of stack frame where 8 bytes wasn't being saved for the callee's frame pointer and saved LR.
2004-07-12 22:32:08 +00:00
.globl CNAME(ppc_db_trap)
CNAME(ppc_db_trap):
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
mtsprg1 %r1
mfmsr %r3
mtsrr1 %r3
andi. %r3,%r3,~(PSL_EE|PSL_ME)@l
mtmsr %r3 /* disable interrupts */
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
isync
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
GET_CPUINFO(%r3)
Rename low-level code ddb -> db. Use KDB instead of DDB. Fix bug in setup of stack frame where 8 bytes wasn't being saved for the callee's frame pointer and saved LR.
2004-07-12 22:32:08 +00:00
stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r3)
stw %r29,(PC_DBSAVE+CPUSAVE_R29)(%r3)
stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r3)
stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r3)
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
mflr %r28
li %r29,EXC_BPT
mtlr %r29
mfcr %r29
mtsrr0 %r28
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
/*
Rename low-level code ddb -> db. Use KDB instead of DDB. Fix bug in setup of stack frame where 8 bytes wasn't being saved for the callee's frame pointer and saved LR.
2004-07-12 22:32:08 +00:00
* Now the kdb trap catching code.
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
*/
Rename low-level code ddb -> db. Use KDB instead of DDB. Fix bug in setup of stack frame where 8 bytes wasn't being saved for the callee's frame pointer and saved LR.
2004-07-12 22:32:08 +00:00
dbtrap:
FRAME_SETUP(PC_DBSAVE)
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
/* Call C trap code: */
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
addi %r3,%r1,8
Rename low-level code ddb -> db. Use KDB instead of DDB. Fix bug in setup of stack frame where 8 bytes wasn't being saved for the callee's frame pointer and saved LR.
2004-07-12 22:32:08 +00:00
bl CNAME(db_trap_glue)
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
or. %r3,%r3,%r3
Rename low-level code ddb -> db. Use KDB instead of DDB. Fix bug in setup of stack frame where 8 bytes wasn't being saved for the callee's frame pointer and saved LR.
2004-07-12 22:32:08 +00:00
bne dbleave
/* This wasn't for KDB, so switch to real trap: */
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
lwz %r3,FRAME_EXC+8(%r1) /* save exception */
GET_CPUINFO(%r4)
Rename low-level code ddb -> db. Use KDB instead of DDB. Fix bug in setup of stack frame where 8 bytes wasn't being saved for the callee's frame pointer and saved LR.
2004-07-12 22:32:08 +00:00
stw %r3,(PC_DBSAVE+CPUSAVE_R31)(%r4)
FRAME_LEAVE(PC_DBSAVE)
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
mtsprg1 %r1 /* prepare for entrance to realtrap */
GET_CPUINFO(%r1)
stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
mflr %r28
mfcr %r29
Rename low-level code ddb -> db. Use KDB instead of DDB. Fix bug in setup of stack frame where 8 bytes wasn't being saved for the callee's frame pointer and saved LR.
2004-07-12 22:32:08 +00:00
lwz %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1)
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
mtlr %r31
mfsprg1 %r1
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
b realtrap
Rename low-level code ddb -> db. Use KDB instead of DDB. Fix bug in setup of stack frame where 8 bytes wasn't being saved for the callee's frame pointer and saved LR.
2004-07-12 22:32:08 +00:00
dbleave:
FRAME_LEAVE(PC_DBSAVE)
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
rfi
/*
Rename low-level code ddb -> db. Use KDB instead of DDB. Fix bug in setup of stack frame where 8 bytes wasn't being saved for the callee's frame pointer and saved LR.
2004-07-12 22:32:08 +00:00
* In case of KDB we want a separate trap catcher for it
Commit of stuff that's been sitting in my tree for a while. Highlights include: - New low-level trap code from NetBSD. The high level code still needs a lot of work. - Fixes for some pmap handling in thread switching. - The kernel will now get to attempting to jump into init in user mode. There are some pmap/trap issues which prevent it from actually getting there though. Obtained from: NetBSD (parts)
2002-04-29 12:14:31 +00:00
*/
Rename low-level code ddb -> db. Use KDB instead of DDB. Fix bug in setup of stack frame where 8 bytes wasn't being saved for the callee's frame pointer and saved LR.
2004-07-12 22:32:08 +00:00
.globl CNAME(dblow),CNAME(dbsize)
CNAME(dblow):
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
mtsprg1 %r1 /* save SP */
mtsprg2 %r29 /* save r29 */
mfcr %r29 /* save CR in r29 */
mfsrr1 %r1
mtcr %r1
GET_CPUINFO(%r1)
bf 17,1f /* branch if privileged */
stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28 */
mfsprg2 %r28 /* r29 holds cr ... */
stw %r28,(PC_TEMPSAVE+CPUSAVE_R29)(%r1) /* free r29 */
stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1) /* free r30 */
stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1) /* free r31 */
mflr %r28 /* save LR */
bla u_trap
1:
Rename low-level code ddb -> db. Use KDB instead of DDB. Fix bug in setup of stack frame where 8 bytes wasn't being saved for the callee's frame pointer and saved LR.
2004-07-12 22:32:08 +00:00
stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
mfsprg2 %r28 /* r29 holds cr... */
Rename low-level code ddb -> db. Use KDB instead of DDB. Fix bug in setup of stack frame where 8 bytes wasn't being saved for the callee's frame pointer and saved LR.
2004-07-12 22:32:08 +00:00
stw %r28,(PC_DBSAVE+CPUSAVE_R29)(%r1) /* free r29 */
stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */
stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */
Major overhaul of common trap code - remove unused 601 and tlb exception code - remove interrupt-time PTE spill code. The pmap code will now take care of pinning kernel PTEs, and there are no longer issues about physical mapping of PTE data structures - All segment registers are switched on kernel entry/exit, allowing the kernel to have more virtual space and for user virtual space to extend to 4G. - The temporary register save area has been shifted from unused exception vector space to the per-cpu data area. This allows interrupts to be delivered to multiple CPUs - ISI traps no longer spill to BAT tables. It is assumed that all of kernel instruction memory is pinned. - shift from 'ldmw/stmw' instructions to individual register loads/stores when saving context. All PPC manuals indicate this should be much faster. - use '%r' for register names throughout. TODO: need to test if DSI traps were the result of kernel stack guard-page hits. Reworked from: NetBSD
2004-02-04 13:10:25 +00:00
mflr %r28 /* save LR */
Rename low-level code ddb -> db. Use KDB instead of DDB. Fix bug in setup of stack frame where 8 bytes wasn't being saved for the callee's frame pointer and saved LR.
2004-07-12 22:32:08 +00:00
lis %r1,dbstk+INTSTK@ha /* get new SP */
addi %r1,%r1,dbstk+INTSTK@l
bla dbtrap
CNAME(dbsize) = .-CNAME(dblow)
#endif /* KDB */
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