2012-10-29 17:23:45 +00:00
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/*-
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* Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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2014-09-01 19:20:34 +00:00
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#include <sys/sysctl.h>
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2012-10-29 17:23:45 +00:00
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#include <sys/taskqueue.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/mmc/bridge.h>
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#include <dev/mmc/mmcreg.h>
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#include <dev/sdhci/sdhci.h>
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2017-03-06 23:47:59 +00:00
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#include "mmcbr_if.h"
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2012-10-29 17:23:45 +00:00
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#include "sdhci_if.h"
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2017-07-09 16:57:24 +00:00
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#include "opt_mmccam.h"
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2013-02-28 19:51:30 +00:00
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#include "bcm2835_dma.h"
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2015-03-20 16:54:21 +00:00
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#include <arm/broadcom/bcm2835/bcm2835_mbox_prop.h>
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2013-02-28 19:51:30 +00:00
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#include "bcm2835_vcbus.h"
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2012-11-30 02:32:37 +00:00
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#define BCM2835_DEFAULT_SDHCI_FREQ 50
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2013-02-28 19:51:30 +00:00
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#define BCM_SDHCI_BUFFER_SIZE 512
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2015-01-12 02:42:33 +00:00
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#define NUM_DMA_SEGS 2
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2013-02-28 19:51:30 +00:00
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2012-10-29 17:23:45 +00:00
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#ifdef DEBUG
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#define dprintf(fmt, args...) do { printf("%s(): ", __func__); \
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printf(fmt,##args); } while (0)
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#else
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#define dprintf(fmt, args...)
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#endif
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2015-01-17 19:57:03 +00:00
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static int bcm2835_sdhci_hs = 1;
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2015-05-05 00:27:55 +00:00
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static int bcm2835_sdhci_pio_mode = 0;
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2013-02-17 00:23:42 +00:00
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2016-10-12 03:00:42 +00:00
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static struct ofw_compat_data compat_data[] = {
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{"broadcom,bcm2835-sdhci", 1},
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{"brcm,bcm2835-mmc", 1},
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{NULL, 0}
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};
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2013-02-17 00:23:42 +00:00
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TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs);
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2013-02-28 19:51:30 +00:00
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TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode);
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2013-02-17 00:23:42 +00:00
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2012-10-29 17:23:45 +00:00
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struct bcm_sdhci_softc {
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device_t sc_dev;
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struct resource * sc_mem_res;
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struct resource * sc_irq_res;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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void * sc_intrhand;
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struct mmc_request * sc_req;
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struct sdhci_slot sc_slot;
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2013-02-28 19:51:30 +00:00
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int sc_dma_ch;
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bus_dma_tag_t sc_dma_tag;
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bus_dmamap_t sc_dma_map;
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2013-03-17 16:31:09 +00:00
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vm_paddr_t sc_sdhci_buffer_phys;
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2015-01-11 17:00:24 +00:00
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uint32_t cmd_and_mode;
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2015-01-12 02:42:33 +00:00
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bus_addr_t dmamap_seg_addrs[NUM_DMA_SEGS];
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bus_size_t dmamap_seg_sizes[NUM_DMA_SEGS];
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2015-01-11 21:27:46 +00:00
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int dmamap_seg_count;
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2015-01-12 02:42:33 +00:00
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int dmamap_seg_index;
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2015-01-11 21:27:46 +00:00
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int dmamap_status;
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2012-10-29 17:23:45 +00:00
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};
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static int bcm_sdhci_probe(device_t);
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static int bcm_sdhci_attach(device_t);
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static int bcm_sdhci_detach(device_t);
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static void bcm_sdhci_intr(void *);
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static int bcm_sdhci_get_ro(device_t, device_t);
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2013-02-28 19:51:30 +00:00
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static void bcm_sdhci_dma_intr(int ch, void *arg);
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2012-10-29 17:23:45 +00:00
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2013-02-28 19:51:30 +00:00
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static void
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2015-01-11 21:27:46 +00:00
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bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
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2013-02-28 19:51:30 +00:00
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{
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2015-01-11 21:27:46 +00:00
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struct bcm_sdhci_softc *sc = arg;
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int i;
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2013-02-28 19:51:30 +00:00
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2015-01-11 21:27:46 +00:00
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sc->dmamap_status = err;
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sc->dmamap_seg_count = nseg;
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2013-02-28 19:51:30 +00:00
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2015-01-11 21:27:46 +00:00
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/* Note nseg is guaranteed to be zero if err is non-zero. */
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for (i = 0; i < nseg; i++) {
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sc->dmamap_seg_addrs[i] = segs[i].ds_addr;
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sc->dmamap_seg_sizes[i] = segs[i].ds_len;
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}
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2013-02-28 19:51:30 +00:00
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}
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2012-10-29 17:23:45 +00:00
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static int
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bcm_sdhci_probe(device_t dev)
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{
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2014-02-02 19:17:28 +00:00
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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2016-10-12 03:00:42 +00:00
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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2012-10-29 17:23:45 +00:00
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return (ENXIO);
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device_set_desc(dev, "Broadcom 2708 SDHCI controller");
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2016-10-12 03:00:42 +00:00
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2012-10-29 17:23:45 +00:00
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return (BUS_PROBE_DEFAULT);
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}
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static int
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bcm_sdhci_attach(device_t dev)
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{
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struct bcm_sdhci_softc *sc = device_get_softc(dev);
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int rid, err;
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2012-11-30 02:32:37 +00:00
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phandle_t node;
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pcell_t cell;
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2015-03-20 16:54:21 +00:00
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u_int default_freq;
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2012-10-29 17:23:45 +00:00
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sc->sc_dev = dev;
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sc->sc_req = NULL;
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2015-11-05 03:46:54 +00:00
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err = bcm2835_mbox_set_power_state(BCM2835_MBOX_POWER_ID_EMMC,
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2015-03-20 16:54:21 +00:00
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TRUE);
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if (err != 0) {
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if (bootverbose)
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device_printf(dev, "Unable to enable the power\n");
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return (err);
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}
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default_freq = 0;
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2015-11-05 03:46:54 +00:00
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err = bcm2835_mbox_get_clock_rate(BCM2835_MBOX_CLOCK_ID_EMMC,
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2015-03-20 16:54:21 +00:00
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&default_freq);
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if (err == 0) {
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/* Convert to MHz */
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default_freq /= 1000000;
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2015-04-22 18:35:02 +00:00
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}
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if (default_freq == 0) {
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node = ofw_bus_get_node(sc->sc_dev);
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if ((OF_getencprop(node, "clock-frequency", &cell,
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sizeof(cell))) > 0)
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default_freq = cell / 1000000;
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2015-03-20 16:54:21 +00:00
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}
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if (default_freq == 0)
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default_freq = BCM2835_DEFAULT_SDHCI_FREQ;
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if (bootverbose)
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device_printf(dev, "SDHCI frequency: %dMHz\n", default_freq);
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2012-11-30 02:32:37 +00:00
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2012-10-29 17:23:45 +00:00
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rid = 0;
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sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (!sc->sc_mem_res) {
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device_printf(dev, "cannot allocate memory window\n");
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err = ENXIO;
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goto fail;
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}
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sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
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sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
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rid = 0;
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sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_ACTIVE);
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if (!sc->sc_irq_res) {
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device_printf(dev, "cannot allocate interrupt\n");
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err = ENXIO;
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goto fail;
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}
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2013-03-17 16:31:09 +00:00
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if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
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2015-02-04 16:21:45 +00:00
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NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) {
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2012-10-29 17:23:45 +00:00
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device_printf(dev, "cannot setup interrupt handler\n");
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err = ENXIO;
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goto fail;
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}
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2013-02-28 19:51:30 +00:00
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if (!bcm2835_sdhci_pio_mode)
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sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER;
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2013-02-17 00:23:42 +00:00
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sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180;
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if (bcm2835_sdhci_hs)
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sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD;
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2012-11-30 02:32:37 +00:00
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sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT);
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2012-10-29 17:23:45 +00:00
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sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
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| SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
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2015-01-17 19:57:03 +00:00
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| SDHCI_QUIRK_DONT_SET_HISPD_BIT
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2012-10-29 17:23:45 +00:00
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| SDHCI_QUIRK_MISSING_CAPS;
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sdhci_init_slot(dev, &sc->sc_slot, 0);
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2016-02-16 12:19:06 +00:00
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sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY);
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2013-02-28 19:51:30 +00:00
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if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
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goto fail;
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bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc);
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2013-03-17 16:31:09 +00:00
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/* Allocate bus_dma resources. */
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2013-02-28 19:51:30 +00:00
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err = bus_dma_tag_create(bus_get_dma_tag(dev),
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1, 0, BUS_SPACE_MAXADDR_32BIT,
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BUS_SPACE_MAXADDR, NULL, NULL,
|
2015-01-12 02:42:33 +00:00
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BCM_SDHCI_BUFFER_SIZE, NUM_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE,
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2013-02-28 19:51:30 +00:00
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BUS_DMA_ALLOCNOW, NULL, NULL,
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&sc->sc_dma_tag);
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if (err) {
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device_printf(dev, "failed allocate DMA tag");
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goto fail;
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}
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2013-03-17 16:31:09 +00:00
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err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map);
|
2013-02-28 19:51:30 +00:00
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if (err) {
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2013-03-17 16:31:09 +00:00
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device_printf(dev, "bus_dmamap_create failed\n");
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2013-02-28 19:51:30 +00:00
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goto fail;
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}
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2016-10-13 23:29:24 +00:00
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/* FIXME: Fix along with other BUS_SPACE_PHYSADDR instances */
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sc->sc_sdhci_buffer_phys = rman_get_start(sc->sc_mem_res) +
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SDHCI_BUFFER;
|
2013-02-28 19:51:30 +00:00
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2012-10-29 17:23:45 +00:00
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bus_generic_probe(dev);
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bus_generic_attach(dev);
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sdhci_start_slot(&sc->sc_slot);
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return (0);
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fail:
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if (sc->sc_intrhand)
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bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
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if (sc->sc_irq_res)
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bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
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if (sc->sc_mem_res)
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
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return (err);
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}
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|
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static int
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|
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bcm_sdhci_detach(device_t dev)
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|
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{
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return (EBUSY);
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}
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|
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static void
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|
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bcm_sdhci_intr(void *arg)
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|
|
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{
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|
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struct bcm_sdhci_softc *sc = arg;
|
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|
|
|
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|
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sdhci_generic_intr(&sc->sc_slot);
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|
|
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}
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|
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|
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static int
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|
|
|
bcm_sdhci_get_ro(device_t bus, device_t child)
|
|
|
|
{
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|
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|
|
return (0);
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|
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}
|
|
|
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|
|
static inline uint32_t
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|
|
|
RD4(struct bcm_sdhci_softc *sc, bus_size_t off)
|
|
|
|
{
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|
|
|
uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off);
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|
|
return val;
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|
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}
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|
|
|
|
static inline void
|
|
|
|
WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val)
|
|
|
|
{
|
|
|
|
|
2014-10-18 19:01:07 +00:00
|
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val);
|
|
|
|
/*
|
|
|
|
* The Arasan HC has a bug where it may lose the content of
|
|
|
|
* consecutive writes to registers that are within two SD-card
|
|
|
|
* clock cycles of each other (a clock domain crossing problem).
|
|
|
|
*/
|
|
|
|
if (sc->sc_slot.clock > 0)
|
|
|
|
DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1);
|
2012-10-29 17:23:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static uint8_t
|
|
|
|
bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
|
|
|
|
{
|
|
|
|
struct bcm_sdhci_softc *sc = device_get_softc(dev);
|
|
|
|
uint32_t val = RD4(sc, off & ~3);
|
|
|
|
|
|
|
|
return ((val >> (off & 3)*8) & 0xff);
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint16_t
|
|
|
|
bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
|
|
|
|
{
|
|
|
|
struct bcm_sdhci_softc *sc = device_get_softc(dev);
|
|
|
|
uint32_t val = RD4(sc, off & ~3);
|
|
|
|
|
2015-01-11 17:00:24 +00:00
|
|
|
/*
|
|
|
|
* Standard 32-bit handling of command and transfer mode.
|
|
|
|
*/
|
|
|
|
if (off == SDHCI_TRANSFER_MODE) {
|
|
|
|
return (sc->cmd_and_mode >> 16);
|
|
|
|
} else if (off == SDHCI_COMMAND_FLAGS) {
|
|
|
|
return (sc->cmd_and_mode & 0x0000ffff);
|
|
|
|
}
|
2012-10-29 17:23:45 +00:00
|
|
|
return ((val >> (off & 3)*8) & 0xffff);
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t
|
|
|
|
bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
|
|
|
|
{
|
|
|
|
struct bcm_sdhci_softc *sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
return RD4(sc, off);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
|
|
|
|
uint32_t *data, bus_size_t count)
|
|
|
|
{
|
|
|
|
struct bcm_sdhci_softc *sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
|
|
|
|
{
|
|
|
|
struct bcm_sdhci_softc *sc = device_get_softc(dev);
|
|
|
|
uint32_t val32 = RD4(sc, off & ~3);
|
|
|
|
val32 &= ~(0xff << (off & 3)*8);
|
|
|
|
val32 |= (val << (off & 3)*8);
|
|
|
|
WR4(sc, off & ~3, val32);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
|
|
|
|
{
|
|
|
|
struct bcm_sdhci_softc *sc = device_get_softc(dev);
|
|
|
|
uint32_t val32;
|
|
|
|
if (off == SDHCI_COMMAND_FLAGS)
|
2015-01-11 17:00:24 +00:00
|
|
|
val32 = sc->cmd_and_mode;
|
2012-10-29 17:23:45 +00:00
|
|
|
else
|
|
|
|
val32 = RD4(sc, off & ~3);
|
|
|
|
val32 &= ~(0xffff << (off & 3)*8);
|
|
|
|
val32 |= (val << (off & 3)*8);
|
|
|
|
if (off == SDHCI_TRANSFER_MODE)
|
2015-01-11 17:00:24 +00:00
|
|
|
sc->cmd_and_mode = val32;
|
2015-01-18 20:47:21 +00:00
|
|
|
else {
|
2012-10-29 17:23:45 +00:00
|
|
|
WR4(sc, off & ~3, val32);
|
2015-01-18 20:47:21 +00:00
|
|
|
if (off == SDHCI_COMMAND_FLAGS)
|
|
|
|
sc->cmd_and_mode = val32;
|
|
|
|
}
|
2012-10-29 17:23:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
|
|
|
|
{
|
|
|
|
struct bcm_sdhci_softc *sc = device_get_softc(dev);
|
|
|
|
WR4(sc, off, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
|
|
|
|
uint32_t *data, bus_size_t count)
|
|
|
|
{
|
|
|
|
struct bcm_sdhci_softc *sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
|
|
|
|
}
|
|
|
|
|
2015-01-12 02:42:33 +00:00
|
|
|
static void
|
|
|
|
bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc)
|
|
|
|
{
|
|
|
|
struct sdhci_slot *slot;
|
|
|
|
vm_paddr_t pdst, psrc;
|
|
|
|
int err, idx, len, sync_op;
|
|
|
|
|
|
|
|
slot = &sc->sc_slot;
|
|
|
|
idx = sc->dmamap_seg_index++;
|
|
|
|
len = sc->dmamap_seg_sizes[idx];
|
|
|
|
slot->offset += len;
|
|
|
|
|
|
|
|
if (slot->curcmd->data->flags & MMC_DATA_READ) {
|
|
|
|
bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
|
|
|
|
BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
|
|
|
|
bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
|
|
|
|
BCM_DMA_INC_ADDR,
|
|
|
|
(len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
|
|
|
|
psrc = sc->sc_sdhci_buffer_phys;
|
|
|
|
pdst = sc->dmamap_seg_addrs[idx];
|
|
|
|
sync_op = BUS_DMASYNC_PREREAD;
|
|
|
|
} else {
|
|
|
|
bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
|
|
|
|
BCM_DMA_INC_ADDR,
|
|
|
|
(len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
|
|
|
|
bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
|
|
|
|
BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
|
|
|
|
psrc = sc->dmamap_seg_addrs[idx];
|
|
|
|
pdst = sc->sc_sdhci_buffer_phys;
|
|
|
|
sync_op = BUS_DMASYNC_PREWRITE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* When starting a new DMA operation do the busdma sync operation, and
|
|
|
|
* disable SDCHI data interrrupts because we'll be driven by DMA
|
|
|
|
* interrupts (or SDHCI error interrupts) until the IO is done.
|
|
|
|
*/
|
|
|
|
if (idx == 0) {
|
|
|
|
bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
|
|
|
|
slot->intmask &= ~(SDHCI_INT_DATA_AVAIL |
|
|
|
|
SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END);
|
|
|
|
bcm_sdhci_write_4(sc->sc_dev, &sc->sc_slot, SDHCI_SIGNAL_ENABLE,
|
|
|
|
slot->intmask);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Start the DMA transfer. Only programming errors (like failing to
|
|
|
|
* allocate a channel) cause a non-zero return from bcm_dma_start().
|
|
|
|
*/
|
|
|
|
err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len);
|
|
|
|
KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start"));
|
|
|
|
}
|
|
|
|
|
2013-02-28 19:51:30 +00:00
|
|
|
static void
|
|
|
|
bcm_sdhci_dma_intr(int ch, void *arg)
|
|
|
|
{
|
|
|
|
struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg;
|
|
|
|
struct sdhci_slot *slot = &sc->sc_slot;
|
|
|
|
uint32_t reg, mask;
|
2013-03-17 16:31:09 +00:00
|
|
|
int left, sync_op;
|
2013-02-28 19:51:30 +00:00
|
|
|
|
|
|
|
mtx_lock(&slot->mtx);
|
|
|
|
|
2015-01-12 02:42:33 +00:00
|
|
|
/*
|
|
|
|
* If there are more segments for the current dma, start the next one.
|
|
|
|
* Otherwise unload the dma map and decide what to do next based on the
|
|
|
|
* status of the sdhci controller and whether there's more data left.
|
|
|
|
*/
|
|
|
|
if (sc->dmamap_seg_index < sc->dmamap_seg_count) {
|
|
|
|
bcm_sdhci_start_dma_seg(sc);
|
|
|
|
mtx_unlock(&slot->mtx);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2013-02-28 19:51:30 +00:00
|
|
|
if (slot->curcmd->data->flags & MMC_DATA_READ) {
|
2013-03-17 16:31:09 +00:00
|
|
|
sync_op = BUS_DMASYNC_POSTREAD;
|
2013-02-28 19:51:30 +00:00
|
|
|
mask = SDHCI_INT_DATA_AVAIL;
|
|
|
|
} else {
|
2013-03-17 16:31:09 +00:00
|
|
|
sync_op = BUS_DMASYNC_POSTWRITE;
|
2013-02-28 19:51:30 +00:00
|
|
|
mask = SDHCI_INT_SPACE_AVAIL;
|
|
|
|
}
|
2013-03-17 16:31:09 +00:00
|
|
|
bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
|
|
|
|
bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map);
|
2013-02-28 19:51:30 +00:00
|
|
|
|
2015-01-12 02:42:33 +00:00
|
|
|
sc->dmamap_seg_count = 0;
|
|
|
|
sc->dmamap_seg_index = 0;
|
2013-02-28 19:51:30 +00:00
|
|
|
|
|
|
|
left = min(BCM_SDHCI_BUFFER_SIZE,
|
|
|
|
slot->curcmd->data->len - slot->offset);
|
|
|
|
|
|
|
|
/* DATA END? */
|
|
|
|
reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS);
|
|
|
|
|
|
|
|
if (reg & SDHCI_INT_DATA_END) {
|
|
|
|
/* ACK for all outstanding interrupts */
|
|
|
|
bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg);
|
|
|
|
|
|
|
|
/* enable INT */
|
|
|
|
slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL
|
|
|
|
| SDHCI_INT_DATA_END;
|
|
|
|
bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
|
|
|
|
slot->intmask);
|
|
|
|
|
|
|
|
/* finish this data */
|
|
|
|
sdhci_finish_data(slot);
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
/* already available? */
|
|
|
|
if (reg & mask) {
|
|
|
|
|
|
|
|
/* ACK for DATA_AVAIL or SPACE_AVAIL */
|
|
|
|
bcm_sdhci_write_4(slot->bus, slot,
|
|
|
|
SDHCI_INT_STATUS, mask);
|
|
|
|
|
|
|
|
/* continue next DMA transfer */
|
2015-01-11 21:27:46 +00:00
|
|
|
if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
|
2013-03-17 16:31:09 +00:00
|
|
|
(uint8_t *)slot->curcmd->data->data +
|
2015-01-11 21:27:46 +00:00
|
|
|
slot->offset, left, bcm_sdhci_dmacb, sc,
|
|
|
|
BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) {
|
|
|
|
slot->curcmd->error = MMC_ERR_NO_MEMORY;
|
|
|
|
sdhci_finish_data(slot);
|
2013-02-28 19:51:30 +00:00
|
|
|
} else {
|
2015-01-12 02:42:33 +00:00
|
|
|
bcm_sdhci_start_dma_seg(sc);
|
2013-02-28 19:51:30 +00:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* wait for next data by INT */
|
|
|
|
|
|
|
|
/* enable INT */
|
|
|
|
slot->intmask |= SDHCI_INT_DATA_AVAIL |
|
|
|
|
SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END;
|
|
|
|
bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
|
|
|
|
slot->intmask);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
mtx_unlock(&slot->mtx);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2015-01-11 21:27:46 +00:00
|
|
|
bcm_sdhci_read_dma(device_t dev, struct sdhci_slot *slot)
|
2013-02-28 19:51:30 +00:00
|
|
|
{
|
|
|
|
struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
|
|
|
|
size_t left;
|
|
|
|
|
2015-01-12 02:42:33 +00:00
|
|
|
if (sc->dmamap_seg_count != 0) {
|
2013-02-28 19:51:30 +00:00
|
|
|
device_printf(sc->sc_dev, "DMA in use\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
left = min(BCM_SDHCI_BUFFER_SIZE,
|
|
|
|
slot->curcmd->data->len - slot->offset);
|
|
|
|
|
|
|
|
KASSERT((left & 3) == 0,
|
2016-10-13 23:29:24 +00:00
|
|
|
("%s: len = %zu, not word-aligned", __func__, left));
|
2013-02-28 19:51:30 +00:00
|
|
|
|
2015-01-11 21:27:46 +00:00
|
|
|
if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
|
|
|
|
(uint8_t *)slot->curcmd->data->data + slot->offset, left,
|
|
|
|
bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 ||
|
|
|
|
sc->dmamap_status != 0) {
|
|
|
|
slot->curcmd->error = MMC_ERR_NO_MEMORY;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2013-02-28 19:51:30 +00:00
|
|
|
/* DMA start */
|
2015-01-12 02:42:33 +00:00
|
|
|
bcm_sdhci_start_dma_seg(sc);
|
2013-02-28 19:51:30 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2015-01-11 21:27:46 +00:00
|
|
|
bcm_sdhci_write_dma(device_t dev, struct sdhci_slot *slot)
|
2013-02-28 19:51:30 +00:00
|
|
|
{
|
|
|
|
struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
|
|
|
|
size_t left;
|
|
|
|
|
2015-01-12 02:42:33 +00:00
|
|
|
if (sc->dmamap_seg_count != 0) {
|
2013-02-28 19:51:30 +00:00
|
|
|
device_printf(sc->sc_dev, "DMA in use\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
left = min(BCM_SDHCI_BUFFER_SIZE,
|
|
|
|
slot->curcmd->data->len - slot->offset);
|
|
|
|
|
|
|
|
KASSERT((left & 3) == 0,
|
2016-10-13 23:29:24 +00:00
|
|
|
("%s: len = %zu, not word-aligned", __func__, left));
|
2013-02-28 19:51:30 +00:00
|
|
|
|
2015-01-11 21:27:46 +00:00
|
|
|
if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
|
2013-03-17 16:31:09 +00:00
|
|
|
(uint8_t *)slot->curcmd->data->data + slot->offset, left,
|
2015-01-11 21:27:46 +00:00
|
|
|
bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 ||
|
|
|
|
sc->dmamap_status != 0) {
|
|
|
|
slot->curcmd->error = MMC_ERR_NO_MEMORY;
|
|
|
|
return;
|
|
|
|
}
|
2013-02-28 19:51:30 +00:00
|
|
|
|
|
|
|
/* DMA start */
|
2015-01-12 02:42:33 +00:00
|
|
|
bcm_sdhci_start_dma_seg(sc);
|
2013-02-28 19:51:30 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot)
|
|
|
|
{
|
|
|
|
size_t left;
|
|
|
|
|
2013-03-17 16:31:09 +00:00
|
|
|
/*
|
|
|
|
* Do not use DMA for transfers less than block size or with a length
|
|
|
|
* that is not a multiple of four.
|
|
|
|
*/
|
2013-02-28 19:51:30 +00:00
|
|
|
left = min(BCM_DMA_BLOCK_SIZE,
|
|
|
|
slot->curcmd->data->len - slot->offset);
|
|
|
|
if (left < BCM_DMA_BLOCK_SIZE)
|
|
|
|
return (0);
|
2013-03-17 16:31:09 +00:00
|
|
|
if (left & 0x03)
|
|
|
|
return (0);
|
2013-02-28 19:51:30 +00:00
|
|
|
|
|
|
|
return (1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot,
|
|
|
|
uint32_t *intmask)
|
|
|
|
{
|
|
|
|
|
|
|
|
/* DMA transfer FIFO 1KB */
|
|
|
|
if (slot->curcmd->data->flags & MMC_DATA_READ)
|
2015-01-11 21:27:46 +00:00
|
|
|
bcm_sdhci_read_dma(dev, slot);
|
2013-02-28 19:51:30 +00:00
|
|
|
else
|
2015-01-11 21:27:46 +00:00
|
|
|
bcm_sdhci_write_dma(dev, slot);
|
2013-02-28 19:51:30 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot)
|
|
|
|
{
|
|
|
|
|
|
|
|
sdhci_finish_data(slot);
|
|
|
|
}
|
|
|
|
|
2012-10-29 17:23:45 +00:00
|
|
|
static device_method_t bcm_sdhci_methods[] = {
|
|
|
|
/* Device interface */
|
|
|
|
DEVMETHOD(device_probe, bcm_sdhci_probe),
|
|
|
|
DEVMETHOD(device_attach, bcm_sdhci_attach),
|
|
|
|
DEVMETHOD(device_detach, bcm_sdhci_detach),
|
|
|
|
|
|
|
|
/* Bus interface */
|
|
|
|
DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
|
|
|
|
DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
|
|
|
|
|
|
|
|
/* MMC bridge interface */
|
|
|
|
DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
|
|
|
|
DEVMETHOD(mmcbr_request, sdhci_generic_request),
|
|
|
|
DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro),
|
|
|
|
DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
|
|
|
|
DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
|
|
|
|
|
2013-02-28 19:51:30 +00:00
|
|
|
/* Platform transfer methods */
|
|
|
|
DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer),
|
|
|
|
DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer),
|
|
|
|
DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer),
|
|
|
|
/* SDHCI registers accessors */
|
2012-10-29 17:23:45 +00:00
|
|
|
DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1),
|
|
|
|
DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2),
|
|
|
|
DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4),
|
|
|
|
DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4),
|
|
|
|
DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1),
|
|
|
|
DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2),
|
|
|
|
DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4),
|
|
|
|
DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4),
|
|
|
|
|
2017-03-06 23:47:59 +00:00
|
|
|
DEVMETHOD_END
|
2012-10-29 17:23:45 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static devclass_t bcm_sdhci_devclass;
|
|
|
|
|
|
|
|
static driver_t bcm_sdhci_driver = {
|
|
|
|
"sdhci_bcm",
|
|
|
|
bcm_sdhci_methods,
|
|
|
|
sizeof(struct bcm_sdhci_softc),
|
|
|
|
};
|
|
|
|
|
2017-03-06 23:47:59 +00:00
|
|
|
DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass,
|
|
|
|
NULL, NULL);
|
2012-10-29 17:23:45 +00:00
|
|
|
MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1);
|
2017-09-15 19:47:44 +00:00
|
|
|
#ifndef MMCCAM
|
2017-03-07 22:42:44 +00:00
|
|
|
MMC_DECLARE_BRIDGE(sdhci_bcm);
|
2017-09-15 19:47:44 +00:00
|
|
|
#endif
|