2010-03-20 03:39:35 +00:00
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/* $NetBSD: s3c2410reg.h,v 1.6 2004/02/12 03:52:46 bsh Exp $ */
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/*-
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* Copyright (c) 2003, 2004 Genetec corporation. All rights reserved.
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* Written by Hiroyuki Bessho for Genetec corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of Genetec corporation may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP.
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Samsung S3C2410X processor is ARM920T based integrated CPU
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*
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* Reference:
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2012-06-13 04:59:00 +00:00
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* S3C2410X User's Manual
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2010-03-20 03:39:35 +00:00
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*/
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#ifndef _ARM_S3C2XX0_S3C2410REG_H_
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#define _ARM_S3C2XX0_S3C2410REG_H_
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/* common definitions for S3C2410 and S3C2440 */
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#include <arm/s3c2xx0/s3c24x0reg.h>
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/*
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* Memory Map
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*/
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#define S3C2410_BANK_SIZE 0x08000000
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#define S3C2410_BANK_START(n) (S3C2410_BANK_SIZE*(n))
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#define S3C2410_SDRAM_START S3C2410_BANK_START(6)
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/* interrupt control */
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#define S3C2410_SUBIRQ_MAX (S3C24X0_SUBIRQ_MIN+10)
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/* Clock control */
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/* CLKMAN_CLKCON */
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#define S3C2410_CLKCON_SM (1<<0) /* 1=transition to SPECIAL mode */
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/* CLKMAN_CLKDIVN */
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#define S3C2410_CLKDIVN_HDIVN (1<<1) /* hclk=fclk/2 */
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/* NAND Flash controller */
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#define S3C2410_NANDFC_SIZE 0x18
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/* NANDFC_NFCONF */
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#define S3C2410_NFCONF_ENABLE (1<<15) /* NAND controller enabled */
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#define S3C2410_NFCONF_ECC (1<<12) /* Initialize ECC decoder/encoder */
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#define S3C2410_NFCONF_FCE (1<<11) /* Flash chip enabled */
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#define S3C2410_NFCONF_TACLS (7<<8) /* CLE and ALE duration */
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#define S3C2410_NFCONF_TWRPH0 (7<<4) /* TWRPH0 duration */
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#define S3C2410_NFCONF_TWRPH1 (7<<0) /* TWRPH1 duration */
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#define S3C2410_NANDFC_NFCMD 0x04 /* command */
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#define S3C2410_NANDFC_NFADDR 0x08 /* address */
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#define S3C2410_NANDFC_NFDATA 0x0c /* data */
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#define S3C2410_NANDFC_NFSTAT 0x10 /* operation status */
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#define S3C2410_NANDFC_NFECC 0x14 /* ecc */
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/* MMC/SD */
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/* SDI_CON */
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#define S3C2410_CON_FIFO_RESET (1<<1)
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/* GPIO */
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#define S3C2410_GPIO_SIZE 0xb4
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/* SD interface */
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#define S3C2410_SDI_SIZE 0x44
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#define DCON_STOP (1<<14) /* Force the transfer to stop */
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#define S3C2410_SDI_DAT 0x3c
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#define S3C2410_SDI_IMSK 0x40 /* Interrupt mask */
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#define S3C2410_SDI_IMASK_ALL 0x3ffdf
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/* ADC */
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#define S3C2410_ADC_SIZE 0x14
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#endif /* _ARM_S3C2XX0_S3C2410REG_H_ */
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