284 lines
7.5 KiB
C
284 lines
7.5 KiB
C
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/*
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* Hardware structure definitions for the Adaptec 174X CAM SCSI device driver.
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*
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* Copyright (c) 1998 Justin T. Gibbs
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id$
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*/
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/* Resource Constatns */
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#define AHB_NECB 64
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#define AHB_NSEG 32
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/* AHA1740 EISA ID, IO port range size, and offset from slot base */
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#define EISA_DEVICE_ID_ADAPTEC_1740 0x04900000
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#define AHB_EISA_IOSIZE 0x100
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#define AHB_EISA_SLOT_OFFSET 0xc00
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/* AHA1740 EISA board control registers (Offset from slot base) */
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#define EBCTRL 0x084
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#define CDEN 0x01
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/*
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* AHA1740 EISA board mode registers (Offset from slot base)
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*/
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#define PORTADDR 0x0C0
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#define PORTADDR_ENHANCED 0x80
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#define BIOSADDR 0x0C1
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#define INTDEF 0x0C2
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#define INT9 0x00
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#define INT10 0x01
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#define INT11 0x02
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#define INT12 0x03
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#define INT14 0x05
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#define INT15 0x06
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#define INTLEVEL 0x08
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#define INTEN 0x10
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#define SCSIDEF 0x0C3
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#define HSCSIID 0x0F /* our SCSI ID */
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#define RSTBUS 0x10
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#define BUSDEF 0x0C4
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#define B0uS 0x00 /* give up bus immediatly */
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#define B4uS 0x01 /* delay 4uSec. */
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#define B8uS 0x02 /* delay 8uSec. */
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#define RESV0 0x0C5
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#define RESV1 0x0C6
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#define EXTENDED_TRANS 0x01
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#define RESV2 0x0C7
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/*
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* AHA1740 ENHANCED mode mailbox control regs (Offset from slot base)
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*/
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#define MBOXOUT0 0x0D0
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#define MBOXOUT1 0x0D1
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#define MBOXOUT2 0x0D2
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#define MBOXOUT3 0x0D3
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#define ATTN 0x0D4
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#define ATTN_TARGMASK 0x0F
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#define ATTN_IMMED 0x10
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#define ATTN_STARTECB 0x40
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#define ATTN_ABORTECB 0x50
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#define ATTN_TARG_RESET 0x80
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#define CONTROL 0x0D5
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#define CNTRL_SET_HRDY 0x20
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#define CNTRL_CLRINT 0x40
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#define CNTRL_HARD_RST 0x80
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#define INTSTAT 0x0D6
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#define INTSTAT_TARGET_MASK 0x0F
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#define INTSTAT_MASK 0xF0
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#define INTSTAT_ECB_OK 0x10 /* ECB Completed w/out error */
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#define INTSTAT_ECB_CMPWRETRY 0x50 /* ECB Completed w/retries */
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#define INTSTAT_HW_ERR 0x70 /* Adapter Hardware Failure */
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#define INTSTAT_IMMED_OK 0xA0 /* Immediate command complete */
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#define INTSTAT_ECB_CMPWERR 0xC0 /* ECB Completed w/error */
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#define INTSTAT_AEN_OCCURED 0xD0 /* Async Event Notification */
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#define INTSTAT_IMMED_ERR 0xE0 /* Immediate command failed */
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#define HOSTSTAT 0x0D7
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#define HOSTSTAT_MBOX_EMPTY 0x04
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#define HOSTSTAT_INTPEND 0x02
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#define HOSTSTAT_BUSY 0x01
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#define MBOXIN0 0x0D8
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#define MBOXIN1 0x0D9
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#define MBOXIN2 0x0DA
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#define MBOXIN3 0x0DB
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#define STATUS2 0x0DC
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#define STATUS2_HOST_READY 0x01
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typedef enum {
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IMMED_RESET = 0x000080,
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IMMED_DEVICE_CLEAR_QUEUE = 0x000480,
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IMMED_ADAPTER_CLEAR_QUEUE = 0x000880,
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IMMED_RESUME = 0x200090
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} immed_cmd;
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struct ecb_status {
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/* Status Flags */
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u_int16_t no_error :1, /* Completed with no error */
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data_underrun :1,
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:1,
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ha_queue_full :1,
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spec_check :1,
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data_overrun :1,
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chain_halted :1,
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intr_issued :1,
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status_avail :1, /* status bytes 14-31 are valid */
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sense_stored :1,
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:1,
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init_requied :1,
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major_error :1,
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:1,
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extended_ca :1,
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:1;
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/* Host Status */
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u_int8_t ha_status;
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u_int8_t scsi_status;
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int32_t resid_count;
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u_int32_t resid_addr;
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u_int16_t addit_status;
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u_int8_t sense_len;
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u_int8_t unused[9];
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u_int8_t cdb[6];
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};
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typedef enum {
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HS_OK = 0x00,
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HS_CMD_ABORTED_HOST = 0x04,
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HS_CMD_ABORTED_ADAPTER = 0x05,
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HS_FIRMWARE_LOAD_REQ = 0x08,
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HS_TARGET_NOT_ASSIGNED = 0x0A,
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HS_SEL_TIMEOUT = 0x11,
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HS_DATA_RUN_ERR = 0x12,
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HS_UNEXPECTED_BUSFREE = 0x13,
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HS_INVALID_PHASE = 0x14,
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HS_INVALID_OPCODE = 0x16,
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HS_INVALID_CMD_LINK = 0x17,
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HS_INVALID_ECB_PARAM = 0x18,
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HS_DUP_TCB_RECEIVED = 0x19,
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HS_REQUEST_SENSE_FAILED = 0x1A,
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HS_TAG_MSG_REJECTED = 0x1C,
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HS_HARDWARE_ERR = 0x20,
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HS_ATN_TARGET_FAILED = 0x21,
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HS_SCSI_RESET_ADAPTER = 0x22,
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HS_SCSI_RESET_INCOMING = 0x23,
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HS_PROGRAM_CKSUM_ERROR = 0x80
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} host_status;
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typedef enum {
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ECBOP_NOP = 0x00,
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ECBOP_INITIATOR_SCSI_CMD = 0x01,
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ECBOP_RUN_DIAGNOSTICS = 0x05,
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ECBOP_INITIALIZE_SCSI = 0x06, /* Set syncrate/disc/parity */
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ECBOP_READ_SENSE = 0x08,
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ECBOP_DOWNLOAD_FIRMWARE = 0x09,
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ECBOP_READ_HA_INQDATA = 0x0a,
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ECBOP_TARGET_SCSI_CMD = 0x10
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} ecb_op;
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struct ha_inquiry_data {
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struct scsi_inquiry_data scsi_data;
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u_int8_t release_date[8];
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u_int8_t release_time[8];
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u_int16_t firmware_cksum;
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u_int16_t reserved;
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u_int16_t target_data[16];
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};
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struct hardware_ecb {
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u_int16_t opcode;
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u_int16_t flag_word1;
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#define FW1_LINKED_CMD 0x0001
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#define FW1_DISABLE_INTR 0x0080
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#define FW1_SUPPRESS_URUN_ERR 0x0400
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#define FW1_SG_ECB 0x1000
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#define FW1_ERR_STATUS_BLK_ONLY 0x4000
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#define FW1_AUTO_REQUEST_SENSE 0x8000
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u_int16_t flag_word2;
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#define FW2_LUN_MASK 0x0007
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#define FW2_TAG_ENB 0x0008
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#define FW2_TAG_TYPE 0x0030
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#define FW2_TAG_TYPE_SHIFT 4
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#define FW2_DISABLE_DISC 0x0040
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#define FW2_CHECK_DATA_DIR 0x0100
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#define FW2_DATA_DIR_IN 0x0200
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#define FW2_SUPRESS_TRANSFER 0x0400
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#define FW2_CALC_CKSUM 0x0800
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#define FW2_RECOVERY_ECB 0x4000
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#define FW2_NO_RETRY_ON_BUSY 0x8000
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u_int16_t reserved;
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u_int32_t data_ptr;
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u_int32_t data_len;
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u_int32_t status_ptr;
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u_int32_t link_ptr;
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u_int32_t reserved2;
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u_int32_t sense_ptr;
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u_int8_t sense_len;
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u_int8_t cdb_len;
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u_int16_t cksum;
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u_int8_t cdb[12];
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};
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typedef struct {
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u_int32_t addr;
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u_int32_t len;
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} ahb_sg_t;
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typedef enum {
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ECB_FREE = 0x0,
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ECB_ACTIVE = 0x1,
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ECB_DEVICE_RESET = 0x2,
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ECB_SCSIBUS_RESET = 0x4,
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ECB_RELEASE_SIMQ = 0x8
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} ecb_state;
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struct ecb {
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struct hardware_ecb hecb;
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struct ecb_status status;
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struct scsi_sense_data sense;
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ahb_sg_t sg_list[AHB_NSEG];
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SLIST_ENTRY(ecb) links;
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ecb_state state;
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union ccb *ccb;
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bus_dmamap_t dmamap;
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};
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struct ahb_softc {
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bus_space_tag_t tag;
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bus_space_handle_t bsh;
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struct cam_sim *sim;
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struct cam_path *path;
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SLIST_HEAD(,ecb) free_ecbs;
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LIST_HEAD(,ccb_hdr) pending_ccbs;
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struct ecb *ecb_array;
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u_int32_t ecb_physbase;
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bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
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bus_dma_tag_t ecb_dmat; /* dmat for our ecb array */
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bus_dmamap_t ecb_dmamap;
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volatile u_int32_t immed_cmd;
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struct ecb *immed_ecb;
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struct ha_inquiry_data *ha_inq_data;
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u_int32_t ha_inq_physbase;
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u_long unit;
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u_int init_level;
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u_int scsi_id;
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u_int num_ecbs;
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u_int extended_trans;
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u_int8_t disc_permitted;
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u_int8_t tags_permitted;
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};
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