2005-02-06 15:22:23 +00:00
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/*-
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* Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org>
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2010-01-23 07:54:06 +00:00
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* Copyright (c) 2010 Joerg Wunsch <joerg@FreeBSD.org>
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2005-02-06 15:22:23 +00:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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2012-01-15 13:23:43 +00:00
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* High-level driver for µPD7210 based GPIB cards.
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2005-02-06 15:22:23 +00:00
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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# define GPIB_DEBUG
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# undef GPIB_DEBUG
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/limits.h>
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#include <sys/module.h>
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2005-09-24 20:44:55 +00:00
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#include <sys/rman.h>
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2005-02-06 15:22:23 +00:00
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/uio.h>
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#include <sys/time.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <isa/isavar.h>
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2005-02-12 17:39:50 +00:00
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#define UPD7210_HW_DRIVER
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#define UPD7210_SW_DRIVER
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2005-02-06 15:22:23 +00:00
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#include <dev/ieee488/upd7210.h>
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2010-02-01 21:21:10 +00:00
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#include <dev/ieee488/tnt4882.h>
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2005-02-06 15:22:23 +00:00
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2005-02-10 12:08:55 +00:00
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static MALLOC_DEFINE(M_GPIB, "GPIB", "GPIB");
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2005-02-06 15:22:23 +00:00
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/* upd7210 generic stuff */
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2005-02-12 17:39:50 +00:00
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void
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upd7210_print_isr(u_int isr1, u_int isr2)
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2005-02-06 15:22:23 +00:00
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{
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printf("isr1=0x%b isr2=0x%b",
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isr1, "\20\10CPT\7APT\6DET\5ENDRX\4DEC\3ERR\2DO\1DI",
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isr2, "\20\10INT\7SRQI\6LOK\5REM\4CO\3LOKC\2REMC\1ADSC");
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}
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2005-02-12 17:39:50 +00:00
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u_int
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upd7210_rd(struct upd7210 *u, enum upd7210_rreg reg)
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2005-02-06 15:22:23 +00:00
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{
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u_int r;
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2010-01-23 21:33:33 +00:00
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r = bus_read_1(u->reg_res[reg], u->reg_offset[reg]);
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2005-02-06 15:22:23 +00:00
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u->rreg[reg] = r;
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return (r);
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}
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2005-02-12 17:39:50 +00:00
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void
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upd7210_wr(struct upd7210 *u, enum upd7210_wreg reg, u_int val)
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2005-02-06 15:22:23 +00:00
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{
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2005-09-15 13:07:38 +00:00
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2010-01-23 21:33:33 +00:00
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bus_write_1(u->reg_res[reg], u->reg_offset[reg], val);
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2005-02-06 15:22:23 +00:00
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u->wreg[reg] = val;
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if (reg == AUXMR)
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u->wreg[8 + (val >> 5)] = val & 0x1f;
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}
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void
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upd7210intr(void *arg)
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{
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2010-02-01 21:21:10 +00:00
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u_int isr_1, isr_2, isr_3;
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2005-02-06 15:22:23 +00:00
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struct upd7210 *u;
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u = arg;
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mtx_lock(&u->mutex);
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2010-02-01 21:21:10 +00:00
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isr_1 = upd7210_rd(u, ISR1);
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isr_2 = upd7210_rd(u, ISR2);
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if (u->use_fifo) {
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isr_3 = bus_read_1(u->reg_res[0], isr3);
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} else {
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isr_3 = 0;
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}
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if (isr_1 != 0 || isr_2 != 0 || isr_3 != 0) {
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if (u->busy == 0 || u->irq == NULL || !u->irq(u, isr_3)) {
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2006-03-11 15:39:22 +00:00
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#if 0
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2010-01-23 07:54:06 +00:00
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printf("upd7210intr [%02x %02x %02x",
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upd7210_rd(u, DIR), isr1, isr2);
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printf(" %02x %02x %02x %02x %02x] ",
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upd7210_rd(u, SPSR),
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upd7210_rd(u, ADSR),
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upd7210_rd(u, CPTR),
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upd7210_rd(u, ADR0),
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2005-02-12 17:39:50 +00:00
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upd7210_rd(u, ADR1));
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2010-01-23 07:54:06 +00:00
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upd7210_print_isr(isr1, isr2);
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printf("\n");
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2006-03-11 15:39:22 +00:00
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#endif
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2010-01-23 07:54:06 +00:00
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}
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/*
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* "special interrupt handling"
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*
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* In order to implement shared IRQs, the original
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* PCIIa uses IO locations 0x2f0 + (IRQ#) as an output
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* location. If an ISR for a particular card has
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* detected this card triggered the IRQ, it must reset
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* the card's IRQ by writing (anything) to that IO
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* location.
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*
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* Some clones apparently don't implement this
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* feature, but National Instrument cards do.
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*/
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2010-01-23 21:33:33 +00:00
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if (u->irq_clear_res != NULL)
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bus_write_1(u->irq_clear_res, 0, 42);
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2005-02-06 15:22:23 +00:00
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}
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mtx_unlock(&u->mutex);
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}
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2005-02-12 17:39:50 +00:00
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int
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2005-02-06 15:22:23 +00:00
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upd7210_take_ctrl_async(struct upd7210 *u)
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{
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int i;
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2005-02-12 17:39:50 +00:00
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upd7210_wr(u, AUXMR, AUXMR_TCA);
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2005-02-06 15:22:23 +00:00
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2005-02-12 17:39:50 +00:00
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if (!(upd7210_rd(u, ADSR) & ADSR_ATN))
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2005-02-06 15:22:23 +00:00
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return (0);
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for (i = 0; i < 20; i++) {
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DELAY(1);
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2005-02-12 17:39:50 +00:00
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if (!(upd7210_rd(u, ADSR) & ADSR_ATN))
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2005-02-06 15:22:23 +00:00
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return (0);
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}
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return (1);
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}
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2005-02-12 17:39:50 +00:00
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int
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2005-02-06 15:22:23 +00:00
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upd7210_goto_standby(struct upd7210 *u)
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{
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int i;
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2005-02-12 17:39:50 +00:00
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upd7210_wr(u, AUXMR, AUXMR_GTS);
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2005-02-06 15:22:23 +00:00
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2005-02-12 17:39:50 +00:00
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if (upd7210_rd(u, ADSR) & ADSR_ATN)
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2005-02-06 15:22:23 +00:00
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return (0);
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for (i = 0; i < 20; i++) {
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DELAY(1);
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2005-02-12 17:39:50 +00:00
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if (upd7210_rd(u, ADSR) & ADSR_ATN)
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2005-02-06 15:22:23 +00:00
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return (0);
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}
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return (1);
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}
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/* Unaddressed Listen Only mode */
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static int
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2010-02-01 21:21:10 +00:00
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gpib_l_irq(struct upd7210 *u, int isr_3)
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2005-02-06 15:22:23 +00:00
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{
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int i;
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2010-02-01 21:21:10 +00:00
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int have_data = 0;
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if (u->use_fifo) {
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/* TNT5004 or TNT4882 in FIFO mode */
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if (isr_3 & 0x04) {
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/* FIFO not empty */
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i = bus_read_1(u->reg_res[0], fifob);
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have_data = 1;
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bus_write_1(u->reg_res[0], cnt0, -1);
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bus_write_1(u->reg_res[0], cnt1, (-1) >> 8);
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bus_write_1(u->reg_res[0], cnt2, (-1) >> 16);
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bus_write_1(u->reg_res[0], cnt3, (-1) >> 24);
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bus_write_1(u->reg_res[0], cmdr, 0x04); /* GO */
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}
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} else if (u->rreg[ISR1] & 1) {
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2005-02-12 17:39:50 +00:00
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i = upd7210_rd(u, DIR);
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2010-02-01 21:21:10 +00:00
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have_data = 1;
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}
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if (have_data) {
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2005-02-06 15:22:23 +00:00
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u->buf[u->buf_wp++] = i;
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u->buf_wp &= (u->bufsize - 1);
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i = (u->buf_rp + u->bufsize - u->buf_wp) & (u->bufsize - 1);
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2010-02-01 21:21:10 +00:00
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if (i < 8) {
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if (u->use_fifo)
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bus_write_1(u->reg_res[0], imr3, 0x00);
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else
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upd7210_wr(u, IMR1, 0);
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}
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2005-02-06 15:22:23 +00:00
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wakeup(u->buf);
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return (1);
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}
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return (0);
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}
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static int
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gpib_l_open(struct cdev *dev, int oflags, int devtype, struct thread *td)
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{
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struct upd7210 *u;
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u = dev->si_drv1;
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mtx_lock(&u->mutex);
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2005-04-04 17:37:35 +00:00
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if (u->busy) {
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mtx_unlock(&u->mutex);
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2005-02-06 15:22:23 +00:00
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return (EBUSY);
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2005-04-04 17:37:35 +00:00
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}
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2005-02-06 15:22:23 +00:00
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u->busy = 1;
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u->irq = gpib_l_irq;
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mtx_unlock(&u->mutex);
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u->buf = malloc(PAGE_SIZE, M_GPIB, M_WAITOK);
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u->bufsize = PAGE_SIZE;
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u->buf_wp = 0;
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u->buf_rp = 0;
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2010-02-01 21:21:10 +00:00
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upd7210_wr(u, AUXMR, AUXMR_CRST); /* chip reset */
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2005-02-06 15:22:23 +00:00
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DELAY(10000);
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2010-02-01 21:21:10 +00:00
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upd7210_wr(u, AUXMR, C_ICR | 8); /* 8 MHz clock */
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2005-02-06 15:22:23 +00:00
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DELAY(1000);
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2010-02-01 21:21:10 +00:00
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upd7210_wr(u, ADR, 0x60); /* ADR0: disable listener and talker 0 */
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upd7210_wr(u, ADR, 0xe0); /* ADR1: disable listener and talker 1 */
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upd7210_wr(u, ADMR, 0x70); /* listen-only (lon) */
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upd7210_wr(u, AUXMR, AUXMR_PON); /* immediate execute power-on (pon) */
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if (u->use_fifo) {
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/* TNT5004 or TNT4882 in FIFO mode */
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bus_write_1(u->reg_res[0], cmdr, 0x10); /* reset FIFO */
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bus_write_1(u->reg_res[0], cfg, 0x20); /* xfer IN, 8-bit FIFO */
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bus_write_1(u->reg_res[0], cnt0, -1);
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bus_write_1(u->reg_res[0], cnt1, (-1) >> 8);
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bus_write_1(u->reg_res[0], cnt2, (-1) >> 16);
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bus_write_1(u->reg_res[0], cnt3, (-1) >> 24);
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bus_write_1(u->reg_res[0], cmdr, 0x04); /* GO */
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bus_write_1(u->reg_res[0], imr3, 0x04); /* NEF IE */
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} else {
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2012-01-15 13:23:43 +00:00
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/* µPD7210/NAT7210, or TNT4882 in non-FIFO mode */
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2010-02-01 21:21:10 +00:00
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upd7210_wr(u, IMR1, 0x01); /* data in interrupt enable */
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}
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2005-02-06 15:22:23 +00:00
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return (0);
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}
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static int
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gpib_l_close(struct cdev *dev, int oflags, int devtype, struct thread *td)
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{
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struct upd7210 *u;
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u = dev->si_drv1;
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mtx_lock(&u->mutex);
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u->busy = 0;
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2010-02-01 21:21:10 +00:00
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if (u->use_fifo) {
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/* TNT5004 or TNT4882 in FIFO mode */
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bus_write_1(u->reg_res[0], cmdr, 0x22); /* soft RESET */
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bus_write_1(u->reg_res[0], imr3, 0x00);
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}
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2005-02-12 17:39:50 +00:00
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upd7210_wr(u, AUXMR, AUXMR_CRST);
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2005-02-06 15:22:23 +00:00
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DELAY(10000);
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2005-02-12 17:39:50 +00:00
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upd7210_wr(u, IMR1, 0x00);
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upd7210_wr(u, IMR2, 0x00);
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2005-02-06 15:22:23 +00:00
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free(u->buf, M_GPIB);
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u->buf = NULL;
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mtx_unlock(&u->mutex);
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return (0);
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}
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static int
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gpib_l_read(struct cdev *dev, struct uio *uio, int ioflag)
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{
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struct upd7210 *u;
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int error;
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size_t z;
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u = dev->si_drv1;
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error = 0;
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mtx_lock(&u->mutex);
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while (u->buf_wp == u->buf_rp) {
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|
|
error = msleep(u->buf, &u->mutex, PZERO | PCATCH,
|
|
|
|
"gpibrd", hz);
|
|
|
|
if (error && error != EWOULDBLOCK) {
|
|
|
|
mtx_unlock(&u->mutex);
|
|
|
|
return (error);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
while (uio->uio_resid > 0 && u->buf_wp != u->buf_rp) {
|
|
|
|
if (u->buf_wp < u->buf_rp)
|
|
|
|
z = u->bufsize - u->buf_rp;
|
|
|
|
else
|
|
|
|
z = u->buf_wp - u->buf_rp;
|
|
|
|
if (z > uio->uio_resid)
|
|
|
|
z = uio->uio_resid;
|
|
|
|
mtx_unlock(&u->mutex);
|
|
|
|
error = uiomove(u->buf + u->buf_rp, z, uio);
|
|
|
|
mtx_lock(&u->mutex);
|
|
|
|
if (error)
|
|
|
|
break;
|
|
|
|
u->buf_rp += z;
|
|
|
|
u->buf_rp &= (u->bufsize - 1);
|
|
|
|
}
|
2010-02-01 21:21:10 +00:00
|
|
|
if (u->use_fifo) {
|
|
|
|
bus_write_1(u->reg_res[0], imr3, 0x04); /* NFF IE */
|
|
|
|
} else {
|
|
|
|
if (u->wreg[IMR1] == 0)
|
|
|
|
upd7210_wr(u, IMR1, 0x01);
|
|
|
|
}
|
2005-02-06 15:22:23 +00:00
|
|
|
mtx_unlock(&u->mutex);
|
|
|
|
return (error);
|
|
|
|
}
|
|
|
|
|
2005-02-10 12:08:55 +00:00
|
|
|
static struct cdevsw gpib_l_cdevsw = {
|
2005-02-06 15:22:23 +00:00
|
|
|
.d_version = D_VERSION,
|
|
|
|
.d_name = "gpib_l",
|
|
|
|
.d_open = gpib_l_open,
|
|
|
|
.d_close = gpib_l_close,
|
|
|
|
.d_read = gpib_l_read,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Housekeeping */
|
|
|
|
|
2005-09-15 13:07:38 +00:00
|
|
|
static struct unrhdr *units;
|
|
|
|
|
2005-02-06 15:22:23 +00:00
|
|
|
void
|
|
|
|
upd7210attach(struct upd7210 *u)
|
|
|
|
{
|
|
|
|
struct cdev *dev;
|
|
|
|
|
2005-09-15 13:07:38 +00:00
|
|
|
if (units == NULL)
|
2008-05-29 12:50:46 +00:00
|
|
|
units = new_unrhdr(0, INT_MAX, NULL);
|
2005-09-15 13:07:38 +00:00
|
|
|
u->unit = alloc_unr(units);
|
2005-02-06 15:22:23 +00:00
|
|
|
mtx_init(&u->mutex, "gpib", NULL, MTX_DEF);
|
2005-09-15 13:07:38 +00:00
|
|
|
u->cdev = make_dev(&gpib_l_cdevsw, u->unit,
|
2005-02-06 15:22:23 +00:00
|
|
|
UID_ROOT, GID_WHEEL, 0444,
|
2005-09-15 13:07:38 +00:00
|
|
|
"gpib%ul", u->unit);
|
2005-02-06 15:22:23 +00:00
|
|
|
u->cdev->si_drv1 = u;
|
|
|
|
|
2005-09-15 13:07:38 +00:00
|
|
|
dev = make_dev(&gpib_ib_cdevsw, u->unit,
|
2005-02-06 15:22:23 +00:00
|
|
|
UID_ROOT, GID_WHEEL, 0444,
|
2005-09-15 13:07:38 +00:00
|
|
|
"gpib%uib", u->unit);
|
2005-02-06 15:22:23 +00:00
|
|
|
dev->si_drv1 = u;
|
|
|
|
dev_depends(u->cdev, dev);
|
|
|
|
}
|
2005-09-15 13:07:38 +00:00
|
|
|
|
|
|
|
void
|
|
|
|
upd7210detach(struct upd7210 *u)
|
|
|
|
{
|
|
|
|
|
|
|
|
destroy_dev(u->cdev);
|
|
|
|
mtx_destroy(&u->mutex);
|
|
|
|
free_unr(units, u->unit);
|
|
|
|
}
|