2004-05-14 11:46:45 +00:00
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/* $FreeBSD$ */
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#ifndef _MACHINE_SMP_H_
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#define _MACHINE_SMP_H_
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2012-08-15 03:03:03 +00:00
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#include <sys/_cpuset.h>
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2013-07-29 12:55:37 +00:00
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#include <machine/pcb.h>
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2012-08-15 03:03:03 +00:00
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Import ARM_INTRNG, the "next generation" interrupt architecture for arm
and armv6 architecures. The primary enhancement over the old design is
support for hierarchical interrupt controllers (such as a gpio driver
which can receive interrupts from a root PIC and act as a PIC itself for
clients interested in handling a change of gpio pin state as an
interrupt). The new code also provides an infrastructure for mapping
interrupts described in metadata in the form of a "controller reference
plus interrupt number" tuple into the simple "0-n" flat numeric space
understood by rman and the bus resource mechanisms.
Use of the new code is enabled by setting the ARM_INTRNG option, and by
making a few simple changes to the platform's support code. In addition
each existing PIC driver needs changes to be ready for INTRNG; this commit
contains the changes for the arm/gic driver, which most armv6 SoCs use, but
it does not enable the new code yet on any platform.
This project has been many years in the making, starting as a GSoC project
by Jakub Klama (jceel@) in 2012. That didn't get committed right away and
the source base evolved out from under it to some degree. In 2014 I rebased
the diffs to then -current and did some enhancements in the area of mapping
interrupt numbers and storing associated fdt data, then the project went
cold again for a while. Eventually Svata Kraus took that work in progress
and did another big round of work on it, removing most of the remaining
rough edges. Finally I took that and made one more pass through it, mostly
disabling the "INTR_SOLO" feature for now, pending further design
discussions on how to most efficiently dispatch a pending interrupt through
more than one layer of PIC. The current code with the INTR_SOLO feature
disabled uses approximate 100 extra cpu cycles for each cascaded PIC the
interrupt has to be passed to, so what's left to do is about efficiency, not
correct operation.
Differential Revision: https://reviews.freebsd.org/D2047
2015-10-18 18:26:19 +00:00
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enum {
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IPI_AST,
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IPI_PREEMPT,
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IPI_RENDEZVOUS,
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IPI_STOP,
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IPI_STOP_HARD = IPI_STOP, /* These are synonyms on arm. */
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IPI_HARDCLOCK,
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2016-01-30 13:11:13 +00:00
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IPI_TLB, /* Not used now, but keep it reserved. */
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IPI_CACHE, /* Not used now, but keep it reserved. */
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2015-12-18 05:43:59 +00:00
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INTR_IPI_COUNT
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Import ARM_INTRNG, the "next generation" interrupt architecture for arm
and armv6 architecures. The primary enhancement over the old design is
support for hierarchical interrupt controllers (such as a gpio driver
which can receive interrupts from a root PIC and act as a PIC itself for
clients interested in handling a change of gpio pin state as an
interrupt). The new code also provides an infrastructure for mapping
interrupts described in metadata in the form of a "controller reference
plus interrupt number" tuple into the simple "0-n" flat numeric space
understood by rman and the bus resource mechanisms.
Use of the new code is enabled by setting the ARM_INTRNG option, and by
making a few simple changes to the platform's support code. In addition
each existing PIC driver needs changes to be ready for INTRNG; this commit
contains the changes for the arm/gic driver, which most armv6 SoCs use, but
it does not enable the new code yet on any platform.
This project has been many years in the making, starting as a GSoC project
by Jakub Klama (jceel@) in 2012. That didn't get committed right away and
the source base evolved out from under it to some degree. In 2014 I rebased
the diffs to then -current and did some enhancements in the area of mapping
interrupt numbers and storing associated fdt data, then the project went
cold again for a while. Eventually Svata Kraus took that work in progress
and did another big round of work on it, removing most of the remaining
rough edges. Finally I took that and made one more pass through it, mostly
disabling the "INTR_SOLO" feature for now, pending further design
discussions on how to most efficiently dispatch a pending interrupt through
more than one layer of PIC. The current code with the INTR_SOLO feature
disabled uses approximate 100 extra cpu cycles for each cascaded PIC the
interrupt has to be passed to, so what's left to do is about efficiency, not
correct operation.
Differential Revision: https://reviews.freebsd.org/D2047
2015-10-18 18:26:19 +00:00
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};
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2012-08-15 03:03:03 +00:00
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void init_secondary(int cpu);
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2014-02-23 22:35:18 +00:00
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void mpentry(void);
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2012-08-15 03:03:03 +00:00
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void ipi_all_but_self(u_int ipi);
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void ipi_cpu(int cpu, u_int ipi);
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void ipi_selected(cpuset_t cpus, u_int ipi);
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/* Platform interface */
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void platform_mp_setmaxid(void);
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void platform_mp_start_ap(void);
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2013-07-29 08:07:35 +00:00
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/* global data in mp_machdep.c */
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extern struct pcb stoppcbs[];
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2004-05-14 11:46:45 +00:00
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#endif /* !_MACHINE_SMP_H_ */
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