2000-05-01 20:32:07 +00:00
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/* $FreeBSD$ */
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1996-10-08 21:08:18 +00:00
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static int gpib_port=0x2c0;
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1995-05-30 08:16:23 +00:00
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#define IEEE gpib_port
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1994-12-17 08:07:03 +00:00
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/*NAT4882 Registers*/
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#define DIR IEEE+0
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#define CDOR IEEE+0
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#define ISR1 IEEE+2
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#define IMR1 IEEE+2
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#define ISR2 IEEE+4
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#define IMR2 IEEE+4
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#define SPSR IEEE+6
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#define KSR IEEE+0x17
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#define KCR IEEE+0x17
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#define SPMR IEEE+6
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#define ADSR IEEE+8
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#define ADMR IEEE+8
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#define CPTR IEEE+0x0A
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#define SASR IEEE+0x1B
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#define AUXMR IEEE+0x0A
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#define ADR0 IEEE+0x0c
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#define ISR0 IEEE+0x1d
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#define IMR0 IEEE+0x1d
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#define ADR IEEE+0x0c
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#define ADR1 IEEE+0x0e
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#define BSR IEEE+0x1f
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#define BCR IEEE+0x1f
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#define EOSR IEEE+0x0e
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/*Turbo 488 Registers*/
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#define CNT2 IEEE+0x09
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#define CNT3 IEEE+0x0b
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#define HSSEL IEEE+0x0d
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#define STS1 IEEE+0x10
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#define CFG IEEE+0x10
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#define IMR3 IEEE+0x12
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#define CNT0 IEEE+0x14
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#define CNT1 IEEE+0x16
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#define FIFOB IEEE+0x18
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#define FIFOA IEEE+0x19
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#define ISR3 IEEE+0x1a
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#define CCRG IEEE+0x1a
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#define STS2 IEEE+0x1c
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#define CMDR IEEE+0x1c
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#define TIMER IEEE+0x1e
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#define ACCWR IEEE+0x05
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#define INTR IEEE+0x07
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#define pon 0
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#define chip_reset 2
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#define rhdf 3
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#define trig 4
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#define rtl_pulse 5
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#define rtl_off 5
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#define rtl_on 0x0d
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#define seoi 6
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#define ist_off 1
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#define ist_on 9
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#define rlc 0x0a
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#define rqc 8
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#define lut 0x0b
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#define lul 0x0c
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#define nbaf 0x0e
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#define gts 0x10
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#define tca 0x11
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#define tcs 0x12
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#define tcse 0x1a
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#define ltn 0x13
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#define ltn_cont 0x1b
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#define lun 0x1c
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#define rsc_off 0x14
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#define sic_rsc 0x1e
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#define sic_rsc_off 0x16
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#define sre_rsc 0x1f
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#define sre_rsc_off 0x17
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#define reqt 0x18
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#define reqf 0x19
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#define rppl 0x1d
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#define hldi 0x51
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