272 lines
8.9 KiB
C
272 lines
8.9 KiB
C
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/* SPDX-License-Identifier: BSD-2-Clause AND BSD-3-Clause */
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/*
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* Copyright (c) 2020 Rubicon Communications, LLC (Netgate)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Copyright(c) 2014 - 2020 Intel Corporation.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include "qatreg.h"
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#include "qatvar.h"
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#include "qat_hw17reg.h"
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#include "qat_hw17var.h"
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#include "qat_dh895xccreg.h"
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static uint32_t
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qat_dh895xcc_get_accel_mask(struct qat_softc *sc)
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{
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uint32_t fusectl, strap;
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fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
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strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_DH895XCC, 4);
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return (((~(fusectl | strap)) >> ACCEL_REG_OFFSET_DH895XCC) &
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ACCEL_MASK_DH895XCC);
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}
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static uint32_t
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qat_dh895xcc_get_ae_mask(struct qat_softc *sc)
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{
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uint32_t fusectl, strap;
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fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
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strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_DH895XCC, 4);
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return (~(fusectl | strap)) & AE_MASK_DH895XCC;
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}
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static enum qat_sku
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qat_dh895xcc_get_sku(struct qat_softc *sc)
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{
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uint32_t fusectl, sku;
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fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
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sku = (fusectl & FUSECTL_SKU_MASK_DH895XCC) >>
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FUSECTL_SKU_SHIFT_DH895XCC;
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switch (sku) {
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case FUSECTL_SKU_1_DH895XCC:
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return QAT_SKU_1;
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case FUSECTL_SKU_2_DH895XCC:
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return QAT_SKU_2;
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case FUSECTL_SKU_3_DH895XCC:
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return QAT_SKU_3;
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case FUSECTL_SKU_4_DH895XCC:
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return QAT_SKU_4;
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default:
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return QAT_SKU_UNKNOWN;
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}
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}
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static uint32_t
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qat_dh895xcc_get_accel_cap(struct qat_softc *sc)
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{
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uint32_t cap, legfuse;
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legfuse = pci_read_config(sc->sc_dev, LEGFUSE_REG, 4);
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cap = QAT_ACCEL_CAP_CRYPTO_SYMMETRIC +
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QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC +
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QAT_ACCEL_CAP_CIPHER +
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QAT_ACCEL_CAP_AUTHENTICATION +
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QAT_ACCEL_CAP_COMPRESSION +
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QAT_ACCEL_CAP_ZUC +
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QAT_ACCEL_CAP_SHA3;
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if (legfuse & LEGFUSE_ACCEL_MASK_CIPHER_SLICE) {
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cap &= ~QAT_ACCEL_CAP_CRYPTO_SYMMETRIC;
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cap &= ~QAT_ACCEL_CAP_CIPHER;
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}
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if (legfuse & LEGFUSE_ACCEL_MASK_AUTH_SLICE)
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cap &= ~QAT_ACCEL_CAP_AUTHENTICATION;
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if (legfuse & LEGFUSE_ACCEL_MASK_PKE_SLICE)
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cap &= ~QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC;
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if (legfuse & LEGFUSE_ACCEL_MASK_COMPRESS_SLICE)
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cap &= ~QAT_ACCEL_CAP_COMPRESSION;
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if (legfuse & LEGFUSE_ACCEL_MASK_EIA3_SLICE)
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cap &= ~QAT_ACCEL_CAP_ZUC;
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return cap;
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}
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static const char *
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qat_dh895xcc_get_fw_uof_name(struct qat_softc *sc)
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{
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return AE_FW_UOF_NAME_DH895XCC;
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}
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static void
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qat_dh895xcc_enable_intr(struct qat_softc *sc)
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{
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/* Enable bundle and misc interrupts */
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qat_misc_write_4(sc, SMIAPF0_DH895XCC, SMIA0_MASK_DH895XCC);
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qat_misc_write_4(sc, SMIAPF1_DH895XCC, SMIA1_MASK_DH895XCC);
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}
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/* Worker thread to service arbiter mappings based on dev SKUs */
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static uint32_t thrd_to_arb_map_sku4[] = {
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0x12222AAA, 0x11666666, 0x12222AAA, 0x11666666,
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0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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};
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static uint32_t thrd_to_arb_map_sku6[] = {
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0x12222AAA, 0x11666666, 0x12222AAA, 0x11666666,
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0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222,
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0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222,
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};
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static void
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qat_dh895xcc_get_arb_mapping(struct qat_softc *sc,
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const uint32_t **arb_map_config)
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{
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uint32_t *map, sku;
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int i;
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sku = qat_dh895xcc_get_sku(sc);
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switch (sku) {
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case QAT_SKU_1:
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map = thrd_to_arb_map_sku4;
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break;
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case QAT_SKU_2:
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case QAT_SKU_4:
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map = thrd_to_arb_map_sku6;
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break;
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default:
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*arb_map_config = NULL;
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return;
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}
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for (i = 1; i < MAX_AE_DH895XCC; i++) {
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if ((~sc->sc_ae_mask) & (1 << i))
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map[i] = 0;
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}
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*arb_map_config = map;
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}
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static void
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qat_dh895xcc_enable_error_correction(struct qat_softc *sc)
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{
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uint32_t mask;
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u_int i;
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/* Enable Accel Engine error detection & correction */
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for (i = 0, mask = sc->sc_ae_mask; mask; i++, mask >>= 1) {
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if (!(mask & 1))
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continue;
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qat_misc_read_write_or_4(sc, AE_CTX_ENABLES_DH895XCC(i),
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ENABLE_AE_ECC_ERR_DH895XCC);
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qat_misc_read_write_or_4(sc, AE_MISC_CONTROL_DH895XCC(i),
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ENABLE_AE_ECC_PARITY_CORR_DH895XCC);
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}
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/* Enable shared memory error detection & correction */
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for (i = 0, mask = sc->sc_accel_mask; mask; i++, mask >>= 1) {
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if (!(mask & 1))
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continue;
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qat_misc_read_write_or_4(sc, UERRSSMSH(i), ERRSSMSH_EN_DH895XCC);
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qat_misc_read_write_or_4(sc, CERRSSMSH(i), ERRSSMSH_EN_DH895XCC);
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qat_misc_read_write_or_4(sc, PPERR(i), PPERR_EN_DH895XCC);
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}
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}
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const struct qat_hw qat_hw_dh895xcc = {
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.qhw_sram_bar_id = BAR_SRAM_ID_DH895XCC,
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.qhw_misc_bar_id = BAR_PMISC_ID_DH895XCC,
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.qhw_etr_bar_id = BAR_ETR_ID_DH895XCC,
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.qhw_cap_global_offset = CAP_GLOBAL_OFFSET_DH895XCC,
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.qhw_ae_offset = AE_OFFSET_DH895XCC,
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.qhw_ae_local_offset = AE_LOCAL_OFFSET_DH895XCC,
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.qhw_etr_bundle_size = ETR_BUNDLE_SIZE_DH895XCC,
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.qhw_num_banks = ETR_MAX_BANKS_DH895XCC,
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.qhw_num_rings_per_bank = ETR_MAX_RINGS_PER_BANK,
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.qhw_num_accel = MAX_ACCEL_DH895XCC,
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.qhw_num_engines = MAX_AE_DH895XCC,
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.qhw_tx_rx_gap = ETR_TX_RX_GAP_DH895XCC,
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.qhw_tx_rings_mask = ETR_TX_RINGS_MASK_DH895XCC,
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.qhw_clock_per_sec = CLOCK_PER_SEC_DH895XCC,
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.qhw_fw_auth = false,
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.qhw_fw_req_size = FW_REQ_DEFAULT_SZ_HW17,
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.qhw_fw_resp_size = FW_RESP_DEFAULT_SZ_HW17,
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.qhw_ring_asym_tx = 0,
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.qhw_ring_asym_rx = 8,
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.qhw_ring_sym_tx = 2,
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.qhw_ring_sym_rx = 10,
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.qhw_mof_fwname = AE_FW_MOF_NAME_DH895XCC,
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.qhw_mmp_fwname = AE_FW_MMP_NAME_DH895XCC,
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.qhw_prod_type = AE_FW_PROD_TYPE_DH895XCC,
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.qhw_get_accel_mask = qat_dh895xcc_get_accel_mask,
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.qhw_get_ae_mask = qat_dh895xcc_get_ae_mask,
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.qhw_get_sku = qat_dh895xcc_get_sku,
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.qhw_get_accel_cap = qat_dh895xcc_get_accel_cap,
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.qhw_get_fw_uof_name = qat_dh895xcc_get_fw_uof_name,
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.qhw_enable_intr = qat_dh895xcc_enable_intr,
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.qhw_init_admin_comms = qat_adm_mailbox_init,
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.qhw_send_admin_init = qat_adm_mailbox_send_init,
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.qhw_init_arb = qat_arb_init,
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.qhw_get_arb_mapping = qat_dh895xcc_get_arb_mapping,
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.qhw_enable_error_correction = qat_dh895xcc_enable_error_correction,
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.qhw_check_slice_hang = qat_check_slice_hang,
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.qhw_crypto_setup_desc = qat_hw17_crypto_setup_desc,
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.qhw_crypto_setup_req_params = qat_hw17_crypto_setup_req_params,
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.qhw_crypto_opaque_offset = offsetof(struct fw_la_resp, opaque_data),
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};
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