2014-05-08 18:36:42 +00:00
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/*-
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* Copyright 2011 Semihalf
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <machine/asm.h>
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#include <machine/armreg.h>
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__FBSDID("$FreeBSD$");
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ASENTRY_NP(mptramp)
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0
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mrs r3, cpsr
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bic r3, r3, #(PSR_MODE)
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orr r3, r3, #(PSR_SVC32_MODE)
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msr cpsr_fsxc, r3
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mrc p15, 0, r0, c0, c0, 5
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and r0, #0x0f /* Get CPU ID */
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/* Read boot address for CPU */
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mov r1, #0x100
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mul r2, r0, r1
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ldr r1, Lpmureg
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add r0, r2, r1
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ldr r1, [r0], #0x00
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mov pc, r1
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Lpmureg:
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.word 0xd0022124
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END(mptramp)
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2014-06-05 21:35:10 +00:00
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.global _C_LABEL(mptramp_end)
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_C_LABEL(mptramp_end):
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