freebsd-dev/lib/CodeGen/RegisterScavenging.cpp

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//===-- RegisterScavenging.cpp - Machine register scavenging --------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file implements the machine register scavenger. It can provide
// information, such as unused registers, at any point in a machine basic block.
// It also provides a mechanism to make registers available by evicting them to
// spill slots.
//
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "reg-scavenging"
#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/STLExtras.h"
using namespace llvm;
/// setUsed - Set the register and its sub-registers as being used.
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void RegScavenger::setUsed(unsigned Reg) {
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RegsAvailable.reset(Reg);
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs)
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RegsAvailable.reset(SubReg);
}
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bool RegScavenger::isAliasUsed(unsigned Reg) const {
if (isUsed(Reg))
return true;
for (const unsigned *R = TRI->getAliasSet(Reg); *R; ++R)
if (isUsed(*R))
return true;
return false;
}
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void RegScavenger::initRegState() {
ScavengedReg = 0;
ScavengedRC = NULL;
ScavengeRestore = NULL;
// All registers started out unused.
RegsAvailable.set();
// Reserved registers are always used.
RegsAvailable ^= ReservedRegs;
if (!MBB)
return;
// Live-in registers are in use.
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for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
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E = MBB->livein_end(); I != E; ++I)
setUsed(*I);
// Pristine CSRs are also unavailable.
BitVector PR = MBB->getParent()->getFrameInfo()->getPristineRegs(MBB);
for (int I = PR.find_first(); I>0; I = PR.find_next(I))
setUsed(I);
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}
void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
MachineFunction &MF = *mbb->getParent();
const TargetMachine &TM = MF.getTarget();
TII = TM.getInstrInfo();
TRI = TM.getRegisterInfo();
MRI = &MF.getRegInfo();
assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
"Target changed?");
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// Self-initialize.
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if (!MBB) {
NumPhysRegs = TRI->getNumRegs();
RegsAvailable.resize(NumPhysRegs);
// Create reserved registers bitvector.
ReservedRegs = TRI->getReservedRegs(MF);
// Create callee-saved registers bitvector.
CalleeSavedRegs.resize(NumPhysRegs);
const unsigned *CSRegs = TRI->getCalleeSavedRegs();
if (CSRegs != NULL)
for (unsigned i = 0; CSRegs[i]; ++i)
CalleeSavedRegs.set(CSRegs[i]);
}
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MBB = mbb;
initRegState();
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Tracking = false;
}
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void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) {
BV.set(Reg);
for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
BV.set(*R);
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}
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void RegScavenger::addRegWithAliases(BitVector &BV, unsigned Reg) {
BV.set(Reg);
for (const unsigned *R = TRI->getAliasSet(Reg); *R; R++)
BV.set(*R);
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}
void RegScavenger::forward() {
// Move ptr forward.
if (!Tracking) {
MBBI = MBB->begin();
Tracking = true;
} else {
assert(MBBI != MBB->end() && "Already at the end of the basic block!");
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MBBI = llvm::next(MBBI);
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}
MachineInstr *MI = MBBI;
if (MI == ScavengeRestore) {
ScavengedReg = 0;
ScavengedRC = NULL;
ScavengeRestore = NULL;
}
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if (MI->isDebugValue())
return;
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// Find out which registers are early clobbered, killed, defined, and marked
// def-dead in this instruction.
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// FIXME: The scavenger is not predication aware. If the instruction is
// predicated, conservatively assume "kill" markers do not actually kill the
// register. Similarly ignores "dead" markers.
bool isPred = TII->isPredicated(MI);
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BitVector EarlyClobberRegs(NumPhysRegs);
BitVector KillRegs(NumPhysRegs);
BitVector DefRegs(NumPhysRegs);
BitVector DeadRegs(NumPhysRegs);
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || MO.isUndef())
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continue;
unsigned Reg = MO.getReg();
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if (!Reg || isReserved(Reg))
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continue;
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if (MO.isUse()) {
// Two-address operands implicitly kill.
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if (!isPred && (MO.isKill() || MI->isRegTiedToDefOperand(i)))
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addRegWithSubRegs(KillRegs, Reg);
} else {
assert(MO.isDef());
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if (!isPred && MO.isDead())
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addRegWithSubRegs(DeadRegs, Reg);
else
addRegWithSubRegs(DefRegs, Reg);
if (MO.isEarlyClobber())
addRegWithAliases(EarlyClobberRegs, Reg);
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}
}
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// Verify uses and defs.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || MO.isUndef())
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continue;
unsigned Reg = MO.getReg();
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if (!Reg || isReserved(Reg))
continue;
if (MO.isUse()) {
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if (!isUsed(Reg)) {
// Check if it's partial live: e.g.
// D0 = insert_subreg D0<undef>, S0
// ... D0
// The problem is the insert_subreg could be eliminated. The use of
// D0 is using a partially undef value. This is not *incorrect* since
// S1 is can be freely clobbered.
// Ideally we would like a way to model this, but leaving the
// insert_subreg around causes both correctness and performance issues.
bool SubUsed = false;
for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
unsigned SubReg = *SubRegs; ++SubRegs)
if (isUsed(SubReg)) {
SubUsed = true;
break;
}
assert(SubUsed && "Using an undefined register!");
}
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assert((!EarlyClobberRegs.test(Reg) || MI->isRegTiedToDefOperand(i)) &&
"Using an early clobbered register!");
} else {
assert(MO.isDef());
#if 0
// FIXME: Enable this once we've figured out how to correctly transfer
// implicit kills during codegen passes like the coalescer.
assert((KillRegs.test(Reg) || isUnused(Reg) ||
isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
"Re-defining a live register!");
#endif
}
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}
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// Commit the changes.
setUnused(KillRegs);
setUnused(DeadRegs);
setUsed(DefRegs);
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}
void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
if (includeReserved)
used = ~RegsAvailable;
else
used = ~RegsAvailable & ~ReservedRegs;
}
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unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
I != E; ++I)
if (!isAliasUsed(*I)) {
DEBUG(dbgs() << "Scavenger found unused reg: " << TRI->getName(*I) <<
"\n");
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return *I;
}
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return 0;
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}
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/// getRegsAvailable - Return all available registers in the register class
/// in Mask.
void RegScavenger::getRegsAvailable(const TargetRegisterClass *RC,
BitVector &Mask) {
for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
I != E; ++I)
if (!isAliasUsed(*I))
Mask.set(*I);
}
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/// findSurvivorReg - Return the candidate register that is unused for the
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/// longest after StargMII. UseMI is set to the instruction where the search
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/// stopped.
///
/// No more than InstrLimit instructions are inspected.
///
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unsigned RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI,
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BitVector &Candidates,
unsigned InstrLimit,
MachineBasicBlock::iterator &UseMI) {
int Survivor = Candidates.find_first();
assert(Survivor > 0 && "No candidates for scavenging");
MachineBasicBlock::iterator ME = MBB->getFirstTerminator();
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assert(StartMI != ME && "MI already at terminator");
MachineBasicBlock::iterator RestorePointMI = StartMI;
MachineBasicBlock::iterator MI = StartMI;
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bool inVirtLiveRange = false;
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for (++MI; InstrLimit > 0 && MI != ME; ++MI, --InstrLimit) {
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if (MI->isDebugValue()) {
++InstrLimit; // Don't count debug instructions
continue;
}
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bool isVirtKillInsn = false;
bool isVirtDefInsn = false;
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// Remove any candidates touched by instruction.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || MO.isUndef() || !MO.getReg())
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continue;
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if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
if (MO.isDef())
isVirtDefInsn = true;
else if (MO.isKill())
isVirtKillInsn = true;
continue;
}
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Candidates.reset(MO.getReg());
for (const unsigned *R = TRI->getAliasSet(MO.getReg()); *R; R++)
Candidates.reset(*R);
}
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// If we're not in a virtual reg's live range, this is a valid
// restore point.
if (!inVirtLiveRange) RestorePointMI = MI;
// Update whether we're in the live range of a virtual register
if (isVirtKillInsn) inVirtLiveRange = false;
if (isVirtDefInsn) inVirtLiveRange = true;
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// Was our survivor untouched by this instruction?
if (Candidates.test(Survivor))
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continue;
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// All candidates gone?
if (Candidates.none())
break;
Survivor = Candidates.find_first();
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}
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// If we ran off the end, that's where we want to restore.
if (MI == ME) RestorePointMI = ME;
assert (RestorePointMI != StartMI &&
"No available scavenger restore location!");
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// We ran out of candidates, so stop the search.
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UseMI = RestorePointMI;
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return Survivor;
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}
unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
MachineBasicBlock::iterator I,
int SPAdj) {
// Consider all allocatable registers in the register class initially
BitVector Candidates =
TRI->getAllocatableSet(*I->getParent()->getParent(), RC);
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// Exclude all the registers being used by the instruction.
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
MachineOperand &MO = I->getOperand(i);
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if (MO.isReg() && MO.getReg() != 0 &&
!TargetRegisterInfo::isVirtualRegister(MO.getReg()))
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Candidates.reset(MO.getReg());
}
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// Try to find a register that's unused if there is one, as then we won't
// have to spill.
if ((Candidates & RegsAvailable).any())
Candidates &= RegsAvailable;
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// Find the register whose use is furthest away.
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MachineBasicBlock::iterator UseMI;
unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
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// If we found an unused register there is no reason to spill it.
if (!isAliasUsed(SReg)) {
DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n");
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return SReg;
}
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assert(ScavengedReg == 0 &&
"Scavenger slot is live, unable to scavenge another register!");
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// Avoid infinite regress
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ScavengedReg = SReg;
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// If the target knows how to save/restore the register, let it do so;
// otherwise, use the emergency stack spill slot.
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if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) {
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// Spill the scavenged register before I.
assert(ScavengingFrameIndex >= 0 &&
"Cannot scavenge register without an emergency spill slot!");
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TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC,TRI);
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MachineBasicBlock::iterator II = prior(I);
TRI->eliminateFrameIndex(II, SPAdj, this);
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// Restore the scavenged register before its use (or first terminator).
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TII->loadRegFromStackSlot(*MBB, UseMI, SReg, ScavengingFrameIndex, RC, TRI);
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II = prior(UseMI);
TRI->eliminateFrameIndex(II, SPAdj, this);
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}
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ScavengeRestore = prior(UseMI);
// Doing this here leads to infinite regress.
// ScavengedReg = SReg;
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ScavengedRC = RC;
DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) <<
"\n");
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return SReg;
}