d/freebsd-dev
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
d8b88105c2
freebsd-dev/sys/arm/at91/uart_dev_at91usart.c

853 lines
24 KiB
C
Raw Normal View History

Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
/*-
* Copyright (c) 2005 M. Warner Losh
Resurrect Skyeye support : Add a new option, SKYEYE_WORKAROUNDS, which as the name suggests adds workarounds for things skyeye doesn't simulate. Specifically : - Use USART0 instead of DBGU as the console, make it not use DMA, and manually provoke an interrupt when we're done in the transmit function. - Skyeye maintains an internal counter for clock, but apparently there's no way to access it, so hack the timecounter code to return a value which is increased at every clock interrupts. This is gross, but I didn't find a better way to implement timecounters without hacking Skyeye to get the counter value. - Force the write-back of PTEs once we're done writing them, even if they are supposed to be write-through. I don't know why I have to do that.
2006-05-13 23:41:16 +00:00
* Copyright (c) 2005 Olivier Houchard
Enable hardware flow control and high speed bulk data transfer in at91 uarts. Changes to make rtc/cts flow control work... This does not turn on the builtin hardware flow control on the SoC's usart device, because that doesn't work on uart1 due to a chip erratum (they forgot to wire up pin PA21 to RTS0 internally). Instead it uses the hardware flow control logic where the tty layer calls the driver to assert and de-assert the flow control lines as needed. This prevents overruns at the tty layer (app doesn't read fast enough), but does nothing for overruns at the driver layer (interrupts not serviced fast enough). To work around the wiring problem with RTS0, the driver reassigns that pin as a GPIO and controls it manually. It only does so if given permission via hint.uart.1.use_rts0_workaround=1, to prevent accidentally driving the pin if uart1 is used without flow control (because something not related to serial IO could be wired to that pin). In addition to the RTS0 workaround, driver changes were needed in the area of reading the current set of DCE signals. A priming read is now done at attach() time, and the interrupt routine now sets SER_INT_SIGCHG when any of the DCE signals change. Without these changes, nothing could ever be transmitted, because the tty layer thought CTS was de-asserted (when in fact we had just never read the status register, and the hwsig variable was init'd to CTS de-asserted). Changes to support bulk high-speed (230kbps and higher) data reception... Allow the receive fifo size to be tuned with hint.uart.<dev>.fifo_bytes. For high speed receive, a fifo size of 1024 works well. The default is still 128 bytes if no hint is provided. Using a value larger than 384 requires a change in dev/uart/uart_core.c to size the intermediate buffer as MAX(384, 3*sc->sc_rxfifosize). Recalculate the receive timeout whenever the baud rate changes. At low baud rates (19.2kbps and below) the timeout is the number of bits in 2 characters. At higher speed it's calculated to be 500 microseconds worth of bits. The idea is to compromise between being responsive in interactive situations and not timing out prematurely during a brief pause in bulk data flow. The old fixed timeout of 1.5 characters was just 32 microseconds at 460kbps. At interrupt time, check for receiver holding register overrun status and set the corresponding status bit in the return value. When handling a buffer overrun, get a single buffer emptied and handed back to the hardware as quickly as possible, then deal with the second buffer. This at least minimizes data loss compared to the old logic that fully processed both buffers before restarting the hardware. Rewrite the logic for handling buffers after a receive timeout. The original author speculated in a comment that there may be a race with high speed data. There was, although it was rare. The code now handles all three possible scenarios on receive timeout: two empty buffers, one empty and one partial buffer, or one full and one partial buffer. Reviewed by: imp
2013-04-01 00:00:10 +00:00
* Copyright (c) 2012 Ian Lepore
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
Tweak the disclaimer section of the license to match COPYRIGHT, for better or worse. Ok'd by folks that have additional copyrights to the files in cases where there's joint authorship.
2008-11-25 00:13:26 +00:00
* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/conf.h>
#include <sys/cons.h>
#include <sys/tty.h>
#include <machine/bus.h>
#include <dev/uart/uart.h>
#include <dev/uart/uart_cpu.h>
#include <dev/uart/uart_bus.h>
#include <arm/at91/at91_usartreg.h>
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
#include <arm/at91/at91_pdcreg.h>
Enable hardware flow control and high speed bulk data transfer in at91 uarts. Changes to make rtc/cts flow control work... This does not turn on the builtin hardware flow control on the SoC's usart device, because that doesn't work on uart1 due to a chip erratum (they forgot to wire up pin PA21 to RTS0 internally). Instead it uses the hardware flow control logic where the tty layer calls the driver to assert and de-assert the flow control lines as needed. This prevents overruns at the tty layer (app doesn't read fast enough), but does nothing for overruns at the driver layer (interrupts not serviced fast enough). To work around the wiring problem with RTS0, the driver reassigns that pin as a GPIO and controls it manually. It only does so if given permission via hint.uart.1.use_rts0_workaround=1, to prevent accidentally driving the pin if uart1 is used without flow control (because something not related to serial IO could be wired to that pin). In addition to the RTS0 workaround, driver changes were needed in the area of reading the current set of DCE signals. A priming read is now done at attach() time, and the interrupt routine now sets SER_INT_SIGCHG when any of the DCE signals change. Without these changes, nothing could ever be transmitted, because the tty layer thought CTS was de-asserted (when in fact we had just never read the status register, and the hwsig variable was init'd to CTS de-asserted). Changes to support bulk high-speed (230kbps and higher) data reception... Allow the receive fifo size to be tuned with hint.uart.<dev>.fifo_bytes. For high speed receive, a fifo size of 1024 works well. The default is still 128 bytes if no hint is provided. Using a value larger than 384 requires a change in dev/uart/uart_core.c to size the intermediate buffer as MAX(384, 3*sc->sc_rxfifosize). Recalculate the receive timeout whenever the baud rate changes. At low baud rates (19.2kbps and below) the timeout is the number of bits in 2 characters. At higher speed it's calculated to be 500 microseconds worth of bits. The idea is to compromise between being responsive in interactive situations and not timing out prematurely during a brief pause in bulk data flow. The old fixed timeout of 1.5 characters was just 32 microseconds at 460kbps. At interrupt time, check for receiver holding register overrun status and set the corresponding status bit in the return value. When handling a buffer overrun, get a single buffer emptied and handed back to the hardware as quickly as possible, then deal with the second buffer. This at least minimizes data loss compared to the old logic that fully processed both buffers before restarting the hardware. Rewrite the logic for handling buffers after a receive timeout. The original author speculated in a comment that there may be a race with high speed data. There was, although it was rare. The code now handles all three possible scenarios on receive timeout: two empty buffers, one empty and one partial buffer, or one full and one partial buffer. Reviewed by: imp
2013-04-01 00:00:10 +00:00
#include <arm/at91/at91_piovar.h>
#include <arm/at91/at91_pioreg.h>
#include <arm/at91/at91rm92reg.h>
Migrate towards using at91_master_clock. Initialize the clocks for the serial port class when we set the devclass since it is now no-longer a compile time constant. Eliminate the pci include, as it isn't relevant or necessary.
2009-01-22 21:56:41 +00:00
#include <arm/at91/at91var.h>
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
#include "uart_if.h"
Enable hardware flow control and high speed bulk data transfer in at91 uarts. Changes to make rtc/cts flow control work... This does not turn on the builtin hardware flow control on the SoC's usart device, because that doesn't work on uart1 due to a chip erratum (they forgot to wire up pin PA21 to RTS0 internally). Instead it uses the hardware flow control logic where the tty layer calls the driver to assert and de-assert the flow control lines as needed. This prevents overruns at the tty layer (app doesn't read fast enough), but does nothing for overruns at the driver layer (interrupts not serviced fast enough). To work around the wiring problem with RTS0, the driver reassigns that pin as a GPIO and controls it manually. It only does so if given permission via hint.uart.1.use_rts0_workaround=1, to prevent accidentally driving the pin if uart1 is used without flow control (because something not related to serial IO could be wired to that pin). In addition to the RTS0 workaround, driver changes were needed in the area of reading the current set of DCE signals. A priming read is now done at attach() time, and the interrupt routine now sets SER_INT_SIGCHG when any of the DCE signals change. Without these changes, nothing could ever be transmitted, because the tty layer thought CTS was de-asserted (when in fact we had just never read the status register, and the hwsig variable was init'd to CTS de-asserted). Changes to support bulk high-speed (230kbps and higher) data reception... Allow the receive fifo size to be tuned with hint.uart.<dev>.fifo_bytes. For high speed receive, a fifo size of 1024 works well. The default is still 128 bytes if no hint is provided. Using a value larger than 384 requires a change in dev/uart/uart_core.c to size the intermediate buffer as MAX(384, 3*sc->sc_rxfifosize). Recalculate the receive timeout whenever the baud rate changes. At low baud rates (19.2kbps and below) the timeout is the number of bits in 2 characters. At higher speed it's calculated to be 500 microseconds worth of bits. The idea is to compromise between being responsive in interactive situations and not timing out prematurely during a brief pause in bulk data flow. The old fixed timeout of 1.5 characters was just 32 microseconds at 460kbps. At interrupt time, check for receiver holding register overrun status and set the corresponding status bit in the return value. When handling a buffer overrun, get a single buffer emptied and handed back to the hardware as quickly as possible, then deal with the second buffer. This at least minimizes data loss compared to the old logic that fully processed both buffers before restarting the hardware. Rewrite the logic for handling buffers after a receive timeout. The original author speculated in a comment that there may be a race with high speed data. There was, although it was rare. The code now handles all three possible scenarios on receive timeout: two empty buffers, one empty and one partial buffer, or one full and one partial buffer. Reviewed by: imp
2013-04-01 00:00:10 +00:00
#define DEFAULT_RCLK at91_master_clock
#define USART_DEFAULT_FIFO_BYTES 128
#define USART_DCE_CHANGE_BITS (USART_CSR_CTSIC | USART_CSR_DCDIC | \
USART_CSR_DSRIC | USART_CSR_RIIC)
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
/*
* High-level UART interface.
*/
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
struct at91_usart_rx {
bus_addr_t pa;
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
uint8_t *buffer;
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
bus_dmamap_t map;
};
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
struct at91_usart_softc {
struct uart_softc base;
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
bus_dma_tag_t tx_tag;
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
bus_dmamap_t tx_map;
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
uint32_t flags;
Enable hardware flow control and high speed bulk data transfer in at91 uarts. Changes to make rtc/cts flow control work... This does not turn on the builtin hardware flow control on the SoC's usart device, because that doesn't work on uart1 due to a chip erratum (they forgot to wire up pin PA21 to RTS0 internally). Instead it uses the hardware flow control logic where the tty layer calls the driver to assert and de-assert the flow control lines as needed. This prevents overruns at the tty layer (app doesn't read fast enough), but does nothing for overruns at the driver layer (interrupts not serviced fast enough). To work around the wiring problem with RTS0, the driver reassigns that pin as a GPIO and controls it manually. It only does so if given permission via hint.uart.1.use_rts0_workaround=1, to prevent accidentally driving the pin if uart1 is used without flow control (because something not related to serial IO could be wired to that pin). In addition to the RTS0 workaround, driver changes were needed in the area of reading the current set of DCE signals. A priming read is now done at attach() time, and the interrupt routine now sets SER_INT_SIGCHG when any of the DCE signals change. Without these changes, nothing could ever be transmitted, because the tty layer thought CTS was de-asserted (when in fact we had just never read the status register, and the hwsig variable was init'd to CTS de-asserted). Changes to support bulk high-speed (230kbps and higher) data reception... Allow the receive fifo size to be tuned with hint.uart.<dev>.fifo_bytes. For high speed receive, a fifo size of 1024 works well. The default is still 128 bytes if no hint is provided. Using a value larger than 384 requires a change in dev/uart/uart_core.c to size the intermediate buffer as MAX(384, 3*sc->sc_rxfifosize). Recalculate the receive timeout whenever the baud rate changes. At low baud rates (19.2kbps and below) the timeout is the number of bits in 2 characters. At higher speed it's calculated to be 500 microseconds worth of bits. The idea is to compromise between being responsive in interactive situations and not timing out prematurely during a brief pause in bulk data flow. The old fixed timeout of 1.5 characters was just 32 microseconds at 460kbps. At interrupt time, check for receiver holding register overrun status and set the corresponding status bit in the return value. When handling a buffer overrun, get a single buffer emptied and handed back to the hardware as quickly as possible, then deal with the second buffer. This at least minimizes data loss compared to the old logic that fully processed both buffers before restarting the hardware. Rewrite the logic for handling buffers after a receive timeout. The original author speculated in a comment that there may be a race with high speed data. There was, although it was rare. The code now handles all three possible scenarios on receive timeout: two empty buffers, one empty and one partial buffer, or one full and one partial buffer. Reviewed by: imp
2013-04-01 00:00:10 +00:00
#define HAS_TIMEOUT 0x1
#define USE_RTS0_WORKAROUND 0x2
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
bus_dma_tag_t rx_tag;
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
struct at91_usart_rx ping_pong[2];
struct at91_usart_rx *ping;
struct at91_usart_rx *pong;
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
};
#define RD4(bas, reg) \
bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
#define WR4(bas, reg, value) \
bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
#define SIGCHG(c, i, s, d) \
do { \
if (c) { \
i |= (i & s) ? s : s | d; \
} else { \
i = (i & s) ? (i & ~s) | d : i; \
} \
} while (0);
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
#define BAUD2DIVISOR(b) \
((((DEFAULT_RCLK * 10) / ((b) * 16)) + 5) / 10)
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
/*
* Low-level UART interface.
*/
static int at91_usart_probe(struct uart_bas *bas);
static void at91_usart_init(struct uart_bas *bas, int, int, int, int);
static void at91_usart_term(struct uart_bas *bas);
static void at91_usart_putc(struct uart_bas *bas, int);
- Add a uart_rxready() and corresponding device-specific implementations that can be used to check whether receive data is ready, i.e. whether the subsequent call of uart_poll() should return a char, and unlike uart_poll() doesn't actually receive data. - Remove the device-specific implementations of uart_poll() and implement uart_poll() in terms of uart_getc() and the newly added uart_rxready() in order to minimize code duplication. - In sunkbd(4) take advantage of uart_rxready() and use it to implement the polled mode part of sunkbd_check() so we don't need to buffer a potentially read char in the softc. - Fix some mis-indentation in sunkbd_read_char(). Discussed with: marcel
2007-01-18 22:01:19 +00:00
static int at91_usart_rxready(struct uart_bas *bas);
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
static int at91_usart_getc(struct uart_bas *bas, struct mtx *hwmtx);
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
static int
at91_usart_param(struct uart_bas *bas, int baudrate, int databits,
int stopbits, int parity)
{
uint32_t mr;
/*
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
* Assume 3-wire RS-232 configuration.
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
* XXX Not sure how uart will present the other modes to us, so
* XXX they are unimplemented. maybe ioctl?
*/
mr = USART_MR_MODE_NORMAL;
mr |= USART_MR_USCLKS_MCK; /* Assume MCK */
/*
* Or in the databits requested
*/
if (databits < 9)
mr &= ~USART_MR_MODE9;
switch (databits) {
case 5:
mr |= USART_MR_CHRL_5BITS;
break;
case 6:
mr |= USART_MR_CHRL_6BITS;
break;
case 7:
mr |= USART_MR_CHRL_7BITS;
break;
case 8:
mr |= USART_MR_CHRL_8BITS;
break;
case 9:
mr |= USART_MR_CHRL_8BITS | USART_MR_MODE9;
break;
default:
return (EINVAL);
}
/*
* Or in the parity
*/
switch (parity) {
case UART_PARITY_NONE:
mr |= USART_MR_PAR_NONE;
break;
case UART_PARITY_ODD:
mr |= USART_MR_PAR_ODD;
break;
case UART_PARITY_EVEN:
mr |= USART_MR_PAR_EVEN;
break;
case UART_PARITY_MARK:
mr |= USART_MR_PAR_MARK;
break;
case UART_PARITY_SPACE:
mr |= USART_MR_PAR_SPACE;
break;
default:
return (EINVAL);
}
/*
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
* Or in the stop bits. Note: The hardware supports 1.5 stop
* bits in async mode, but there's no way to specify that
* AFAICT. Instead, rely on the convention documented at
* http://www.lammertbies.nl/comm/info/RS-232_specs.html which
* states that 1.5 stop bits are used for 5 bit bytes and
* 2 stop bits only for longer bytes.
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
*/
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
if (stopbits == 1)
mr |= USART_MR_NBSTOP_1;
else if (databits > 5)
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
mr |= USART_MR_NBSTOP_2;
else
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
mr |= USART_MR_NBSTOP_1_5;
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
/*
* We want normal plumbing mode too, none of this fancy
* loopback or echo mode.
*/
mr |= USART_MR_CHMODE_NORMAL;
mr &= ~USART_MR_MSBF; /* lsb first */
mr &= ~USART_MR_CKLO_SCK; /* Don't drive SCK */
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
WR4(bas, USART_MR, mr);
/*
if_ate.c: * Support for sam9 "EMAC" controller. * Support for rmii interface to phy. at91.c & at91sam9.c: * Eliminate separate at91sam9.c file. * Add new devices to at91sam9_devs table. at91_machdep.c & at at91sam9_machdep.c: * Automatic chip type determination. * Remove compile time chip dependencies. * Eliminate separate at91sam9_machdep.c file. at91_pmc.c: * Corrected support for all of the sam926? and sam9g20 chips. * Remove compile time chip dependencies. My apologies to Greg for taking so long to take care of it.
2010-10-06 22:25:21 +00:00
* Set the baud rate (only if we know our master clock rate)
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
*/
if_ate.c: * Support for sam9 "EMAC" controller. * Support for rmii interface to phy. at91.c & at91sam9.c: * Eliminate separate at91sam9.c file. * Add new devices to at91sam9_devs table. at91_machdep.c & at at91sam9_machdep.c: * Automatic chip type determination. * Remove compile time chip dependencies. * Eliminate separate at91sam9_machdep.c file. at91_pmc.c: * Corrected support for all of the sam926? and sam9g20 chips. * Remove compile time chip dependencies. My apologies to Greg for taking so long to take care of it.
2010-10-06 22:25:21 +00:00
if (DEFAULT_RCLK != 0)
WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate));
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
Enable hardware flow control and high speed bulk data transfer in at91 uarts. Changes to make rtc/cts flow control work... This does not turn on the builtin hardware flow control on the SoC's usart device, because that doesn't work on uart1 due to a chip erratum (they forgot to wire up pin PA21 to RTS0 internally). Instead it uses the hardware flow control logic where the tty layer calls the driver to assert and de-assert the flow control lines as needed. This prevents overruns at the tty layer (app doesn't read fast enough), but does nothing for overruns at the driver layer (interrupts not serviced fast enough). To work around the wiring problem with RTS0, the driver reassigns that pin as a GPIO and controls it manually. It only does so if given permission via hint.uart.1.use_rts0_workaround=1, to prevent accidentally driving the pin if uart1 is used without flow control (because something not related to serial IO could be wired to that pin). In addition to the RTS0 workaround, driver changes were needed in the area of reading the current set of DCE signals. A priming read is now done at attach() time, and the interrupt routine now sets SER_INT_SIGCHG when any of the DCE signals change. Without these changes, nothing could ever be transmitted, because the tty layer thought CTS was de-asserted (when in fact we had just never read the status register, and the hwsig variable was init'd to CTS de-asserted). Changes to support bulk high-speed (230kbps and higher) data reception... Allow the receive fifo size to be tuned with hint.uart.<dev>.fifo_bytes. For high speed receive, a fifo size of 1024 works well. The default is still 128 bytes if no hint is provided. Using a value larger than 384 requires a change in dev/uart/uart_core.c to size the intermediate buffer as MAX(384, 3*sc->sc_rxfifosize). Recalculate the receive timeout whenever the baud rate changes. At low baud rates (19.2kbps and below) the timeout is the number of bits in 2 characters. At higher speed it's calculated to be 500 microseconds worth of bits. The idea is to compromise between being responsive in interactive situations and not timing out prematurely during a brief pause in bulk data flow. The old fixed timeout of 1.5 characters was just 32 microseconds at 460kbps. At interrupt time, check for receiver holding register overrun status and set the corresponding status bit in the return value. When handling a buffer overrun, get a single buffer emptied and handed back to the hardware as quickly as possible, then deal with the second buffer. This at least minimizes data loss compared to the old logic that fully processed both buffers before restarting the hardware. Rewrite the logic for handling buffers after a receive timeout. The original author speculated in a comment that there may be a race with high speed data. There was, although it was rare. The code now handles all three possible scenarios on receive timeout: two empty buffers, one empty and one partial buffer, or one full and one partial buffer. Reviewed by: imp
2013-04-01 00:00:10 +00:00
/*
* Set the receive timeout based on the baud rate. The idea is to
* compromise between being responsive on an interactive connection and
* giving a bulk data sender a bit of time to queue up a new buffer
* without mistaking it for a stopping point in the transmission. For
* 19.2kbps and below, use 20 * bit time (2 characters). For faster
* connections use 500 microseconds worth of bits.
*/
if (baudrate <= 19200)
WR4(bas, USART_RTOR, 20);
else
WR4(bas, USART_RTOR, baudrate / 2000);
WR4(bas, USART_CR, USART_CR_STTTO);
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
/* XXX Need to take possible synchronous mode into account */
return (0);
}
Don't expose the uart_ops structure directly, but instead have it obtained through the uart_class structure. This allows us to declare the uart_class structure as weak and as such allows us to reference it even when it's not compiled-in. It also allows is to get the uart_ops structure by name, which makes it possible to implement the dt tag handling in uart_getenv(). The side-effect of all this is that we're using the uart_class structure more consistently which means that we now also have access to the size of the bus space block needed by the hardware when we map the bus space, eliminating any hardcoding.
2007-04-02 22:00:22 +00:00
static struct uart_ops at91_usart_ops = {
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
.probe = at91_usart_probe,
.init = at91_usart_init,
.term = at91_usart_term,
.putc = at91_usart_putc,
- Add a uart_rxready() and corresponding device-specific implementations that can be used to check whether receive data is ready, i.e. whether the subsequent call of uart_poll() should return a char, and unlike uart_poll() doesn't actually receive data. - Remove the device-specific implementations of uart_poll() and implement uart_poll() in terms of uart_getc() and the newly added uart_rxready() in order to minimize code duplication. - In sunkbd(4) take advantage of uart_rxready() and use it to implement the polled mode part of sunkbd_check() so we don't need to buffer a potentially read char in the softc. - Fix some mis-indentation in sunkbd_read_char(). Discussed with: marcel
2007-01-18 22:01:19 +00:00
.rxready = at91_usart_rxready,
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
.getc = at91_usart_getc,
};
static int
at91_usart_probe(struct uart_bas *bas)
{
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
/* We know that this is always here */
return (0);
}
/*
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
* Initialize this device for use as a console.
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
*/
static void
at91_usart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
int parity)
{
MFp4: Handle break interrupts (it seems to only work for USART, not DBGU).
2006-03-22 21:16:09 +00:00
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
at91_usart_param(bas, baudrate, databits, stopbits, parity);
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
/* Reset the rx and tx buffers and turn on rx and tx */
WR4(bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX);
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
WR4(bas, USART_IDR, 0xffffffff);
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
}
/*
* Free resources now that we're no longer the console. This appears to
* be never called, and I'm unsure quite what to do if I am called.
*/
static void
at91_usart_term(struct uart_bas *bas)
{
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
/* XXX */
}
/*
* Put a character of console output (so we do it here polling rather than
Enable hardware flow control and high speed bulk data transfer in at91 uarts. Changes to make rtc/cts flow control work... This does not turn on the builtin hardware flow control on the SoC's usart device, because that doesn't work on uart1 due to a chip erratum (they forgot to wire up pin PA21 to RTS0 internally). Instead it uses the hardware flow control logic where the tty layer calls the driver to assert and de-assert the flow control lines as needed. This prevents overruns at the tty layer (app doesn't read fast enough), but does nothing for overruns at the driver layer (interrupts not serviced fast enough). To work around the wiring problem with RTS0, the driver reassigns that pin as a GPIO and controls it manually. It only does so if given permission via hint.uart.1.use_rts0_workaround=1, to prevent accidentally driving the pin if uart1 is used without flow control (because something not related to serial IO could be wired to that pin). In addition to the RTS0 workaround, driver changes were needed in the area of reading the current set of DCE signals. A priming read is now done at attach() time, and the interrupt routine now sets SER_INT_SIGCHG when any of the DCE signals change. Without these changes, nothing could ever be transmitted, because the tty layer thought CTS was de-asserted (when in fact we had just never read the status register, and the hwsig variable was init'd to CTS de-asserted). Changes to support bulk high-speed (230kbps and higher) data reception... Allow the receive fifo size to be tuned with hint.uart.<dev>.fifo_bytes. For high speed receive, a fifo size of 1024 works well. The default is still 128 bytes if no hint is provided. Using a value larger than 384 requires a change in dev/uart/uart_core.c to size the intermediate buffer as MAX(384, 3*sc->sc_rxfifosize). Recalculate the receive timeout whenever the baud rate changes. At low baud rates (19.2kbps and below) the timeout is the number of bits in 2 characters. At higher speed it's calculated to be 500 microseconds worth of bits. The idea is to compromise between being responsive in interactive situations and not timing out prematurely during a brief pause in bulk data flow. The old fixed timeout of 1.5 characters was just 32 microseconds at 460kbps. At interrupt time, check for receiver holding register overrun status and set the corresponding status bit in the return value. When handling a buffer overrun, get a single buffer emptied and handed back to the hardware as quickly as possible, then deal with the second buffer. This at least minimizes data loss compared to the old logic that fully processed both buffers before restarting the hardware. Rewrite the logic for handling buffers after a receive timeout. The original author speculated in a comment that there may be a race with high speed data. There was, although it was rare. The code now handles all three possible scenarios on receive timeout: two empty buffers, one empty and one partial buffer, or one full and one partial buffer. Reviewed by: imp
2013-04-01 00:00:10 +00:00
* interrupt driven).
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
*/
static void
at91_usart_putc(struct uart_bas *bas, int c)
{
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
while (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY))
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
continue;
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
WR4(bas, USART_THR, c);
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
}
Implement support for early printf. You need to define SOCDEV_{PA,VA} as described in the comments for the eputc function in your config file.
2014-01-22 21:49:20 +00:00
#ifdef EARLY_PRINTF
/*
* Early printf support. This assumes that we have the SoC "system" devices
* mapped into AT91_BASE. To use this before we adjust the boostrap tables,
* You'll need to define SOCDEV_VA to be 0xdc000000 and SOCDEV_PA to be
* 0xfc000000 in your config file where you define EARLY_PRINTF
*/
volatile uint32_t *at91_dbgu = (volatile uint32_t *)(AT91_BASE + AT91_DBGU0);
void
eputc(int c)
{
Make early printf output nicer by inserting a carriage return before any linefeeds that are output.
2014-01-25 21:57:45 +00:00
if (c == '\n')
eputc('\r');
Implement support for early printf. You need to define SOCDEV_{PA,VA} as described in the comments for the eputc function in your config file.
2014-01-22 21:49:20 +00:00
while (!(at91_dbgu[USART_CSR / 4] & USART_CSR_TXRDY))
continue;
at91_dbgu[USART_THR / 4] = c;
}
#endif
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
/*
- Add a uart_rxready() and corresponding device-specific implementations that can be used to check whether receive data is ready, i.e. whether the subsequent call of uart_poll() should return a char, and unlike uart_poll() doesn't actually receive data. - Remove the device-specific implementations of uart_poll() and implement uart_poll() in terms of uart_getc() and the newly added uart_rxready() in order to minimize code duplication. - In sunkbd(4) take advantage of uart_rxready() and use it to implement the polled mode part of sunkbd_check() so we don't need to buffer a potentially read char in the softc. - Fix some mis-indentation in sunkbd_read_char(). Discussed with: marcel
2007-01-18 22:01:19 +00:00
* Check for a character available.
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
*/
static int
- Add a uart_rxready() and corresponding device-specific implementations that can be used to check whether receive data is ready, i.e. whether the subsequent call of uart_poll() should return a char, and unlike uart_poll() doesn't actually receive data. - Remove the device-specific implementations of uart_poll() and implement uart_poll() in terms of uart_getc() and the newly added uart_rxready() in order to minimize code duplication. - In sunkbd(4) take advantage of uart_rxready() and use it to implement the polled mode part of sunkbd_check() so we don't need to buffer a potentially read char in the softc. - Fix some mis-indentation in sunkbd_read_char(). Discussed with: marcel
2007-01-18 22:01:19 +00:00
at91_usart_rxready(struct uart_bas *bas)
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
{
- Add a uart_rxready() and corresponding device-specific implementations that can be used to check whether receive data is ready, i.e. whether the subsequent call of uart_poll() should return a char, and unlike uart_poll() doesn't actually receive data. - Remove the device-specific implementations of uart_poll() and implement uart_poll() in terms of uart_getc() and the newly added uart_rxready() in order to minimize code duplication. - In sunkbd(4) take advantage of uart_rxready() and use it to implement the polled mode part of sunkbd_check() so we don't need to buffer a potentially read char in the softc. - Fix some mis-indentation in sunkbd_read_char(). Discussed with: marcel
2007-01-18 22:01:19 +00:00
return ((RD4(bas, USART_CSR) & USART_CSR_RXRDY) != 0 ? 1 : 0);
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
}
/*
* Block waiting for a character.
*/
static int
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
at91_usart_getc(struct uart_bas *bas, struct mtx *hwmtx)
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
{
int c;
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
uart_lock(hwmtx);
while (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY)) {
uart_unlock(hwmtx);
DELAY(4);
uart_lock(hwmtx);
}
c = RD4(bas, USART_RHR) & 0xff;
uart_unlock(hwmtx);
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
return (c);
}
static int at91_usart_bus_probe(struct uart_softc *sc);
static int at91_usart_bus_attach(struct uart_softc *sc);
static int at91_usart_bus_flush(struct uart_softc *, int);
static int at91_usart_bus_getsig(struct uart_softc *);
static int at91_usart_bus_ioctl(struct uart_softc *, int, intptr_t);
static int at91_usart_bus_ipend(struct uart_softc *);
static int at91_usart_bus_param(struct uart_softc *, int, int, int, int);
static int at91_usart_bus_receive(struct uart_softc *);
static int at91_usart_bus_setsig(struct uart_softc *, int);
static int at91_usart_bus_transmit(struct uart_softc *);
Connect NAND for the SAM9260EK eval board, as well as the HotE HL-201. # expect more refinement as do more boards.
2014-01-19 17:59:34 +00:00
static void at91_usart_bus_grab(struct uart_softc *);
static void at91_usart_bus_ungrab(struct uart_softc *);
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
static kobj_method_t at91_usart_methods[] = {
KOBJMETHOD(uart_probe, at91_usart_bus_probe),
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
KOBJMETHOD(uart_attach, at91_usart_bus_attach),
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
KOBJMETHOD(uart_flush, at91_usart_bus_flush),
KOBJMETHOD(uart_getsig, at91_usart_bus_getsig),
KOBJMETHOD(uart_ioctl, at91_usart_bus_ioctl),
KOBJMETHOD(uart_ipend, at91_usart_bus_ipend),
KOBJMETHOD(uart_param, at91_usart_bus_param),
KOBJMETHOD(uart_receive, at91_usart_bus_receive),
KOBJMETHOD(uart_setsig, at91_usart_bus_setsig),
KOBJMETHOD(uart_transmit, at91_usart_bus_transmit),
Connect NAND for the SAM9260EK eval board, as well as the HotE HL-201. # expect more refinement as do more boards.
2014-01-19 17:59:34 +00:00
KOBJMETHOD(uart_grab, at91_usart_bus_grab),
KOBJMETHOD(uart_ungrab, at91_usart_bus_ungrab),
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
KOBJMETHOD_END
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
};
int
at91_usart_bus_probe(struct uart_softc *sc)
{
Enable hardware flow control and high speed bulk data transfer in at91 uarts. Changes to make rtc/cts flow control work... This does not turn on the builtin hardware flow control on the SoC's usart device, because that doesn't work on uart1 due to a chip erratum (they forgot to wire up pin PA21 to RTS0 internally). Instead it uses the hardware flow control logic where the tty layer calls the driver to assert and de-assert the flow control lines as needed. This prevents overruns at the tty layer (app doesn't read fast enough), but does nothing for overruns at the driver layer (interrupts not serviced fast enough). To work around the wiring problem with RTS0, the driver reassigns that pin as a GPIO and controls it manually. It only does so if given permission via hint.uart.1.use_rts0_workaround=1, to prevent accidentally driving the pin if uart1 is used without flow control (because something not related to serial IO could be wired to that pin). In addition to the RTS0 workaround, driver changes were needed in the area of reading the current set of DCE signals. A priming read is now done at attach() time, and the interrupt routine now sets SER_INT_SIGCHG when any of the DCE signals change. Without these changes, nothing could ever be transmitted, because the tty layer thought CTS was de-asserted (when in fact we had just never read the status register, and the hwsig variable was init'd to CTS de-asserted). Changes to support bulk high-speed (230kbps and higher) data reception... Allow the receive fifo size to be tuned with hint.uart.<dev>.fifo_bytes. For high speed receive, a fifo size of 1024 works well. The default is still 128 bytes if no hint is provided. Using a value larger than 384 requires a change in dev/uart/uart_core.c to size the intermediate buffer as MAX(384, 3*sc->sc_rxfifosize). Recalculate the receive timeout whenever the baud rate changes. At low baud rates (19.2kbps and below) the timeout is the number of bits in 2 characters. At higher speed it's calculated to be 500 microseconds worth of bits. The idea is to compromise between being responsive in interactive situations and not timing out prematurely during a brief pause in bulk data flow. The old fixed timeout of 1.5 characters was just 32 microseconds at 460kbps. At interrupt time, check for receiver holding register overrun status and set the corresponding status bit in the return value. When handling a buffer overrun, get a single buffer emptied and handed back to the hardware as quickly as possible, then deal with the second buffer. This at least minimizes data loss compared to the old logic that fully processed both buffers before restarting the hardware. Rewrite the logic for handling buffers after a receive timeout. The original author speculated in a comment that there may be a race with high speed data. There was, although it was rare. The code now handles all three possible scenarios on receive timeout: two empty buffers, one empty and one partial buffer, or one full and one partial buffer. Reviewed by: imp
2013-04-01 00:00:10 +00:00
int value;
value = USART_DEFAULT_FIFO_BYTES;
resource_int_value(device_get_name(sc->sc_dev),
device_get_unit(sc->sc_dev), "fifo_bytes", &value);
value = roundup2(value, arm_dcache_align);
sc->sc_txfifosz = value;
sc->sc_rxfifosz = value;
- Proprely intialize UART parameters at probe stage, so uart(4) will initialize the FIFO memory correctly on attach. Before that this values was intialized in only in at91_usart_bus_attach which is called after the uart(4) memory allocation happens. Approved by: re (kib) MFC after: 1 week
2009-08-15 15:15:20 +00:00
sc->sc_hwiflow = 0;
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
return (0);
}
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
static void
at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
{
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
if (error != 0)
return;
*(bus_addr_t *)arg = segs[0].ds_addr;
}
Enable hardware flow control and high speed bulk data transfer in at91 uarts. Changes to make rtc/cts flow control work... This does not turn on the builtin hardware flow control on the SoC's usart device, because that doesn't work on uart1 due to a chip erratum (they forgot to wire up pin PA21 to RTS0 internally). Instead it uses the hardware flow control logic where the tty layer calls the driver to assert and de-assert the flow control lines as needed. This prevents overruns at the tty layer (app doesn't read fast enough), but does nothing for overruns at the driver layer (interrupts not serviced fast enough). To work around the wiring problem with RTS0, the driver reassigns that pin as a GPIO and controls it manually. It only does so if given permission via hint.uart.1.use_rts0_workaround=1, to prevent accidentally driving the pin if uart1 is used without flow control (because something not related to serial IO could be wired to that pin). In addition to the RTS0 workaround, driver changes were needed in the area of reading the current set of DCE signals. A priming read is now done at attach() time, and the interrupt routine now sets SER_INT_SIGCHG when any of the DCE signals change. Without these changes, nothing could ever be transmitted, because the tty layer thought CTS was de-asserted (when in fact we had just never read the status register, and the hwsig variable was init'd to CTS de-asserted). Changes to support bulk high-speed (230kbps and higher) data reception... Allow the receive fifo size to be tuned with hint.uart.<dev>.fifo_bytes. For high speed receive, a fifo size of 1024 works well. The default is still 128 bytes if no hint is provided. Using a value larger than 384 requires a change in dev/uart/uart_core.c to size the intermediate buffer as MAX(384, 3*sc->sc_rxfifosize). Recalculate the receive timeout whenever the baud rate changes. At low baud rates (19.2kbps and below) the timeout is the number of bits in 2 characters. At higher speed it's calculated to be 500 microseconds worth of bits. The idea is to compromise between being responsive in interactive situations and not timing out prematurely during a brief pause in bulk data flow. The old fixed timeout of 1.5 characters was just 32 microseconds at 460kbps. At interrupt time, check for receiver holding register overrun status and set the corresponding status bit in the return value. When handling a buffer overrun, get a single buffer emptied and handed back to the hardware as quickly as possible, then deal with the second buffer. This at least minimizes data loss compared to the old logic that fully processed both buffers before restarting the hardware. Rewrite the logic for handling buffers after a receive timeout. The original author speculated in a comment that there may be a race with high speed data. There was, although it was rare. The code now handles all three possible scenarios on receive timeout: two empty buffers, one empty and one partial buffer, or one full and one partial buffer. Reviewed by: imp
2013-04-01 00:00:10 +00:00
static int
at91_usart_requires_rts0_workaround(struct uart_softc *sc)
{
int value;
int unit;
unit = device_get_unit(sc->sc_dev);
/*
* On the rm9200 chips, the PA21/RTS0 pin is not correctly wired to the
* usart device interally (so-called 'erratum 39', but it's 41.14 in rev
* I of the manual). This prevents use of the hardware flow control
* feature in the usart itself. It also means that if we are to
* implement RTS/CTS flow via the tty layer logic, we must use pin PA21
* as a gpio and manually manipulate it in at91_usart_bus_setsig(). We
* can only safely do so if we've been given permission via a hint,
* otherwise we might manipulate a pin that's attached to who-knows-what
* and Bad Things could happen.
*/
if (at91_is_rm92() && unit == 1) {
value = 0;
resource_int_value(device_get_name(sc->sc_dev), unit,
"use_rts0_workaround", &value);
if (value != 0) {
at91_pio_use_gpio(AT91RM92_PIOA_BASE, AT91C_PIO_PA21);
at91_pio_gpio_output(AT91RM92_PIOA_BASE,
AT91C_PIO_PA21, 1);
at91_pio_use_periph_a(AT91RM92_PIOA_BASE,
AT91C_PIO_PA20, 0);
return (1);
}
}
return (0);
}
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
static int
at91_usart_bus_attach(struct uart_softc *sc)
{
Unbreak build for Skyeye: do not attempt to do any DMA, as Skyeye doesn't emulate it. Reported by: ru
2006-12-07 00:24:15 +00:00
int err;
int i;
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
struct at91_usart_softc *atsc;
atsc = (struct at91_usart_softc *)sc;
Enable hardware flow control and high speed bulk data transfer in at91 uarts. Changes to make rtc/cts flow control work... This does not turn on the builtin hardware flow control on the SoC's usart device, because that doesn't work on uart1 due to a chip erratum (they forgot to wire up pin PA21 to RTS0 internally). Instead it uses the hardware flow control logic where the tty layer calls the driver to assert and de-assert the flow control lines as needed. This prevents overruns at the tty layer (app doesn't read fast enough), but does nothing for overruns at the driver layer (interrupts not serviced fast enough). To work around the wiring problem with RTS0, the driver reassigns that pin as a GPIO and controls it manually. It only does so if given permission via hint.uart.1.use_rts0_workaround=1, to prevent accidentally driving the pin if uart1 is used without flow control (because something not related to serial IO could be wired to that pin). In addition to the RTS0 workaround, driver changes were needed in the area of reading the current set of DCE signals. A priming read is now done at attach() time, and the interrupt routine now sets SER_INT_SIGCHG when any of the DCE signals change. Without these changes, nothing could ever be transmitted, because the tty layer thought CTS was de-asserted (when in fact we had just never read the status register, and the hwsig variable was init'd to CTS de-asserted). Changes to support bulk high-speed (230kbps and higher) data reception... Allow the receive fifo size to be tuned with hint.uart.<dev>.fifo_bytes. For high speed receive, a fifo size of 1024 works well. The default is still 128 bytes if no hint is provided. Using a value larger than 384 requires a change in dev/uart/uart_core.c to size the intermediate buffer as MAX(384, 3*sc->sc_rxfifosize). Recalculate the receive timeout whenever the baud rate changes. At low baud rates (19.2kbps and below) the timeout is the number of bits in 2 characters. At higher speed it's calculated to be 500 microseconds worth of bits. The idea is to compromise between being responsive in interactive situations and not timing out prematurely during a brief pause in bulk data flow. The old fixed timeout of 1.5 characters was just 32 microseconds at 460kbps. At interrupt time, check for receiver holding register overrun status and set the corresponding status bit in the return value. When handling a buffer overrun, get a single buffer emptied and handed back to the hardware as quickly as possible, then deal with the second buffer. This at least minimizes data loss compared to the old logic that fully processed both buffers before restarting the hardware. Rewrite the logic for handling buffers after a receive timeout. The original author speculated in a comment that there may be a race with high speed data. There was, although it was rare. The code now handles all three possible scenarios on receive timeout: two empty buffers, one empty and one partial buffer, or one full and one partial buffer. Reviewed by: imp
2013-04-01 00:00:10 +00:00
if (at91_usart_requires_rts0_workaround(sc))
atsc->flags |= USE_RTS0_WORKAROUND;
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
/*
Be sure to flush the cache after a partial read on timeout. Expand comments about timeouts. Fix a style nit. Sometimes small messages were getting corrupted.
2006-07-14 21:33:04 +00:00
* See if we have a TIMEOUT bit. We disable all interrupts as
* a side effect. Boot loaders may have enabled them. Since
* a TIMEOUT interrupt can't happen without other setup, the
* apparent race here can't actually happen.
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
*/
WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT);
if (RD4(&sc->sc_bas, USART_IMR) & USART_CSR_TIMEOUT)
atsc->flags |= HAS_TIMEOUT;
WR4(&sc->sc_bas, USART_IDR, 0xffffffff);
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
/*
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
* Allocate transmit DMA tag and map. We allow a transmit buffer
* to be any size, but it must map to a single contiguous physical
* extent.
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
*/
- Fix two minor errors in at91 code. PR: arm/128959 Submitted by: Bjorn Konig <bkoenig@alpha-tierchen.de> Approved by: kib (mentor)
2008-11-18 12:42:59 +00:00
err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
Use bus_get_dma_tag() instead of NULL here. Not really needed for atmel at the moment, but it is more correct.
2008-10-07 17:23:16 +00:00
BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
BUS_SPACE_MAXSIZE_32BIT, 1, BUS_SPACE_MAXSIZE_32BIT, 0, NULL,
NULL, &atsc->tx_tag);
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
if (err != 0)
goto errout;
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
err = bus_dmamap_create(atsc->tx_tag, 0, &atsc->tx_map);
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
if (err != 0)
Be sure to flush the cache after a partial read on timeout. Expand comments about timeouts. Fix a style nit. Sometimes small messages were getting corrupted.
2006-07-14 21:33:04 +00:00
goto errout;
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
if (atsc->flags & HAS_TIMEOUT) {
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
/*
* Allocate receive DMA tags, maps, and buffers.
* The receive buffers should be aligned to arm_dcache_align,
* otherwise partial cache line flushes on every receive
* interrupt are pretty much guaranteed.
*/
err = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),
arm_dcache_align, 0, BUS_SPACE_MAXADDR_32BIT,
BUS_SPACE_MAXADDR, NULL, NULL, sc->sc_rxfifosz, 1,
sc->sc_rxfifosz, BUS_DMA_ALLOCNOW, NULL, NULL,
&atsc->rx_tag);
if (err != 0)
goto errout;
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
for (i = 0; i < 2; i++) {
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
err = bus_dmamem_alloc(atsc->rx_tag,
(void **)&atsc->ping_pong[i].buffer,
BUS_DMA_NOWAIT, &atsc->ping_pong[i].map);
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
if (err != 0)
goto errout;
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
err = bus_dmamap_load(atsc->rx_tag,
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
atsc->ping_pong[i].map,
atsc->ping_pong[i].buffer, sc->sc_rxfifosz,
at91_getaddr, &atsc->ping_pong[i].pa, 0);
if (err != 0)
goto errout;
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
bus_dmamap_sync(atsc->rx_tag, atsc->ping_pong[i].map,
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
BUS_DMASYNC_PREREAD);
}
atsc->ping = &atsc->ping_pong[0];
atsc->pong = &atsc->ping_pong[1];
}
/* Turn on rx and tx */
Before resetting the USART, delay a bit to allow the transmitter to finish the current character to drain to avoid glitching. Also, simplify the code a smidge.
2014-01-26 04:57:58 +00:00
DELAY(1000); /* Give pending character a chance to drain. */
WR4(&sc->sc_bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX);
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
WR4(&sc->sc_bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN);
/*
* Setup the PDC to receive data. We use the ping-pong buffers
* so that we can more easily bounce between the two and so that
* we get an interrupt 1/2 way through the software 'fifo' we have
* to avoid overruns.
*/
if (atsc->flags & HAS_TIMEOUT) {
WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
/*
* Set the receive timeout to be 1.5 character times
* assuming 8N1.
*/
WR4(&sc->sc_bas, USART_RTOR, 15);
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
WR4(&sc->sc_bas, USART_IER, USART_CSR_TIMEOUT |
USART_CSR_RXBUFF | USART_CSR_ENDRX);
} else {
WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY);
}
Enable hardware flow control and high speed bulk data transfer in at91 uarts. Changes to make rtc/cts flow control work... This does not turn on the builtin hardware flow control on the SoC's usart device, because that doesn't work on uart1 due to a chip erratum (they forgot to wire up pin PA21 to RTS0 internally). Instead it uses the hardware flow control logic where the tty layer calls the driver to assert and de-assert the flow control lines as needed. This prevents overruns at the tty layer (app doesn't read fast enough), but does nothing for overruns at the driver layer (interrupts not serviced fast enough). To work around the wiring problem with RTS0, the driver reassigns that pin as a GPIO and controls it manually. It only does so if given permission via hint.uart.1.use_rts0_workaround=1, to prevent accidentally driving the pin if uart1 is used without flow control (because something not related to serial IO could be wired to that pin). In addition to the RTS0 workaround, driver changes were needed in the area of reading the current set of DCE signals. A priming read is now done at attach() time, and the interrupt routine now sets SER_INT_SIGCHG when any of the DCE signals change. Without these changes, nothing could ever be transmitted, because the tty layer thought CTS was de-asserted (when in fact we had just never read the status register, and the hwsig variable was init'd to CTS de-asserted). Changes to support bulk high-speed (230kbps and higher) data reception... Allow the receive fifo size to be tuned with hint.uart.<dev>.fifo_bytes. For high speed receive, a fifo size of 1024 works well. The default is still 128 bytes if no hint is provided. Using a value larger than 384 requires a change in dev/uart/uart_core.c to size the intermediate buffer as MAX(384, 3*sc->sc_rxfifosize). Recalculate the receive timeout whenever the baud rate changes. At low baud rates (19.2kbps and below) the timeout is the number of bits in 2 characters. At higher speed it's calculated to be 500 microseconds worth of bits. The idea is to compromise between being responsive in interactive situations and not timing out prematurely during a brief pause in bulk data flow. The old fixed timeout of 1.5 characters was just 32 microseconds at 460kbps. At interrupt time, check for receiver holding register overrun status and set the corresponding status bit in the return value. When handling a buffer overrun, get a single buffer emptied and handed back to the hardware as quickly as possible, then deal with the second buffer. This at least minimizes data loss compared to the old logic that fully processed both buffers before restarting the hardware. Rewrite the logic for handling buffers after a receive timeout. The original author speculated in a comment that there may be a race with high speed data. There was, although it was rare. The code now handles all three possible scenarios on receive timeout: two empty buffers, one empty and one partial buffer, or one full and one partial buffer. Reviewed by: imp
2013-04-01 00:00:10 +00:00
WR4(&sc->sc_bas, USART_IER, USART_CSR_RXBRK | USART_DCE_CHANGE_BITS);
/* Prime sc->hwsig with the initial hw line states. */
at91_usart_bus_getsig(sc);
Remove pointless semicolons after label
2011-09-30 04:55:23 +00:00
errout:
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
return (err);
}
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
static int
at91_usart_bus_transmit(struct uart_softc *sc)
{
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
bus_addr_t addr;
struct at91_usart_softc *atsc;
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
int err;
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
err = 0;
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
atsc = (struct at91_usart_softc *)sc;
MFp4: Catchup with recent UART changes.
2006-04-06 20:47:54 +00:00
uart_lock(sc->sc_hwmtx);
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
if (bus_dmamap_load(atsc->tx_tag, atsc->tx_map, sc->sc_txbuf,
sc->sc_txdatasz, at91_getaddr, &addr, 0) != 0) {
err = EAGAIN;
goto errout;
}
bus_dmamap_sync(atsc->tx_tag, atsc->tx_map, BUS_DMASYNC_PREWRITE);
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
sc->sc_txbusy = 1;
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
/*
* Setup the PDC to transfer the data and interrupt us when it
* is done. We've already requested the interrupt.
*/
WR4(&sc->sc_bas, PDC_TPR, addr);
WR4(&sc->sc_bas, PDC_TCR, sc->sc_txdatasz);
WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_TXTEN);
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
WR4(&sc->sc_bas, USART_IER, USART_CSR_ENDTX);
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
errout:
MFp4: Catchup with recent UART changes.
2006-04-06 20:47:54 +00:00
uart_unlock(sc->sc_hwmtx);
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
return (err);
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
}
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
static int
at91_usart_bus_setsig(struct uart_softc *sc, int sig)
{
uint32_t new, old, cr;
Enable hardware flow control and high speed bulk data transfer in at91 uarts. Changes to make rtc/cts flow control work... This does not turn on the builtin hardware flow control on the SoC's usart device, because that doesn't work on uart1 due to a chip erratum (they forgot to wire up pin PA21 to RTS0 internally). Instead it uses the hardware flow control logic where the tty layer calls the driver to assert and de-assert the flow control lines as needed. This prevents overruns at the tty layer (app doesn't read fast enough), but does nothing for overruns at the driver layer (interrupts not serviced fast enough). To work around the wiring problem with RTS0, the driver reassigns that pin as a GPIO and controls it manually. It only does so if given permission via hint.uart.1.use_rts0_workaround=1, to prevent accidentally driving the pin if uart1 is used without flow control (because something not related to serial IO could be wired to that pin). In addition to the RTS0 workaround, driver changes were needed in the area of reading the current set of DCE signals. A priming read is now done at attach() time, and the interrupt routine now sets SER_INT_SIGCHG when any of the DCE signals change. Without these changes, nothing could ever be transmitted, because the tty layer thought CTS was de-asserted (when in fact we had just never read the status register, and the hwsig variable was init'd to CTS de-asserted). Changes to support bulk high-speed (230kbps and higher) data reception... Allow the receive fifo size to be tuned with hint.uart.<dev>.fifo_bytes. For high speed receive, a fifo size of 1024 works well. The default is still 128 bytes if no hint is provided. Using a value larger than 384 requires a change in dev/uart/uart_core.c to size the intermediate buffer as MAX(384, 3*sc->sc_rxfifosize). Recalculate the receive timeout whenever the baud rate changes. At low baud rates (19.2kbps and below) the timeout is the number of bits in 2 characters. At higher speed it's calculated to be 500 microseconds worth of bits. The idea is to compromise between being responsive in interactive situations and not timing out prematurely during a brief pause in bulk data flow. The old fixed timeout of 1.5 characters was just 32 microseconds at 460kbps. At interrupt time, check for receiver holding register overrun status and set the corresponding status bit in the return value. When handling a buffer overrun, get a single buffer emptied and handed back to the hardware as quickly as possible, then deal with the second buffer. This at least minimizes data loss compared to the old logic that fully processed both buffers before restarting the hardware. Rewrite the logic for handling buffers after a receive timeout. The original author speculated in a comment that there may be a race with high speed data. There was, although it was rare. The code now handles all three possible scenarios on receive timeout: two empty buffers, one empty and one partial buffer, or one full and one partial buffer. Reviewed by: imp
2013-04-01 00:00:10 +00:00
struct at91_usart_softc *atsc;
atsc = (struct at91_usart_softc *)sc;
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
do {
old = sc->sc_hwsig;
new = old;
if (sig & SER_DDTR)
SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR);
if (sig & SER_DRTS)
SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS);
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
Enable hardware flow control and high speed bulk data transfer in at91 uarts. Changes to make rtc/cts flow control work... This does not turn on the builtin hardware flow control on the SoC's usart device, because that doesn't work on uart1 due to a chip erratum (they forgot to wire up pin PA21 to RTS0 internally). Instead it uses the hardware flow control logic where the tty layer calls the driver to assert and de-assert the flow control lines as needed. This prevents overruns at the tty layer (app doesn't read fast enough), but does nothing for overruns at the driver layer (interrupts not serviced fast enough). To work around the wiring problem with RTS0, the driver reassigns that pin as a GPIO and controls it manually. It only does so if given permission via hint.uart.1.use_rts0_workaround=1, to prevent accidentally driving the pin if uart1 is used without flow control (because something not related to serial IO could be wired to that pin). In addition to the RTS0 workaround, driver changes were needed in the area of reading the current set of DCE signals. A priming read is now done at attach() time, and the interrupt routine now sets SER_INT_SIGCHG when any of the DCE signals change. Without these changes, nothing could ever be transmitted, because the tty layer thought CTS was de-asserted (when in fact we had just never read the status register, and the hwsig variable was init'd to CTS de-asserted). Changes to support bulk high-speed (230kbps and higher) data reception... Allow the receive fifo size to be tuned with hint.uart.<dev>.fifo_bytes. For high speed receive, a fifo size of 1024 works well. The default is still 128 bytes if no hint is provided. Using a value larger than 384 requires a change in dev/uart/uart_core.c to size the intermediate buffer as MAX(384, 3*sc->sc_rxfifosize). Recalculate the receive timeout whenever the baud rate changes. At low baud rates (19.2kbps and below) the timeout is the number of bits in 2 characters. At higher speed it's calculated to be 500 microseconds worth of bits. The idea is to compromise between being responsive in interactive situations and not timing out prematurely during a brief pause in bulk data flow. The old fixed timeout of 1.5 characters was just 32 microseconds at 460kbps. At interrupt time, check for receiver holding register overrun status and set the corresponding status bit in the return value. When handling a buffer overrun, get a single buffer emptied and handed back to the hardware as quickly as possible, then deal with the second buffer. This at least minimizes data loss compared to the old logic that fully processed both buffers before restarting the hardware. Rewrite the logic for handling buffers after a receive timeout. The original author speculated in a comment that there may be a race with high speed data. There was, although it was rare. The code now handles all three possible scenarios on receive timeout: two empty buffers, one empty and one partial buffer, or one full and one partial buffer. Reviewed by: imp
2013-04-01 00:00:10 +00:00
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
cr = 0;
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
if (new & SER_DTR)
cr |= USART_CR_DTREN;
else
cr |= USART_CR_DTRDIS;
if (new & SER_RTS)
cr |= USART_CR_RTSEN;
else
cr |= USART_CR_RTSDIS;
Enable hardware flow control and high speed bulk data transfer in at91 uarts. Changes to make rtc/cts flow control work... This does not turn on the builtin hardware flow control on the SoC's usart device, because that doesn't work on uart1 due to a chip erratum (they forgot to wire up pin PA21 to RTS0 internally). Instead it uses the hardware flow control logic where the tty layer calls the driver to assert and de-assert the flow control lines as needed. This prevents overruns at the tty layer (app doesn't read fast enough), but does nothing for overruns at the driver layer (interrupts not serviced fast enough). To work around the wiring problem with RTS0, the driver reassigns that pin as a GPIO and controls it manually. It only does so if given permission via hint.uart.1.use_rts0_workaround=1, to prevent accidentally driving the pin if uart1 is used without flow control (because something not related to serial IO could be wired to that pin). In addition to the RTS0 workaround, driver changes were needed in the area of reading the current set of DCE signals. A priming read is now done at attach() time, and the interrupt routine now sets SER_INT_SIGCHG when any of the DCE signals change. Without these changes, nothing could ever be transmitted, because the tty layer thought CTS was de-asserted (when in fact we had just never read the status register, and the hwsig variable was init'd to CTS de-asserted). Changes to support bulk high-speed (230kbps and higher) data reception... Allow the receive fifo size to be tuned with hint.uart.<dev>.fifo_bytes. For high speed receive, a fifo size of 1024 works well. The default is still 128 bytes if no hint is provided. Using a value larger than 384 requires a change in dev/uart/uart_core.c to size the intermediate buffer as MAX(384, 3*sc->sc_rxfifosize). Recalculate the receive timeout whenever the baud rate changes. At low baud rates (19.2kbps and below) the timeout is the number of bits in 2 characters. At higher speed it's calculated to be 500 microseconds worth of bits. The idea is to compromise between being responsive in interactive situations and not timing out prematurely during a brief pause in bulk data flow. The old fixed timeout of 1.5 characters was just 32 microseconds at 460kbps. At interrupt time, check for receiver holding register overrun status and set the corresponding status bit in the return value. When handling a buffer overrun, get a single buffer emptied and handed back to the hardware as quickly as possible, then deal with the second buffer. This at least minimizes data loss compared to the old logic that fully processed both buffers before restarting the hardware. Rewrite the logic for handling buffers after a receive timeout. The original author speculated in a comment that there may be a race with high speed data. There was, although it was rare. The code now handles all three possible scenarios on receive timeout: two empty buffers, one empty and one partial buffer, or one full and one partial buffer. Reviewed by: imp
2013-04-01 00:00:10 +00:00
uart_lock(sc->sc_hwmtx);
WR4(&sc->sc_bas, USART_CR, cr);
if (atsc->flags & USE_RTS0_WORKAROUND) {
/* Signal is active-low. */
if (new & SER_RTS)
at91_pio_gpio_clear(AT91RM92_PIOA_BASE, AT91C_PIO_PA21);
else
at91_pio_gpio_set(AT91RM92_PIOA_BASE,AT91C_PIO_PA21);
}
MFp4: Catchup with recent UART changes.
2006-04-06 20:47:54 +00:00
uart_unlock(sc->sc_hwmtx);
Enable hardware flow control and high speed bulk data transfer in at91 uarts. Changes to make rtc/cts flow control work... This does not turn on the builtin hardware flow control on the SoC's usart device, because that doesn't work on uart1 due to a chip erratum (they forgot to wire up pin PA21 to RTS0 internally). Instead it uses the hardware flow control logic where the tty layer calls the driver to assert and de-assert the flow control lines as needed. This prevents overruns at the tty layer (app doesn't read fast enough), but does nothing for overruns at the driver layer (interrupts not serviced fast enough). To work around the wiring problem with RTS0, the driver reassigns that pin as a GPIO and controls it manually. It only does so if given permission via hint.uart.1.use_rts0_workaround=1, to prevent accidentally driving the pin if uart1 is used without flow control (because something not related to serial IO could be wired to that pin). In addition to the RTS0 workaround, driver changes were needed in the area of reading the current set of DCE signals. A priming read is now done at attach() time, and the interrupt routine now sets SER_INT_SIGCHG when any of the DCE signals change. Without these changes, nothing could ever be transmitted, because the tty layer thought CTS was de-asserted (when in fact we had just never read the status register, and the hwsig variable was init'd to CTS de-asserted). Changes to support bulk high-speed (230kbps and higher) data reception... Allow the receive fifo size to be tuned with hint.uart.<dev>.fifo_bytes. For high speed receive, a fifo size of 1024 works well. The default is still 128 bytes if no hint is provided. Using a value larger than 384 requires a change in dev/uart/uart_core.c to size the intermediate buffer as MAX(384, 3*sc->sc_rxfifosize). Recalculate the receive timeout whenever the baud rate changes. At low baud rates (19.2kbps and below) the timeout is the number of bits in 2 characters. At higher speed it's calculated to be 500 microseconds worth of bits. The idea is to compromise between being responsive in interactive situations and not timing out prematurely during a brief pause in bulk data flow. The old fixed timeout of 1.5 characters was just 32 microseconds at 460kbps. At interrupt time, check for receiver holding register overrun status and set the corresponding status bit in the return value. When handling a buffer overrun, get a single buffer emptied and handed back to the hardware as quickly as possible, then deal with the second buffer. This at least minimizes data loss compared to the old logic that fully processed both buffers before restarting the hardware. Rewrite the logic for handling buffers after a receive timeout. The original author speculated in a comment that there may be a race with high speed data. There was, although it was rare. The code now handles all three possible scenarios on receive timeout: two empty buffers, one empty and one partial buffer, or one full and one partial buffer. Reviewed by: imp
2013-04-01 00:00:10 +00:00
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
return (0);
}
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
static int
at91_usart_bus_receive(struct uart_softc *sc)
{
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
return (0);
}
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
static int
at91_usart_bus_param(struct uart_softc *sc, int baudrate, int databits,
int stopbits, int parity)
{
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
return (at91_usart_param(&sc->sc_bas, baudrate, databits, stopbits,
parity));
}
Fix ALT_BREAK_TO_DEBUGGER on the AT91 : The core uart code expects the receive method to actually puts the characters read into its buffers. For AT91, it's done in the ipend routine, so also check if we have the alternate break sequence here. MFC after: 3 days
2006-07-20 21:03:43 +00:00
static __inline void
at91_rx_put(struct uart_softc *sc, int key)
{
Follow up to r225203 refining break-to-debugger run-time configuration improvements: (1) Implement new model in previously missed at91 UART driver (2) Move BREAK_TO_DEBUGGER and ALT_BREAK_TO_DEBUGGER from opt_comconsole.h to opt_kdb.h (spotted by np) (3) Garbage collect now-unused opt_comconsole.h MFC after: 3 weeks Approved by: re (bz)
2011-08-27 14:24:27 +00:00
#if defined(KDB)
if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE)
kdb_alt_break(key, &sc->sc_altbrk);
Fix ALT_BREAK_TO_DEBUGGER on the AT91 : The core uart code expects the receive method to actually puts the characters read into its buffers. For AT91, it's done in the ipend routine, so also check if we have the alternate break sequence here. MFC after: 3 days
2006-07-20 21:03:43 +00:00
#endif
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
uart_rx_put(sc, key);
Fix ALT_BREAK_TO_DEBUGGER on the AT91 : The core uart code expects the receive method to actually puts the characters read into its buffers. For AT91, it's done in the ipend routine, so also check if we have the alternate break sequence here. MFC after: 3 days
2006-07-20 21:03:43 +00:00
}
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
static int
at91_usart_bus_ipend(struct uart_softc *sc)
{
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
struct at91_usart_softc *atsc;
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
struct at91_usart_rx *p;
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
int i, ipend, len;
uint32_t csr;
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
ipend = 0;
atsc = (struct at91_usart_softc *)sc;
uart_lock(sc->sc_hwmtx);
csr = RD4(&sc->sc_bas, USART_CSR);
Enable hardware flow control and high speed bulk data transfer in at91 uarts. Changes to make rtc/cts flow control work... This does not turn on the builtin hardware flow control on the SoC's usart device, because that doesn't work on uart1 due to a chip erratum (they forgot to wire up pin PA21 to RTS0 internally). Instead it uses the hardware flow control logic where the tty layer calls the driver to assert and de-assert the flow control lines as needed. This prevents overruns at the tty layer (app doesn't read fast enough), but does nothing for overruns at the driver layer (interrupts not serviced fast enough). To work around the wiring problem with RTS0, the driver reassigns that pin as a GPIO and controls it manually. It only does so if given permission via hint.uart.1.use_rts0_workaround=1, to prevent accidentally driving the pin if uart1 is used without flow control (because something not related to serial IO could be wired to that pin). In addition to the RTS0 workaround, driver changes were needed in the area of reading the current set of DCE signals. A priming read is now done at attach() time, and the interrupt routine now sets SER_INT_SIGCHG when any of the DCE signals change. Without these changes, nothing could ever be transmitted, because the tty layer thought CTS was de-asserted (when in fact we had just never read the status register, and the hwsig variable was init'd to CTS de-asserted). Changes to support bulk high-speed (230kbps and higher) data reception... Allow the receive fifo size to be tuned with hint.uart.<dev>.fifo_bytes. For high speed receive, a fifo size of 1024 works well. The default is still 128 bytes if no hint is provided. Using a value larger than 384 requires a change in dev/uart/uart_core.c to size the intermediate buffer as MAX(384, 3*sc->sc_rxfifosize). Recalculate the receive timeout whenever the baud rate changes. At low baud rates (19.2kbps and below) the timeout is the number of bits in 2 characters. At higher speed it's calculated to be 500 microseconds worth of bits. The idea is to compromise between being responsive in interactive situations and not timing out prematurely during a brief pause in bulk data flow. The old fixed timeout of 1.5 characters was just 32 microseconds at 460kbps. At interrupt time, check for receiver holding register overrun status and set the corresponding status bit in the return value. When handling a buffer overrun, get a single buffer emptied and handed back to the hardware as quickly as possible, then deal with the second buffer. This at least minimizes data loss compared to the old logic that fully processed both buffers before restarting the hardware. Rewrite the logic for handling buffers after a receive timeout. The original author speculated in a comment that there may be a race with high speed data. There was, although it was rare. The code now handles all three possible scenarios on receive timeout: two empty buffers, one empty and one partial buffer, or one full and one partial buffer. Reviewed by: imp
2013-04-01 00:00:10 +00:00
if (csr & USART_CSR_OVRE) {
WR4(&sc->sc_bas, USART_CR, USART_CR_RSTSTA);
ipend |= SER_INT_OVERRUN;
}
if (csr & USART_DCE_CHANGE_BITS)
ipend |= SER_INT_SIGCHG;
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
if (csr & USART_CSR_ENDTX) {
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
bus_dmamap_sync(atsc->tx_tag, atsc->tx_map,
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
BUS_DMASYNC_POSTWRITE);
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
bus_dmamap_unload(atsc->tx_tag, atsc->tx_map);
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
}
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
if (csr & (USART_CSR_TXRDY | USART_CSR_ENDTX)) {
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
if (sc->sc_txbusy)
ipend |= SER_INT_TXIDLE;
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
WR4(&sc->sc_bas, USART_IDR, csr & (USART_CSR_TXRDY |
USART_CSR_ENDTX));
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
}
/*
* Due to the contraints of the DMA engine present in the
* atmel chip, I can't just say I have a rx interrupt pending
* and do all the work elsewhere. I need to look at the CSR
* bits right now and do things based on them to avoid races.
*/
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
if (atsc->flags & HAS_TIMEOUT) {
if (csr & USART_CSR_RXBUFF) {
/*
Enable hardware flow control and high speed bulk data transfer in at91 uarts. Changes to make rtc/cts flow control work... This does not turn on the builtin hardware flow control on the SoC's usart device, because that doesn't work on uart1 due to a chip erratum (they forgot to wire up pin PA21 to RTS0 internally). Instead it uses the hardware flow control logic where the tty layer calls the driver to assert and de-assert the flow control lines as needed. This prevents overruns at the tty layer (app doesn't read fast enough), but does nothing for overruns at the driver layer (interrupts not serviced fast enough). To work around the wiring problem with RTS0, the driver reassigns that pin as a GPIO and controls it manually. It only does so if given permission via hint.uart.1.use_rts0_workaround=1, to prevent accidentally driving the pin if uart1 is used without flow control (because something not related to serial IO could be wired to that pin). In addition to the RTS0 workaround, driver changes were needed in the area of reading the current set of DCE signals. A priming read is now done at attach() time, and the interrupt routine now sets SER_INT_SIGCHG when any of the DCE signals change. Without these changes, nothing could ever be transmitted, because the tty layer thought CTS was de-asserted (when in fact we had just never read the status register, and the hwsig variable was init'd to CTS de-asserted). Changes to support bulk high-speed (230kbps and higher) data reception... Allow the receive fifo size to be tuned with hint.uart.<dev>.fifo_bytes. For high speed receive, a fifo size of 1024 works well. The default is still 128 bytes if no hint is provided. Using a value larger than 384 requires a change in dev/uart/uart_core.c to size the intermediate buffer as MAX(384, 3*sc->sc_rxfifosize). Recalculate the receive timeout whenever the baud rate changes. At low baud rates (19.2kbps and below) the timeout is the number of bits in 2 characters. At higher speed it's calculated to be 500 microseconds worth of bits. The idea is to compromise between being responsive in interactive situations and not timing out prematurely during a brief pause in bulk data flow. The old fixed timeout of 1.5 characters was just 32 microseconds at 460kbps. At interrupt time, check for receiver holding register overrun status and set the corresponding status bit in the return value. When handling a buffer overrun, get a single buffer emptied and handed back to the hardware as quickly as possible, then deal with the second buffer. This at least minimizes data loss compared to the old logic that fully processed both buffers before restarting the hardware. Rewrite the logic for handling buffers after a receive timeout. The original author speculated in a comment that there may be a race with high speed data. There was, although it was rare. The code now handles all three possible scenarios on receive timeout: two empty buffers, one empty and one partial buffer, or one full and one partial buffer. Reviewed by: imp
2013-04-01 00:00:10 +00:00
* We have a buffer overflow. Consume data from ping
* and give it back to the hardware before worrying
* about pong, to minimze data loss. Insert an overrun
* marker after the contents of the pong buffer.
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
*/
Enable hardware flow control and high speed bulk data transfer in at91 uarts. Changes to make rtc/cts flow control work... This does not turn on the builtin hardware flow control on the SoC's usart device, because that doesn't work on uart1 due to a chip erratum (they forgot to wire up pin PA21 to RTS0 internally). Instead it uses the hardware flow control logic where the tty layer calls the driver to assert and de-assert the flow control lines as needed. This prevents overruns at the tty layer (app doesn't read fast enough), but does nothing for overruns at the driver layer (interrupts not serviced fast enough). To work around the wiring problem with RTS0, the driver reassigns that pin as a GPIO and controls it manually. It only does so if given permission via hint.uart.1.use_rts0_workaround=1, to prevent accidentally driving the pin if uart1 is used without flow control (because something not related to serial IO could be wired to that pin). In addition to the RTS0 workaround, driver changes were needed in the area of reading the current set of DCE signals. A priming read is now done at attach() time, and the interrupt routine now sets SER_INT_SIGCHG when any of the DCE signals change. Without these changes, nothing could ever be transmitted, because the tty layer thought CTS was de-asserted (when in fact we had just never read the status register, and the hwsig variable was init'd to CTS de-asserted). Changes to support bulk high-speed (230kbps and higher) data reception... Allow the receive fifo size to be tuned with hint.uart.<dev>.fifo_bytes. For high speed receive, a fifo size of 1024 works well. The default is still 128 bytes if no hint is provided. Using a value larger than 384 requires a change in dev/uart/uart_core.c to size the intermediate buffer as MAX(384, 3*sc->sc_rxfifosize). Recalculate the receive timeout whenever the baud rate changes. At low baud rates (19.2kbps and below) the timeout is the number of bits in 2 characters. At higher speed it's calculated to be 500 microseconds worth of bits. The idea is to compromise between being responsive in interactive situations and not timing out prematurely during a brief pause in bulk data flow. The old fixed timeout of 1.5 characters was just 32 microseconds at 460kbps. At interrupt time, check for receiver holding register overrun status and set the corresponding status bit in the return value. When handling a buffer overrun, get a single buffer emptied and handed back to the hardware as quickly as possible, then deal with the second buffer. This at least minimizes data loss compared to the old logic that fully processed both buffers before restarting the hardware. Rewrite the logic for handling buffers after a receive timeout. The original author speculated in a comment that there may be a race with high speed data. There was, although it was rare. The code now handles all three possible scenarios on receive timeout: two empty buffers, one empty and one partial buffer, or one full and one partial buffer. Reviewed by: imp
2013-04-01 00:00:10 +00:00
WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS);
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
BUS_DMASYNC_POSTREAD);
for (i = 0; i < sc->sc_rxfifosz; i++)
at91_rx_put(sc, atsc->ping->buffer[i]);
Enable hardware flow control and high speed bulk data transfer in at91 uarts. Changes to make rtc/cts flow control work... This does not turn on the builtin hardware flow control on the SoC's usart device, because that doesn't work on uart1 due to a chip erratum (they forgot to wire up pin PA21 to RTS0 internally). Instead it uses the hardware flow control logic where the tty layer calls the driver to assert and de-assert the flow control lines as needed. This prevents overruns at the tty layer (app doesn't read fast enough), but does nothing for overruns at the driver layer (interrupts not serviced fast enough). To work around the wiring problem with RTS0, the driver reassigns that pin as a GPIO and controls it manually. It only does so if given permission via hint.uart.1.use_rts0_workaround=1, to prevent accidentally driving the pin if uart1 is used without flow control (because something not related to serial IO could be wired to that pin). In addition to the RTS0 workaround, driver changes were needed in the area of reading the current set of DCE signals. A priming read is now done at attach() time, and the interrupt routine now sets SER_INT_SIGCHG when any of the DCE signals change. Without these changes, nothing could ever be transmitted, because the tty layer thought CTS was de-asserted (when in fact we had just never read the status register, and the hwsig variable was init'd to CTS de-asserted). Changes to support bulk high-speed (230kbps and higher) data reception... Allow the receive fifo size to be tuned with hint.uart.<dev>.fifo_bytes. For high speed receive, a fifo size of 1024 works well. The default is still 128 bytes if no hint is provided. Using a value larger than 384 requires a change in dev/uart/uart_core.c to size the intermediate buffer as MAX(384, 3*sc->sc_rxfifosize). Recalculate the receive timeout whenever the baud rate changes. At low baud rates (19.2kbps and below) the timeout is the number of bits in 2 characters. At higher speed it's calculated to be 500 microseconds worth of bits. The idea is to compromise between being responsive in interactive situations and not timing out prematurely during a brief pause in bulk data flow. The old fixed timeout of 1.5 characters was just 32 microseconds at 460kbps. At interrupt time, check for receiver holding register overrun status and set the corresponding status bit in the return value. When handling a buffer overrun, get a single buffer emptied and handed back to the hardware as quickly as possible, then deal with the second buffer. This at least minimizes data loss compared to the old logic that fully processed both buffers before restarting the hardware. Rewrite the logic for handling buffers after a receive timeout. The original author speculated in a comment that there may be a race with high speed data. There was, although it was rare. The code now handles all three possible scenarios on receive timeout: two empty buffers, one empty and one partial buffer, or one full and one partial buffer. Reviewed by: imp
2013-04-01 00:00:10 +00:00
bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
BUS_DMASYNC_PREREAD);
WR4(&sc->sc_bas, PDC_RPR, atsc->ping->pa);
WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
bus_dmamap_sync(atsc->rx_tag, atsc->pong->map,
BUS_DMASYNC_POSTREAD);
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
for (i = 0; i < sc->sc_rxfifosz; i++)
at91_rx_put(sc, atsc->pong->buffer[i]);
uart_rx_put(sc, UART_STAT_OVERRUN);
bus_dmamap_sync(atsc->rx_tag, atsc->pong->map,
BUS_DMASYNC_PREREAD);
WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
ipend |= SER_INT_RXREADY;
} else if (csr & USART_CSR_ENDRX) {
/*
Enable hardware flow control and high speed bulk data transfer in at91 uarts. Changes to make rtc/cts flow control work... This does not turn on the builtin hardware flow control on the SoC's usart device, because that doesn't work on uart1 due to a chip erratum (they forgot to wire up pin PA21 to RTS0 internally). Instead it uses the hardware flow control logic where the tty layer calls the driver to assert and de-assert the flow control lines as needed. This prevents overruns at the tty layer (app doesn't read fast enough), but does nothing for overruns at the driver layer (interrupts not serviced fast enough). To work around the wiring problem with RTS0, the driver reassigns that pin as a GPIO and controls it manually. It only does so if given permission via hint.uart.1.use_rts0_workaround=1, to prevent accidentally driving the pin if uart1 is used without flow control (because something not related to serial IO could be wired to that pin). In addition to the RTS0 workaround, driver changes were needed in the area of reading the current set of DCE signals. A priming read is now done at attach() time, and the interrupt routine now sets SER_INT_SIGCHG when any of the DCE signals change. Without these changes, nothing could ever be transmitted, because the tty layer thought CTS was de-asserted (when in fact we had just never read the status register, and the hwsig variable was init'd to CTS de-asserted). Changes to support bulk high-speed (230kbps and higher) data reception... Allow the receive fifo size to be tuned with hint.uart.<dev>.fifo_bytes. For high speed receive, a fifo size of 1024 works well. The default is still 128 bytes if no hint is provided. Using a value larger than 384 requires a change in dev/uart/uart_core.c to size the intermediate buffer as MAX(384, 3*sc->sc_rxfifosize). Recalculate the receive timeout whenever the baud rate changes. At low baud rates (19.2kbps and below) the timeout is the number of bits in 2 characters. At higher speed it's calculated to be 500 microseconds worth of bits. The idea is to compromise between being responsive in interactive situations and not timing out prematurely during a brief pause in bulk data flow. The old fixed timeout of 1.5 characters was just 32 microseconds at 460kbps. At interrupt time, check for receiver holding register overrun status and set the corresponding status bit in the return value. When handling a buffer overrun, get a single buffer emptied and handed back to the hardware as quickly as possible, then deal with the second buffer. This at least minimizes data loss compared to the old logic that fully processed both buffers before restarting the hardware. Rewrite the logic for handling buffers after a receive timeout. The original author speculated in a comment that there may be a race with high speed data. There was, although it was rare. The code now handles all three possible scenarios on receive timeout: two empty buffers, one empty and one partial buffer, or one full and one partial buffer. Reviewed by: imp
2013-04-01 00:00:10 +00:00
* Consume data from ping of ping pong buffer, but leave
* current pong in place, as it has become the new ping.
* We need to copy data and setup the old ping as the
* new pong when we're done.
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
*/
bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
BUS_DMASYNC_POSTREAD);
for (i = 0; i < sc->sc_rxfifosz; i++)
at91_rx_put(sc, atsc->ping->buffer[i]);
p = atsc->ping;
atsc->ping = atsc->pong;
atsc->pong = p;
bus_dmamap_sync(atsc->rx_tag, atsc->pong->map,
BUS_DMASYNC_PREREAD);
WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
ipend |= SER_INT_RXREADY;
} else if (csr & USART_CSR_TIMEOUT) {
/*
Enable hardware flow control and high speed bulk data transfer in at91 uarts. Changes to make rtc/cts flow control work... This does not turn on the builtin hardware flow control on the SoC's usart device, because that doesn't work on uart1 due to a chip erratum (they forgot to wire up pin PA21 to RTS0 internally). Instead it uses the hardware flow control logic where the tty layer calls the driver to assert and de-assert the flow control lines as needed. This prevents overruns at the tty layer (app doesn't read fast enough), but does nothing for overruns at the driver layer (interrupts not serviced fast enough). To work around the wiring problem with RTS0, the driver reassigns that pin as a GPIO and controls it manually. It only does so if given permission via hint.uart.1.use_rts0_workaround=1, to prevent accidentally driving the pin if uart1 is used without flow control (because something not related to serial IO could be wired to that pin). In addition to the RTS0 workaround, driver changes were needed in the area of reading the current set of DCE signals. A priming read is now done at attach() time, and the interrupt routine now sets SER_INT_SIGCHG when any of the DCE signals change. Without these changes, nothing could ever be transmitted, because the tty layer thought CTS was de-asserted (when in fact we had just never read the status register, and the hwsig variable was init'd to CTS de-asserted). Changes to support bulk high-speed (230kbps and higher) data reception... Allow the receive fifo size to be tuned with hint.uart.<dev>.fifo_bytes. For high speed receive, a fifo size of 1024 works well. The default is still 128 bytes if no hint is provided. Using a value larger than 384 requires a change in dev/uart/uart_core.c to size the intermediate buffer as MAX(384, 3*sc->sc_rxfifosize). Recalculate the receive timeout whenever the baud rate changes. At low baud rates (19.2kbps and below) the timeout is the number of bits in 2 characters. At higher speed it's calculated to be 500 microseconds worth of bits. The idea is to compromise between being responsive in interactive situations and not timing out prematurely during a brief pause in bulk data flow. The old fixed timeout of 1.5 characters was just 32 microseconds at 460kbps. At interrupt time, check for receiver holding register overrun status and set the corresponding status bit in the return value. When handling a buffer overrun, get a single buffer emptied and handed back to the hardware as quickly as possible, then deal with the second buffer. This at least minimizes data loss compared to the old logic that fully processed both buffers before restarting the hardware. Rewrite the logic for handling buffers after a receive timeout. The original author speculated in a comment that there may be a race with high speed data. There was, although it was rare. The code now handles all three possible scenarios on receive timeout: two empty buffers, one empty and one partial buffer, or one full and one partial buffer. Reviewed by: imp
2013-04-01 00:00:10 +00:00
* On a timeout, one of the following applies:
* 1. Two empty buffers. The last received byte exactly
* filled a buffer, causing an ENDTX that got
* processed earlier; no new bytes have arrived.
* 2. Ping buffer contains some data and pong is empty.
* This should be the most common timeout condition.
* 3. Ping buffer is full and pong is now being filled.
* This is exceedingly rare; it can happen only if
* the ping buffer is almost full when a timeout is
* signaled, and then dataflow resumes and the ping
* buffer filled up between the time we read the
* status register above and the point where the
* RXTDIS takes effect here. Yes, it can happen.
* Because dataflow can resume at any time following a
* timeout (it may have already resumed before we get
* here), it's important to minimize the time the PDC is
* disabled -- just long enough to take the ping buffer
* out of service (so we can consume it) and install the
* pong buffer as the active one. Note that in case 3
* the hardware has already done the ping-pong swap.
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
*/
WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTDIS);
Enable hardware flow control and high speed bulk data transfer in at91 uarts. Changes to make rtc/cts flow control work... This does not turn on the builtin hardware flow control on the SoC's usart device, because that doesn't work on uart1 due to a chip erratum (they forgot to wire up pin PA21 to RTS0 internally). Instead it uses the hardware flow control logic where the tty layer calls the driver to assert and de-assert the flow control lines as needed. This prevents overruns at the tty layer (app doesn't read fast enough), but does nothing for overruns at the driver layer (interrupts not serviced fast enough). To work around the wiring problem with RTS0, the driver reassigns that pin as a GPIO and controls it manually. It only does so if given permission via hint.uart.1.use_rts0_workaround=1, to prevent accidentally driving the pin if uart1 is used without flow control (because something not related to serial IO could be wired to that pin). In addition to the RTS0 workaround, driver changes were needed in the area of reading the current set of DCE signals. A priming read is now done at attach() time, and the interrupt routine now sets SER_INT_SIGCHG when any of the DCE signals change. Without these changes, nothing could ever be transmitted, because the tty layer thought CTS was de-asserted (when in fact we had just never read the status register, and the hwsig variable was init'd to CTS de-asserted). Changes to support bulk high-speed (230kbps and higher) data reception... Allow the receive fifo size to be tuned with hint.uart.<dev>.fifo_bytes. For high speed receive, a fifo size of 1024 works well. The default is still 128 bytes if no hint is provided. Using a value larger than 384 requires a change in dev/uart/uart_core.c to size the intermediate buffer as MAX(384, 3*sc->sc_rxfifosize). Recalculate the receive timeout whenever the baud rate changes. At low baud rates (19.2kbps and below) the timeout is the number of bits in 2 characters. At higher speed it's calculated to be 500 microseconds worth of bits. The idea is to compromise between being responsive in interactive situations and not timing out prematurely during a brief pause in bulk data flow. The old fixed timeout of 1.5 characters was just 32 microseconds at 460kbps. At interrupt time, check for receiver holding register overrun status and set the corresponding status bit in the return value. When handling a buffer overrun, get a single buffer emptied and handed back to the hardware as quickly as possible, then deal with the second buffer. This at least minimizes data loss compared to the old logic that fully processed both buffers before restarting the hardware. Rewrite the logic for handling buffers after a receive timeout. The original author speculated in a comment that there may be a race with high speed data. There was, although it was rare. The code now handles all three possible scenarios on receive timeout: two empty buffers, one empty and one partial buffer, or one full and one partial buffer. Reviewed by: imp
2013-04-01 00:00:10 +00:00
if (RD4(&sc->sc_bas, PDC_RNCR) == 0) {
len = sc->sc_rxfifosz;
} else {
len = sc->sc_rxfifosz - RD4(&sc->sc_bas, PDC_RCR);
WR4(&sc->sc_bas, PDC_RPR, atsc->pong->pa);
WR4(&sc->sc_bas, PDC_RCR, sc->sc_rxfifosz);
WR4(&sc->sc_bas, PDC_RNCR, 0);
}
WR4(&sc->sc_bas, USART_CR, USART_CR_STTTO);
WR4(&sc->sc_bas, PDC_PTCR, PDC_PTCR_RXTEN);
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
BUS_DMASYNC_POSTREAD);
for (i = 0; i < len; i++)
at91_rx_put(sc, atsc->ping->buffer[i]);
bus_dmamap_sync(atsc->rx_tag, atsc->ping->map,
BUS_DMASYNC_PREREAD);
Enable hardware flow control and high speed bulk data transfer in at91 uarts. Changes to make rtc/cts flow control work... This does not turn on the builtin hardware flow control on the SoC's usart device, because that doesn't work on uart1 due to a chip erratum (they forgot to wire up pin PA21 to RTS0 internally). Instead it uses the hardware flow control logic where the tty layer calls the driver to assert and de-assert the flow control lines as needed. This prevents overruns at the tty layer (app doesn't read fast enough), but does nothing for overruns at the driver layer (interrupts not serviced fast enough). To work around the wiring problem with RTS0, the driver reassigns that pin as a GPIO and controls it manually. It only does so if given permission via hint.uart.1.use_rts0_workaround=1, to prevent accidentally driving the pin if uart1 is used without flow control (because something not related to serial IO could be wired to that pin). In addition to the RTS0 workaround, driver changes were needed in the area of reading the current set of DCE signals. A priming read is now done at attach() time, and the interrupt routine now sets SER_INT_SIGCHG when any of the DCE signals change. Without these changes, nothing could ever be transmitted, because the tty layer thought CTS was de-asserted (when in fact we had just never read the status register, and the hwsig variable was init'd to CTS de-asserted). Changes to support bulk high-speed (230kbps and higher) data reception... Allow the receive fifo size to be tuned with hint.uart.<dev>.fifo_bytes. For high speed receive, a fifo size of 1024 works well. The default is still 128 bytes if no hint is provided. Using a value larger than 384 requires a change in dev/uart/uart_core.c to size the intermediate buffer as MAX(384, 3*sc->sc_rxfifosize). Recalculate the receive timeout whenever the baud rate changes. At low baud rates (19.2kbps and below) the timeout is the number of bits in 2 characters. At higher speed it's calculated to be 500 microseconds worth of bits. The idea is to compromise between being responsive in interactive situations and not timing out prematurely during a brief pause in bulk data flow. The old fixed timeout of 1.5 characters was just 32 microseconds at 460kbps. At interrupt time, check for receiver holding register overrun status and set the corresponding status bit in the return value. When handling a buffer overrun, get a single buffer emptied and handed back to the hardware as quickly as possible, then deal with the second buffer. This at least minimizes data loss compared to the old logic that fully processed both buffers before restarting the hardware. Rewrite the logic for handling buffers after a receive timeout. The original author speculated in a comment that there may be a race with high speed data. There was, although it was rare. The code now handles all three possible scenarios on receive timeout: two empty buffers, one empty and one partial buffer, or one full and one partial buffer. Reviewed by: imp
2013-04-01 00:00:10 +00:00
p = atsc->ping;
atsc->ping = atsc->pong;
atsc->pong = p;
WR4(&sc->sc_bas, PDC_RNPR, atsc->pong->pa);
WR4(&sc->sc_bas, PDC_RNCR, sc->sc_rxfifosz);
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
ipend |= SER_INT_RXREADY;
}
} else if (csr & USART_CSR_RXRDY) {
/*
* We have another charater in a device that doesn't support
* timeouts, so we do it one character at a time.
*/
Fix ALT_BREAK_TO_DEBUGGER on the AT91 : The core uart code expects the receive method to actually puts the characters read into its buffers. For AT91, it's done in the ipend routine, so also check if we have the alternate break sequence here. MFC after: 3 days
2006-07-20 21:03:43 +00:00
at91_rx_put(sc, RD4(&sc->sc_bas, USART_RHR) & 0xff);
Get this to compile with the recent UART changes.
2006-02-27 23:19:13 +00:00
ipend |= SER_INT_RXREADY;
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
}
MFp4: Handle break interrupts (it seems to only work for USART, not DBGU).
2006-03-22 21:16:09 +00:00
if (csr & USART_CSR_RXBRK) {
ipend |= SER_INT_BREAK;
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
WR4(&sc->sc_bas, USART_CR, USART_CR_RSTSTA);
MFp4: Handle break interrupts (it seems to only work for USART, not DBGU).
2006-03-22 21:16:09 +00:00
}
MFp4: Catchup with recent UART changes.
2006-04-06 20:47:54 +00:00
uart_unlock(sc->sc_hwmtx);
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
return (ipend);
}
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
static int
at91_usart_bus_flush(struct uart_softc *sc, int what)
{
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
return (0);
}
static int
at91_usart_bus_getsig(struct uart_softc *sc)
{
Enable hardware flow control and high speed bulk data transfer in at91 uarts. Changes to make rtc/cts flow control work... This does not turn on the builtin hardware flow control on the SoC's usart device, because that doesn't work on uart1 due to a chip erratum (they forgot to wire up pin PA21 to RTS0 internally). Instead it uses the hardware flow control logic where the tty layer calls the driver to assert and de-assert the flow control lines as needed. This prevents overruns at the tty layer (app doesn't read fast enough), but does nothing for overruns at the driver layer (interrupts not serviced fast enough). To work around the wiring problem with RTS0, the driver reassigns that pin as a GPIO and controls it manually. It only does so if given permission via hint.uart.1.use_rts0_workaround=1, to prevent accidentally driving the pin if uart1 is used without flow control (because something not related to serial IO could be wired to that pin). In addition to the RTS0 workaround, driver changes were needed in the area of reading the current set of DCE signals. A priming read is now done at attach() time, and the interrupt routine now sets SER_INT_SIGCHG when any of the DCE signals change. Without these changes, nothing could ever be transmitted, because the tty layer thought CTS was de-asserted (when in fact we had just never read the status register, and the hwsig variable was init'd to CTS de-asserted). Changes to support bulk high-speed (230kbps and higher) data reception... Allow the receive fifo size to be tuned with hint.uart.<dev>.fifo_bytes. For high speed receive, a fifo size of 1024 works well. The default is still 128 bytes if no hint is provided. Using a value larger than 384 requires a change in dev/uart/uart_core.c to size the intermediate buffer as MAX(384, 3*sc->sc_rxfifosize). Recalculate the receive timeout whenever the baud rate changes. At low baud rates (19.2kbps and below) the timeout is the number of bits in 2 characters. At higher speed it's calculated to be 500 microseconds worth of bits. The idea is to compromise between being responsive in interactive situations and not timing out prematurely during a brief pause in bulk data flow. The old fixed timeout of 1.5 characters was just 32 microseconds at 460kbps. At interrupt time, check for receiver holding register overrun status and set the corresponding status bit in the return value. When handling a buffer overrun, get a single buffer emptied and handed back to the hardware as quickly as possible, then deal with the second buffer. This at least minimizes data loss compared to the old logic that fully processed both buffers before restarting the hardware. Rewrite the logic for handling buffers after a receive timeout. The original author speculated in a comment that there may be a race with high speed data. There was, although it was rare. The code now handles all three possible scenarios on receive timeout: two empty buffers, one empty and one partial buffer, or one full and one partial buffer. Reviewed by: imp
2013-04-01 00:00:10 +00:00
uint32_t csr, new, old, sig;
/*
* Note that the atmel channel status register DCE status bits reflect
* the electrical state of the lines, not the logical state. Since they
* are logically active-low signals, we invert the tests here.
*/
do {
old = sc->sc_hwsig;
sig = old;
csr = RD4(&sc->sc_bas, USART_CSR);
SIGCHG(!(csr & USART_CSR_DSR), sig, SER_DSR, SER_DDSR);
SIGCHG(!(csr & USART_CSR_CTS), sig, SER_CTS, SER_DCTS);
SIGCHG(!(csr & USART_CSR_DCD), sig, SER_DCD, SER_DDCD);
SIGCHG(!(csr & USART_CSR_RI), sig, SER_RI, SER_DRI);
new = sig & ~SER_MASK_DELTA;
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
return (sig);
}
static int
at91_usart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
{
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
switch (request) {
case UART_IOCTL_BREAK:
case UART_IOCTL_IFLOW:
case UART_IOCTL_OFLOW:
break;
case UART_IOCTL_BAUD:
if_ate.c: * Support for sam9 "EMAC" controller. * Support for rmii interface to phy. at91.c & at91sam9.c: * Eliminate separate at91sam9.c file. * Add new devices to at91sam9_devs table. at91_machdep.c & at at91sam9_machdep.c: * Automatic chip type determination. * Remove compile time chip dependencies. * Eliminate separate at91sam9_machdep.c file. at91_pmc.c: * Corrected support for all of the sam926? and sam9g20 chips. * Remove compile time chip dependencies. My apologies to Greg for taking so long to take care of it.
2010-10-06 22:25:21 +00:00
/* only if we know our master clock rate */
if (DEFAULT_RCLK != 0)
WR4(&sc->sc_bas, USART_BRGR,
- Add missing locking in at91_usart_getc(). - Align the RX buffers on the cache line size, otherwise the requirement of partial cache line flushes on every are pretty much guaranteed. [1] - Make the code setting the RX timeout match its comment (apparently, start and stop bits were missed in the previous calculation). [1] - Cover the busdma operations in at91_usart_bus_{ipend,transmit}() with the hardware mutex, too, so these don't race against each other. - In at91_usart_bus_ipend(), reduce duplication in the code dealing with TX interrupts. - In at91_usart_bus_ipend(), turn the code dealing with RX interrupts into an else-if cascade in order reduce its complexity and to improve its run-time behavior. - In at91_usart_bus_ipend(), add missing BUS_DMASYNC_PREREAD calls on the RX buffer map before handing things over to the hardware again. [1] - In at91_usart_bus_getsig(), used a variable of sufficient width for storing the contents of USART_CSR. - Use KOBJMETHOD_END. - Remove an unused header. Submitted by: Ian Lepore [1] Reviewed by: Ian Lepore MFC after: 1 week
2012-05-01 20:42:03 +00:00
BAUD2DIVISOR(*(int *)data));
MFp4: Make serial ports more robust and reliable. Make non-console ports work. This might have broken skyeye stuff. o Introduce ping-pong receive buffers. o Use DMA to copy characters directly into memory. o Support baud rates other than 115200 o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used, which caused dropped characters when received in bursts). o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2 stop bits were requested. o Actually update line parameters. o Fix comments o Move init into attach o Tweaks to TX interrupt registers to get them reliable and non-storming. o harvest data in ipend since the latency between it and the callback was too long. This likely is how it should be, I don't know why I deferred things to the callback before. o disable all interrupts in console init. We don't want interrupts until we turn on an ISR. o cosmetic tweaks o Automatically detect of the TIMEOUT interrupt is supported. If so, use it so we get better CPU utilization. Otherwise do a character at a time RX. Good news here is that it seems we have enough CPU and low enough fast interrupt latency to do this reliably. o Don't read USART_CR. It is a write-only register. o start to implement bus_ioctl. Do BAUD now...
2006-07-02 03:45:33 +00:00
return (0);
}
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
return (EINVAL);
}
Don't expose the uart_ops structure directly, but instead have it obtained through the uart_class structure. This allows us to declare the uart_class structure as weak and as such allows us to reference it even when it's not compiled-in. It also allows is to get the uart_ops structure by name, which makes it possible to implement the dt tag handling in uart_getenv(). The side-effect of all this is that we're using the uart_class structure more consistently which means that we now also have access to the size of the bus space block needed by the hardware when we map the bus space, eliminating any hardcoding.
2007-04-02 22:00:22 +00:00
Connect NAND for the SAM9260EK eval board, as well as the HotE HL-201. # expect more refinement as do more boards.
2014-01-19 17:59:34 +00:00
static void
at91_usart_bus_grab(struct uart_softc *sc)
{
uart_lock(sc->sc_hwmtx);
WR4(&sc->sc_bas, USART_IDR, USART_CSR_RXRDY);
uart_unlock(sc->sc_hwmtx);
}
static void
at91_usart_bus_ungrab(struct uart_softc *sc)
{
uart_lock(sc->sc_hwmtx);
WR4(&sc->sc_bas, USART_IER, USART_CSR_RXRDY);
uart_unlock(sc->sc_hwmtx);
}
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
struct uart_class at91_usart_class = {
Don't expose the uart_ops structure directly, but instead have it obtained through the uart_class structure. This allows us to declare the uart_class structure as weak and as such allows us to reference it even when it's not compiled-in. It also allows is to get the uart_ops structure by name, which makes it possible to implement the dt tag handling in uart_getenv(). The side-effect of all this is that we're using the uart_class structure more consistently which means that we now also have access to the size of the bus space block needed by the hardware when we map the bus space, eliminating any hardcoding.
2007-04-02 22:00:22 +00:00
"at91_usart",
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
at91_usart_methods,
Optimize the TX side of the part by using the PDC to move bytes out to the wire. This increases the speed considerably. Start to put infrastructure in place to do RX side, but that requires more study before it can be done.
2006-04-06 04:27:19 +00:00
sizeof(struct at91_usart_softc),
Don't expose the uart_ops structure directly, but instead have it obtained through the uart_class structure. This allows us to declare the uart_class structure as weak and as such allows us to reference it even when it's not compiled-in. It also allows is to get the uart_ops structure by name, which makes it possible to implement the dt tag handling in uart_getenv(). The side-effect of all this is that we're using the uart_class structure more consistently which means that we now also have access to the size of the bus space block needed by the hardware when we map the bus space, eliminating any hardcoding.
2007-04-02 22:00:22 +00:00
.uc_ops = &at91_usart_ops,
Migrate towards using at91_master_clock. Initialize the clocks for the serial port class when we set the devclass since it is now no-longer a compile time constant. Eliminate the pci include, as it isn't relevant or necessary.
2009-01-22 21:56:41 +00:00
.uc_range = 8
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
};
Reference in New Issue Copy Permalink