1997-05-26 17:58:27 +00:00
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/*
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* from: vector.s, 386BSD 0.1 unknown origin
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1999-08-28 01:08:13 +00:00
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* $FreeBSD$
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1997-05-26 17:58:27 +00:00
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*/
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1997-08-10 20:59:07 +00:00
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#include <machine/apic.h>
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1997-07-28 03:59:54 +00:00
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#include <machine/smp.h>
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1997-08-10 20:59:07 +00:00
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1997-07-18 21:27:53 +00:00
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#include "i386/isa/intr_machdep.h"
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1997-06-27 23:48:05 +00:00
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1997-05-26 17:58:27 +00:00
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/* convert an absolute IRQ# into a bitmask */
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#define IRQ_BIT(irq_num) (1 << (irq_num))
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/* make an index into the IO APIC from the IRQ# */
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#define REDTBL_IDX(irq_num) (0x10 + ((irq_num) * 2))
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2000-10-06 02:20:21 +00:00
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/*
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*
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*/
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#define PUSH_FRAME \
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pushl $0 ; /* dummy error code */ \
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pushl $0 ; /* dummy trap type */ \
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pushal ; \
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pushl %ds ; /* save data and extra segments ... */ \
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pushl %es ; \
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pushl %fs
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#define POP_FRAME \
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popl %fs ; \
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popl %es ; \
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popl %ds ; \
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popal ; \
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addl $4+4,%esp
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1997-08-20 05:25:48 +00:00
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1997-05-26 17:58:27 +00:00
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/*
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2000-09-07 01:33:02 +00:00
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* Macros for interrupt entry, call to handler, and exit.
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1997-05-26 17:58:27 +00:00
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*/
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#define FAST_INTR(irq_num, vec_name) \
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.text ; \
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SUPERALIGN_TEXT ; \
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IDTVEC(vec_name) ; \
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2000-10-06 02:20:21 +00:00
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PUSH_FRAME ; \
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1997-05-26 17:58:27 +00:00
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movl $KDSEL,%eax ; \
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2000-05-10 01:24:23 +00:00
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mov %ax,%ds ; \
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2000-10-06 02:20:21 +00:00
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mov %ax,%es ; \
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1999-04-28 01:04:33 +00:00
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movl $KPSEL,%eax ; \
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2000-05-10 01:24:23 +00:00
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mov %ax,%fs ; \
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2000-10-06 02:20:21 +00:00
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FAKE_MCOUNT(13*4(%esp)) ; \
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2001-01-21 19:25:07 +00:00
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movl PCPU(CURPROC),%ebx ; \
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incl P_INTR_NESTING_LEVEL(%ebx) ; \
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2001-02-25 06:29:04 +00:00
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pushl intr_unit + (irq_num) * 4 ; \
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call *intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \
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1997-08-20 05:25:48 +00:00
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addl $4, %esp ; \
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2001-02-25 06:29:04 +00:00
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movl $0, lapic+LA_EOI ; \
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1997-08-20 05:25:48 +00:00
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lock ; \
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2001-02-25 06:29:04 +00:00
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incl cnt+V_INTR ; /* book-keeping can wait */ \
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movl intr_countp + (irq_num) * 4, %eax ; \
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1997-08-20 05:25:48 +00:00
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lock ; \
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incl (%eax) ; \
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2001-01-21 19:25:07 +00:00
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decl P_INTR_NESTING_LEVEL(%ebx) ; \
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1997-08-20 05:25:48 +00:00
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MEXITCOUNT ; \
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2001-02-25 06:29:04 +00:00
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jmp doreti
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1997-08-21 05:08:25 +00:00
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1998-09-06 22:41:42 +00:00
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#define IOAPICADDR(irq_num) CNAME(int_to_apicintpin) + 16 * (irq_num) + 8
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#define REDIRIDX(irq_num) CNAME(int_to_apicintpin) + 16 * (irq_num) + 12
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1998-03-03 22:56:30 +00:00
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#define MASK_IRQ(irq_num) \
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1997-09-07 22:04:09 +00:00
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IMASK_LOCK ; /* into critical reg */ \
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2001-02-25 06:29:04 +00:00
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testl $IRQ_BIT(irq_num), apic_imen ; \
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1998-03-03 22:56:30 +00:00
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jne 7f ; /* masked, don't mask */ \
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2001-02-25 06:29:04 +00:00
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orl $IRQ_BIT(irq_num), apic_imen ; /* set the mask bit */ \
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1998-09-06 22:41:42 +00:00
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movl IOAPICADDR(irq_num), %ecx ; /* ioapic addr */ \
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movl REDIRIDX(irq_num), %eax ; /* get the index */ \
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movl %eax, (%ecx) ; /* write the index */ \
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1997-08-21 05:08:25 +00:00
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movl IOAPIC_WINDOW(%ecx), %eax ; /* current value */ \
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orl $IOART_INTMASK, %eax ; /* set the mask */ \
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movl %eax, IOAPIC_WINDOW(%ecx) ; /* new value */ \
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1998-03-03 22:56:30 +00:00
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7: ; /* already masked */ \
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IMASK_UNLOCK
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/*
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* Test to see whether we are handling an edge or level triggered INT.
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* Level-triggered INTs must still be masked as we don't clear the source,
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* and the EOI cycle would cause redundant INTs to occur.
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*/
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#define MASK_LEVEL_IRQ(irq_num) \
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2001-02-25 06:29:04 +00:00
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testl $IRQ_BIT(irq_num), apic_pin_trigger ; \
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1998-03-03 22:56:30 +00:00
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jz 9f ; /* edge, don't mask */ \
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MASK_IRQ(irq_num) ; \
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9:
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1997-08-21 05:08:25 +00:00
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1998-03-03 22:56:30 +00:00
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#ifdef APIC_INTR_REORDER
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#define EOI_IRQ(irq_num) \
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2001-02-25 06:29:04 +00:00
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movl apic_isrbit_location + 8 * (irq_num), %eax ; \
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1998-03-03 22:56:30 +00:00
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movl (%eax), %eax ; \
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2001-02-25 06:29:04 +00:00
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testl apic_isrbit_location + 4 + 8 * (irq_num), %eax ; \
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1998-03-03 22:56:30 +00:00
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jz 9f ; /* not active */ \
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2001-02-25 06:29:04 +00:00
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movl $0, lapic+LA_EOI ; \
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1998-03-03 22:56:30 +00:00
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9:
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#else
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#define EOI_IRQ(irq_num) \
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2001-02-25 06:29:04 +00:00
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testl $IRQ_BIT(irq_num), lapic+LA_ISR1; \
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1998-03-03 22:56:30 +00:00
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jz 9f ; /* not active */ \
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2001-02-25 06:29:04 +00:00
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movl $0, lapic+LA_EOI; \
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1998-03-03 22:56:30 +00:00
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9:
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#endif
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1997-08-21 05:08:25 +00:00
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/*
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2000-09-07 01:33:02 +00:00
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* Test to see if the source is currently masked, clear if so.
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1997-08-21 05:08:25 +00:00
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*/
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#define UNMASK_IRQ(irq_num) \
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IMASK_LOCK ; /* into critical reg */ \
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testl $IRQ_BIT(irq_num), _apic_imen ; \
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1998-03-03 22:56:30 +00:00
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je 7f ; /* bit clear, not masked */ \
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1997-08-21 05:08:25 +00:00
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andl $~IRQ_BIT(irq_num), _apic_imen ;/* clear mask bit */ \
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2000-12-04 21:15:14 +00:00
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movl IOAPICADDR(irq_num), %ecx ; /* ioapic addr */ \
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1998-09-06 22:41:42 +00:00
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movl REDIRIDX(irq_num), %eax ; /* get the index */ \
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2000-12-04 21:15:14 +00:00
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movl %eax, (%ecx) ; /* write the index */ \
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movl IOAPIC_WINDOW(%ecx), %eax ; /* current value */ \
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andl $~IOART_INTMASK, %eax ; /* clear the mask */ \
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movl %eax, IOAPIC_WINDOW(%ecx) ; /* new value */ \
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7: ; /* already unmasked */ \
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1997-08-21 05:08:25 +00:00
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IMASK_UNLOCK
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2000-09-07 01:33:02 +00:00
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/*
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* Slow, threaded interrupts.
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*
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* XXX Most of the parameters here are obsolete. Fix this when we're
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* done.
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* XXX we really shouldn't return via doreti if we just schedule the
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* interrupt handler and don't run anything. We could just do an
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* iret. FIXME.
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*/
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1999-05-28 14:08:59 +00:00
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#define INTR(irq_num, vec_name, maybe_extra_ipending) \
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1997-08-29 18:45:23 +00:00
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.text ; \
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SUPERALIGN_TEXT ; \
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2001-01-19 10:51:13 +00:00
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/* _XintrNN: entry point used by IDT/HWIs via _vec[]. */ \
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1997-08-29 18:45:23 +00:00
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IDTVEC(vec_name) ; \
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PUSH_FRAME ; \
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movl $KDSEL, %eax ; /* reload with kernel's data segment */ \
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2000-05-10 01:24:23 +00:00
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mov %ax, %ds ; \
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mov %ax, %es ; \
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1999-04-28 01:04:33 +00:00
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movl $KPSEL, %eax ; \
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2000-05-10 01:24:23 +00:00
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mov %ax, %fs ; \
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1999-05-28 14:08:59 +00:00
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; \
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maybe_extra_ipending ; \
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1997-08-29 18:45:23 +00:00
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; \
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1998-03-03 22:56:30 +00:00
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MASK_LEVEL_IRQ(irq_num) ; \
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EOI_IRQ(irq_num) ; \
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0: ; \
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2001-01-21 19:25:07 +00:00
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movl PCPU(CURPROC),%ebx ; \
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incl P_INTR_NESTING_LEVEL(%ebx) ; \
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1997-09-07 22:04:09 +00:00
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; \
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/* entry point used by doreti_unpend for HWIs. */ \
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1997-08-29 18:45:23 +00:00
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__CONCAT(Xresume,irq_num): ; \
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1999-04-28 01:04:33 +00:00
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FAKE_MCOUNT(13*4(%esp)) ; /* XXX avoid dbl cnt */ \
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2000-09-07 01:33:02 +00:00
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pushl $irq_num; /* pass the IRQ */ \
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2001-02-25 06:29:04 +00:00
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call sched_ithd ; \
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2000-09-07 01:33:02 +00:00
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addl $4, %esp ; /* discard the parameter */ \
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1997-08-21 05:08:25 +00:00
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; \
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2001-01-21 19:25:07 +00:00
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decl P_INTR_NESTING_LEVEL(%ebx) ; \
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1997-05-26 17:58:27 +00:00
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MEXITCOUNT ; \
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2001-02-25 06:29:04 +00:00
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jmp doreti
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1997-05-26 17:58:27 +00:00
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1997-07-13 01:18:51 +00:00
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/*
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* Handle "spurious INTerrupts".
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* Notes:
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* This is different than the "spurious INTerrupt" generated by an
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* 8259 PIC for missing INTs. See the APIC documentation for details.
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* This routine should NOT do an 'EOI' cycle.
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*/
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.text
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SUPERALIGN_TEXT
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2001-02-25 06:29:04 +00:00
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.globl Xspuriousint
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Xspuriousint:
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1997-07-13 01:18:51 +00:00
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/* No EOI cycle used here */
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iret
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1997-07-06 23:32:38 +00:00
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/*
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* Handle TLB shootdowns.
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*/
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1997-05-26 17:58:27 +00:00
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.text
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SUPERALIGN_TEXT
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2001-02-25 06:29:04 +00:00
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.globl Xinvltlb
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Xinvltlb:
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1997-05-26 17:58:27 +00:00
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pushl %eax
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1997-07-06 23:32:38 +00:00
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#ifdef COUNT_XINVLTLB_HITS
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1999-04-28 01:04:33 +00:00
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pushl %fs
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movl $KPSEL, %eax
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2000-05-10 01:24:23 +00:00
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mov %ax, %fs
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2000-12-13 09:23:53 +00:00
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movl PCPU(CPUID), %eax
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1999-04-28 01:04:33 +00:00
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popl %fs
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1997-07-06 23:32:38 +00:00
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ss
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incl _xhits(,%eax,4)
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#endif /* COUNT_XINVLTLB_HITS */
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1997-05-26 17:58:27 +00:00
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movl %cr3, %eax /* invalidate the TLB */
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movl %eax, %cr3
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1997-07-06 23:32:38 +00:00
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1997-05-26 17:58:27 +00:00
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ss /* stack segment, avoid %ds load */
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2001-02-25 06:29:04 +00:00
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movl $0, lapic+LA_EOI /* End Of Interrupt to APIC */
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1997-07-06 23:32:38 +00:00
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popl %eax
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iret
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1997-12-08 22:59:39 +00:00
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/*
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* Executed by a CPU when it receives an Xcpucheckstate IPI from another CPU,
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*
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* - Stores current cpu state in checkstate_cpustate[cpuid]
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* 0 == user, 1 == sys, 2 == intr
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* - Stores current process in checkstate_curproc[cpuid]
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*
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* - Signals its receipt by setting bit cpuid in checkstate_probed_cpus.
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*
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1999-04-28 01:04:33 +00:00
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* stack: 0->ds, 4->fs, 8->ebx, 12->eax, 16->eip, 20->cs, 24->eflags
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1997-12-08 22:59:39 +00:00
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*/
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.text
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SUPERALIGN_TEXT
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2001-02-25 06:29:04 +00:00
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.globl Xcpucheckstate
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.globl checkstate_cpustate
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.globl checkstate_curproc
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.globl checkstate_pc
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Xcpucheckstate:
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1997-12-08 22:59:39 +00:00
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pushl %eax
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pushl %ebx
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pushl %ds /* save current data segment */
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1999-04-28 01:04:33 +00:00
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pushl %fs
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1997-12-08 22:59:39 +00:00
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movl $KDSEL, %eax
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2000-05-10 01:24:23 +00:00
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mov %ax, %ds /* use KERNEL data segment */
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1999-04-28 01:04:33 +00:00
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movl $KPSEL, %eax
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2000-05-10 01:24:23 +00:00
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mov %ax, %fs
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1997-12-08 22:59:39 +00:00
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2001-02-25 06:29:04 +00:00
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movl $0, lapic+LA_EOI /* End Of Interrupt to APIC */
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1997-12-08 22:59:39 +00:00
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movl $0, %ebx
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1999-04-28 01:04:33 +00:00
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movl 20(%esp), %eax
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1997-12-08 22:59:39 +00:00
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andl $3, %eax
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cmpl $3, %eax
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je 1f
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1999-04-28 01:04:33 +00:00
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testl $PSL_VM, 24(%esp)
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1997-12-08 22:59:39 +00:00
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jne 1f
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incl %ebx /* system or interrupt */
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1:
|
2000-12-13 09:23:53 +00:00
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movl PCPU(CPUID), %eax
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2001-02-25 06:29:04 +00:00
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movl %ebx, checkstate_cpustate(,%eax,4)
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2000-12-13 09:23:53 +00:00
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movl PCPU(CURPROC), %ebx
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2001-02-25 06:29:04 +00:00
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movl %ebx, checkstate_curproc(,%eax,4)
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2000-12-13 09:23:53 +00:00
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1999-04-28 01:04:33 +00:00
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movl 16(%esp), %ebx
|
2001-02-25 06:29:04 +00:00
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movl %ebx, checkstate_pc(,%eax,4)
|
1997-12-08 22:59:39 +00:00
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lock /* checkstate_probed_cpus |= (1<<id) */
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2001-02-25 06:29:04 +00:00
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btsl %eax, checkstate_probed_cpus
|
1997-12-08 22:59:39 +00:00
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1999-04-28 01:04:33 +00:00
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popl %fs
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1997-12-08 22:59:39 +00:00
|
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|
popl %ds /* restore previous data segment */
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popl %ebx
|
|
|
|
popl %eax
|
|
|
|
iret
|
|
|
|
|
1998-03-03 20:55:26 +00:00
|
|
|
|
1997-12-08 22:59:39 +00:00
|
|
|
/*
|
|
|
|
* Executed by a CPU when it receives an Xcpuast IPI from another CPU,
|
|
|
|
*
|
|
|
|
* - Signals its receipt by clearing bit cpuid in checkstate_need_ast.
|
|
|
|
*
|
|
|
|
* - We need a better method of triggering asts on other cpus.
|
|
|
|
*/
|
|
|
|
|
|
|
|
.text
|
|
|
|
SUPERALIGN_TEXT
|
2001-02-25 06:29:04 +00:00
|
|
|
.globl Xcpuast
|
|
|
|
Xcpuast:
|
1997-12-08 22:59:39 +00:00
|
|
|
PUSH_FRAME
|
|
|
|
movl $KDSEL, %eax
|
2000-05-10 01:24:23 +00:00
|
|
|
mov %ax, %ds /* use KERNEL data segment */
|
|
|
|
mov %ax, %es
|
1999-04-28 01:04:33 +00:00
|
|
|
movl $KPSEL, %eax
|
2000-05-10 01:24:23 +00:00
|
|
|
mov %ax, %fs
|
1997-12-08 22:59:39 +00:00
|
|
|
|
2000-12-13 09:23:53 +00:00
|
|
|
movl PCPU(CPUID), %eax
|
1997-12-08 22:59:39 +00:00
|
|
|
lock /* checkstate_need_ast &= ~(1<<id) */
|
2001-02-25 06:29:04 +00:00
|
|
|
btrl %eax, checkstate_need_ast
|
|
|
|
movl $0, lapic+LA_EOI /* End Of Interrupt to APIC */
|
1997-12-08 22:59:39 +00:00
|
|
|
|
|
|
|
lock
|
2001-02-25 06:29:04 +00:00
|
|
|
btsl %eax, checkstate_pending_ast
|
1997-12-08 22:59:39 +00:00
|
|
|
jc 1f
|
|
|
|
|
1999-04-28 01:04:33 +00:00
|
|
|
FAKE_MCOUNT(13*4(%esp))
|
1997-12-08 22:59:39 +00:00
|
|
|
|
2001-02-10 02:20:34 +00:00
|
|
|
MTX_LOCK_SPIN(sched_lock, 0)
|
2001-01-21 19:25:07 +00:00
|
|
|
movl PCPU(CURPROC),%ebx
|
2001-02-10 02:20:34 +00:00
|
|
|
orl $PS_ASTPENDING, P_SFLAG(%ebx)
|
1997-12-08 22:59:39 +00:00
|
|
|
|
2000-12-13 09:23:53 +00:00
|
|
|
movl PCPU(CPUID), %eax
|
1997-12-08 22:59:39 +00:00
|
|
|
lock
|
2001-02-25 06:29:04 +00:00
|
|
|
btrl %eax, checkstate_pending_ast
|
1998-05-17 22:12:14 +00:00
|
|
|
lock
|
|
|
|
btrl %eax, CNAME(resched_cpus)
|
1999-04-10 19:19:02 +00:00
|
|
|
jnc 2f
|
2001-02-10 02:20:34 +00:00
|
|
|
orl $PS_NEEDRESCHED, P_SFLAG(%ebx)
|
1998-05-17 22:12:14 +00:00
|
|
|
lock
|
|
|
|
incl CNAME(want_resched_cnt)
|
|
|
|
2:
|
2001-02-10 02:20:34 +00:00
|
|
|
MTX_UNLOCK_SPIN(sched_lock)
|
1998-05-17 22:12:14 +00:00
|
|
|
lock
|
|
|
|
incl CNAME(cpuast_cnt)
|
1997-12-08 22:59:39 +00:00
|
|
|
MEXITCOUNT
|
2001-02-25 06:29:04 +00:00
|
|
|
jmp doreti
|
1997-12-08 22:59:39 +00:00
|
|
|
1:
|
|
|
|
/* We are already in the process of delivering an ast for this CPU */
|
|
|
|
POP_FRAME
|
|
|
|
iret
|
|
|
|
|
1997-06-27 23:48:05 +00:00
|
|
|
/*
|
|
|
|
* Executed by a CPU when it receives an Xcpustop IPI from another CPU,
|
|
|
|
*
|
|
|
|
* - Signals its receipt.
|
|
|
|
* - Waits for permission to restart.
|
|
|
|
* - Signals its restart.
|
|
|
|
*/
|
|
|
|
|
|
|
|
.text
|
|
|
|
SUPERALIGN_TEXT
|
2001-02-25 06:29:04 +00:00
|
|
|
.globl Xcpustop
|
|
|
|
Xcpustop:
|
1998-05-17 22:12:14 +00:00
|
|
|
pushl %ebp
|
|
|
|
movl %esp, %ebp
|
1997-06-27 23:48:05 +00:00
|
|
|
pushl %eax
|
1998-05-17 22:12:14 +00:00
|
|
|
pushl %ecx
|
|
|
|
pushl %edx
|
1997-06-27 23:48:05 +00:00
|
|
|
pushl %ds /* save current data segment */
|
1999-04-28 01:04:33 +00:00
|
|
|
pushl %fs
|
1997-06-27 23:48:05 +00:00
|
|
|
|
|
|
|
movl $KDSEL, %eax
|
2000-05-10 01:24:23 +00:00
|
|
|
mov %ax, %ds /* use KERNEL data segment */
|
1999-04-28 01:04:33 +00:00
|
|
|
movl $KPSEL, %eax
|
2000-05-10 01:24:23 +00:00
|
|
|
mov %ax, %fs
|
1997-06-27 23:48:05 +00:00
|
|
|
|
2001-02-25 06:29:04 +00:00
|
|
|
movl $0, lapic+LA_EOI /* End Of Interrupt to APIC */
|
1998-05-17 22:12:14 +00:00
|
|
|
|
2000-12-13 09:23:53 +00:00
|
|
|
movl PCPU(CPUID), %eax
|
1998-05-17 22:12:14 +00:00
|
|
|
imull $PCB_SIZE, %eax
|
|
|
|
leal CNAME(stoppcbs)(%eax), %eax
|
|
|
|
pushl %eax
|
|
|
|
call CNAME(savectx) /* Save process context */
|
|
|
|
addl $4, %esp
|
|
|
|
|
|
|
|
|
2000-12-13 09:23:53 +00:00
|
|
|
movl PCPU(CPUID), %eax
|
1997-07-13 01:18:51 +00:00
|
|
|
|
1997-06-27 23:48:05 +00:00
|
|
|
lock
|
2001-02-25 06:29:04 +00:00
|
|
|
btsl %eax, stopped_cpus /* stopped_cpus |= (1<<id) */
|
1997-06-27 23:48:05 +00:00
|
|
|
1:
|
2001-02-25 06:29:04 +00:00
|
|
|
btl %eax, started_cpus /* while (!(started_cpus & (1<<id))) */
|
1997-06-27 23:48:05 +00:00
|
|
|
jnc 1b
|
|
|
|
|
|
|
|
lock
|
2001-02-25 06:29:04 +00:00
|
|
|
btrl %eax, started_cpus /* started_cpus &= ~(1<<id) */
|
1998-05-17 22:12:14 +00:00
|
|
|
lock
|
2001-02-25 06:29:04 +00:00
|
|
|
btrl %eax, stopped_cpus /* stopped_cpus &= ~(1<<id) */
|
1997-06-27 23:48:05 +00:00
|
|
|
|
1998-05-17 22:12:14 +00:00
|
|
|
test %eax, %eax
|
|
|
|
jnz 2f
|
1997-06-27 23:48:05 +00:00
|
|
|
|
1998-05-17 22:12:14 +00:00
|
|
|
movl CNAME(cpustop_restartfunc), %eax
|
|
|
|
test %eax, %eax
|
|
|
|
jz 2f
|
|
|
|
movl $0, CNAME(cpustop_restartfunc) /* One-shot */
|
|
|
|
|
2000-05-10 01:24:23 +00:00
|
|
|
call *%eax
|
1998-05-17 22:12:14 +00:00
|
|
|
2:
|
1999-04-28 01:04:33 +00:00
|
|
|
popl %fs
|
1997-06-27 23:48:05 +00:00
|
|
|
popl %ds /* restore previous data segment */
|
1998-05-17 22:12:14 +00:00
|
|
|
popl %edx
|
|
|
|
popl %ecx
|
1997-06-27 23:48:05 +00:00
|
|
|
popl %eax
|
1998-05-17 22:12:14 +00:00
|
|
|
movl %ebp, %esp
|
|
|
|
popl %ebp
|
1997-06-27 23:48:05 +00:00
|
|
|
iret
|
1997-07-06 23:32:38 +00:00
|
|
|
|
1997-06-27 23:48:05 +00:00
|
|
|
|
1997-05-26 17:58:27 +00:00
|
|
|
MCOUNT_LABEL(bintr)
|
|
|
|
FAST_INTR(0,fastintr0)
|
|
|
|
FAST_INTR(1,fastintr1)
|
|
|
|
FAST_INTR(2,fastintr2)
|
|
|
|
FAST_INTR(3,fastintr3)
|
|
|
|
FAST_INTR(4,fastintr4)
|
|
|
|
FAST_INTR(5,fastintr5)
|
|
|
|
FAST_INTR(6,fastintr6)
|
|
|
|
FAST_INTR(7,fastintr7)
|
|
|
|
FAST_INTR(8,fastintr8)
|
|
|
|
FAST_INTR(9,fastintr9)
|
|
|
|
FAST_INTR(10,fastintr10)
|
|
|
|
FAST_INTR(11,fastintr11)
|
|
|
|
FAST_INTR(12,fastintr12)
|
|
|
|
FAST_INTR(13,fastintr13)
|
|
|
|
FAST_INTR(14,fastintr14)
|
|
|
|
FAST_INTR(15,fastintr15)
|
|
|
|
FAST_INTR(16,fastintr16)
|
|
|
|
FAST_INTR(17,fastintr17)
|
|
|
|
FAST_INTR(18,fastintr18)
|
|
|
|
FAST_INTR(19,fastintr19)
|
|
|
|
FAST_INTR(20,fastintr20)
|
|
|
|
FAST_INTR(21,fastintr21)
|
|
|
|
FAST_INTR(22,fastintr22)
|
|
|
|
FAST_INTR(23,fastintr23)
|
2000-12-04 21:15:14 +00:00
|
|
|
FAST_INTR(24,fastintr24)
|
|
|
|
FAST_INTR(25,fastintr25)
|
|
|
|
FAST_INTR(26,fastintr26)
|
|
|
|
FAST_INTR(27,fastintr27)
|
|
|
|
FAST_INTR(28,fastintr28)
|
|
|
|
FAST_INTR(29,fastintr29)
|
|
|
|
FAST_INTR(30,fastintr30)
|
|
|
|
FAST_INTR(31,fastintr31)
|
1999-05-28 14:08:59 +00:00
|
|
|
#define CLKINTR_PENDING movl $1,CNAME(clkintr_pending)
|
2000-09-07 01:33:02 +00:00
|
|
|
/* Threaded interrupts */
|
1999-05-28 14:08:59 +00:00
|
|
|
INTR(0,intr0, CLKINTR_PENDING)
|
|
|
|
INTR(1,intr1,)
|
|
|
|
INTR(2,intr2,)
|
|
|
|
INTR(3,intr3,)
|
|
|
|
INTR(4,intr4,)
|
|
|
|
INTR(5,intr5,)
|
|
|
|
INTR(6,intr6,)
|
|
|
|
INTR(7,intr7,)
|
|
|
|
INTR(8,intr8,)
|
|
|
|
INTR(9,intr9,)
|
|
|
|
INTR(10,intr10,)
|
|
|
|
INTR(11,intr11,)
|
|
|
|
INTR(12,intr12,)
|
|
|
|
INTR(13,intr13,)
|
|
|
|
INTR(14,intr14,)
|
|
|
|
INTR(15,intr15,)
|
|
|
|
INTR(16,intr16,)
|
|
|
|
INTR(17,intr17,)
|
|
|
|
INTR(18,intr18,)
|
|
|
|
INTR(19,intr19,)
|
|
|
|
INTR(20,intr20,)
|
|
|
|
INTR(21,intr21,)
|
|
|
|
INTR(22,intr22,)
|
|
|
|
INTR(23,intr23,)
|
2000-12-04 21:15:14 +00:00
|
|
|
INTR(24,intr24,)
|
|
|
|
INTR(25,intr25,)
|
|
|
|
INTR(26,intr26,)
|
|
|
|
INTR(27,intr27,)
|
|
|
|
INTR(28,intr28,)
|
|
|
|
INTR(29,intr29,)
|
|
|
|
INTR(30,intr30,)
|
|
|
|
INTR(31,intr31,)
|
1997-05-26 17:58:27 +00:00
|
|
|
MCOUNT_LABEL(eintr)
|
|
|
|
|
1999-07-20 06:52:35 +00:00
|
|
|
/*
|
|
|
|
* Executed by a CPU when it receives a RENDEZVOUS IPI from another CPU.
|
|
|
|
*
|
|
|
|
* - Calls the generic rendezvous action function.
|
|
|
|
*/
|
|
|
|
.text
|
|
|
|
SUPERALIGN_TEXT
|
2001-02-25 06:29:04 +00:00
|
|
|
.globl Xrendezvous
|
|
|
|
Xrendezvous:
|
1999-07-20 06:52:35 +00:00
|
|
|
PUSH_FRAME
|
|
|
|
movl $KDSEL, %eax
|
2000-05-10 01:24:23 +00:00
|
|
|
mov %ax, %ds /* use KERNEL data segment */
|
|
|
|
mov %ax, %es
|
1999-07-20 06:52:35 +00:00
|
|
|
movl $KPSEL, %eax
|
2000-05-10 01:24:23 +00:00
|
|
|
mov %ax, %fs
|
1999-07-20 06:52:35 +00:00
|
|
|
|
2001-02-25 06:29:04 +00:00
|
|
|
call smp_rendezvous_action
|
1999-07-20 06:52:35 +00:00
|
|
|
|
2001-02-25 06:29:04 +00:00
|
|
|
movl $0, lapic+LA_EOI /* End Of Interrupt to APIC */
|
1999-07-20 06:52:35 +00:00
|
|
|
POP_FRAME
|
|
|
|
iret
|
|
|
|
|
|
|
|
|
1997-05-26 17:58:27 +00:00
|
|
|
.data
|
|
|
|
|
1997-07-06 23:32:38 +00:00
|
|
|
#ifdef COUNT_XINVLTLB_HITS
|
|
|
|
.globl _xhits
|
|
|
|
_xhits:
|
1997-07-18 21:27:53 +00:00
|
|
|
.space (NCPU * 4), 0
|
1997-07-06 23:32:38 +00:00
|
|
|
#endif /* COUNT_XINVLTLB_HITS */
|
|
|
|
|
1997-07-18 21:27:53 +00:00
|
|
|
/* variables used by stop_cpus()/restart_cpus()/Xcpustop */
|
2001-02-25 06:29:04 +00:00
|
|
|
.globl stopped_cpus, started_cpus
|
|
|
|
stopped_cpus:
|
1997-06-27 23:48:05 +00:00
|
|
|
.long 0
|
2001-02-25 06:29:04 +00:00
|
|
|
started_cpus:
|
1997-06-27 23:48:05 +00:00
|
|
|
.long 0
|
1997-07-06 23:32:38 +00:00
|
|
|
|
2001-02-25 06:29:04 +00:00
|
|
|
.globl checkstate_probed_cpus
|
|
|
|
checkstate_probed_cpus:
|
1997-12-08 22:59:39 +00:00
|
|
|
.long 0
|
2001-02-25 06:29:04 +00:00
|
|
|
.globl checkstate_need_ast
|
|
|
|
checkstate_need_ast:
|
1997-12-08 22:59:39 +00:00
|
|
|
.long 0
|
2001-02-25 06:29:04 +00:00
|
|
|
checkstate_pending_ast:
|
1997-12-08 22:59:39 +00:00
|
|
|
.long 0
|
1998-05-17 22:12:14 +00:00
|
|
|
.globl CNAME(resched_cpus)
|
|
|
|
.globl CNAME(want_resched_cnt)
|
|
|
|
.globl CNAME(cpuast_cnt)
|
|
|
|
.globl CNAME(cpustop_restartfunc)
|
|
|
|
CNAME(resched_cpus):
|
|
|
|
.long 0
|
|
|
|
CNAME(want_resched_cnt):
|
|
|
|
.long 0
|
|
|
|
CNAME(cpuast_cnt):
|
|
|
|
.long 0
|
|
|
|
CNAME(cpustop_restartfunc):
|
|
|
|
.long 0
|
1997-12-08 22:59:39 +00:00
|
|
|
|
2001-02-25 06:29:04 +00:00
|
|
|
.globl apic_pin_trigger
|
|
|
|
apic_pin_trigger:
|
1998-09-06 22:41:42 +00:00
|
|
|
.long 0
|
1997-07-28 03:59:54 +00:00
|
|
|
|
1997-05-26 17:58:27 +00:00
|
|
|
.text
|