180 lines
5.1 KiB
C
180 lines
5.1 KiB
C
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/*-
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* Copyright (c) 2012 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define PCI_VENDOR_XILINX 0x10ee
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#define PCI_DEVICE_XILINX_HDSPE 0x3fc6 /* AIO, MADI, AES, RayDAT */
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#define PCI_CLASS_REVISION 0x08
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#define PCI_REVISION_AIO 212
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#define PCI_REVISION_RAYDAT 211
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#define AIO 0
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#define RAYDAT 1
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/* Hardware mixer */
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#define HDSPE_OUT_ENABLE_BASE 512
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#define HDSPE_IN_ENABLE_BASE 768
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#define HDSPE_MIXER_BASE 32768
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#define HDSPE_MAX_GAIN 32768
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/* Buffer */
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#define HDSPE_PAGE_ADDR_BUF_OUT 8192
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#define HDSPE_PAGE_ADDR_BUF_IN (HDSPE_PAGE_ADDR_BUF_OUT + 64 * 16 * 4)
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#define HDSPE_BUF_POSITION_MASK 0x000FFC0
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/* Frequency */
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#define HDSPE_FREQ_0 (1<<6)
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#define HDSPE_FREQ_1 (1<<7)
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#define HDSPE_FREQ_DOUBLE (1<<8)
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#define HDSPE_FREQ_QUAD (1<<31)
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#define HDSPE_FREQ_32000 HDSPE_FREQ_0
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#define HDSPE_FREQ_44100 HDSPE_FREQ_1
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#define HDSPE_FREQ_48000 (HDSPE_FREQ_0 | HDSPE_FREQ_1)
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#define HDSPE_FREQ_MASK (HDSPE_FREQ_0 | HDSPE_FREQ_1 | \
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HDSPE_FREQ_DOUBLE | HDSPE_FREQ_QUAD)
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#define HDSPE_FREQ_MASK_DEFAULT HDSPE_FREQ_48000
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#define HDSPE_FREQ_REG 256
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#define HDSPE_FREQ_AIO 104857600000000ULL
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#define HDSPE_SPEED_DEFAULT 48000
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/* Latency */
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#define HDSPE_LAT_0 (1<<1)
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#define HDSPE_LAT_1 (1<<2)
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#define HDSPE_LAT_2 (1<<3)
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#define HDSPE_LAT_MASK (HDSPE_LAT_0 | HDSPE_LAT_1 | HDSPE_LAT_2)
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#define HDSPE_LAT_BYTES_MAX (4096 * 4)
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#define HDSPE_LAT_BYTES_MIN (32 * 4)
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#define hdspe_encode_latency(x) (((x)<<1) & HDSPE_LAT_MASK)
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/* Settings */
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#define HDSPE_SETTINGS_REG 0
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#define HDSPE_CONTROL_REG 64
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#define HDSPE_STATUS_REG 0
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#define HDSPE_ENABLE (1<<0)
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#define HDSPM_CLOCK_MODE_MASTER (1<<4)
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/* Interrupts */
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#define HDSPE_AUDIO_IRQ_PENDING (1<<0)
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#define HDSPE_AUDIO_INT_ENABLE (1<<5)
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#define HDSPE_INTERRUPT_ACK 96
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/* Channels */
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#define HDSPE_MAX_SLOTS 64 /* Mono channels */
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#define HDSPE_MAX_CHANS (HDSPE_MAX_SLOTS / 2) /* Stereo pairs */
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#define HDSPE_CHANBUF_SAMPLES (16 * 1024)
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#define HDSPE_CHANBUF_SIZE (4 * HDSPE_CHANBUF_SAMPLES)
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#define HDSPE_DMASEGSIZE (HDSPE_CHANBUF_SIZE * HDSPE_MAX_SLOTS)
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struct hdspe_channel {
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uint32_t left;
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uint32_t right;
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char *descr;
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uint32_t play;
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uint32_t rec;
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};
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static MALLOC_DEFINE(M_HDSPE, "hdspe", "hdspe audio");
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/* Channel registers */
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struct sc_chinfo {
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struct snd_dbuf *buffer;
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struct pcm_channel *channel;
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struct sc_pcminfo *parent;
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/* Channel information */
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uint32_t dir;
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uint32_t format;
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uint32_t lslot;
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uint32_t rslot;
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uint32_t lvol;
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uint32_t rvol;
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/* Buffer */
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uint32_t *data;
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uint32_t size;
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/* Flags */
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uint32_t run;
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};
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/* PCM device private data */
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struct sc_pcminfo {
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device_t dev;
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uint32_t (*ih) (struct sc_pcminfo *scp);
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uint32_t chnum;
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struct sc_chinfo chan[HDSPE_MAX_CHANS];
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struct sc_info *sc;
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struct hdspe_channel *hc;
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};
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/* HDSPe device private data */
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struct sc_info {
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device_t dev;
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struct mtx *lock;
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uint32_t ctrl_register;
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uint32_t settings_register;
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uint32_t type;
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/* Control/Status register */
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struct resource *cs;
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int csid;
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bus_space_tag_t cst;
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bus_space_handle_t csh;
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struct resource *irq;
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int irqid;
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void *ih;
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bus_dma_tag_t dmat;
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/* Play/Record DMA buffers */
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uint32_t *pbuf;
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uint32_t *rbuf;
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uint32_t bufsize;
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bus_dmamap_t pmap;
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bus_dmamap_t rmap;
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uint32_t period;
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uint32_t speed;
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};
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#define hdspe_read_1(sc, regno) \
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bus_space_read_1((sc)->cst, (sc)->csh, (regno))
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#define hdspe_read_2(sc, regno) \
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bus_space_read_2((sc)->cst, (sc)->csh, (regno))
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#define hdspe_read_4(sc, regno) \
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bus_space_read_4((sc)->cst, (sc)->csh, (regno))
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#define hdspe_write_1(sc, regno, data) \
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bus_space_write_1((sc)->cst, (sc)->csh, (regno), (data))
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#define hdspe_write_2(sc, regno, data) \
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bus_space_write_2((sc)->cst, (sc)->csh, (regno), (data))
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#define hdspe_write_4(sc, regno, data) \
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bus_space_write_4((sc)->cst, (sc)->csh, (regno), (data))
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