545 lines
12 KiB
C
545 lines
12 KiB
C
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/*-
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* Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by the University of Cambridge Computer
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* Laboratory with support from ARM Ltd.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/pmc.h>
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#include <sys/pmckern.h>
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#include <machine/pmc_mdep.h>
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#include <machine/cpu.h>
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static int arm64_npmcs;
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struct arm64_event_code_map {
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enum pmc_event pe_ev;
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uint8_t pe_code;
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};
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/*
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* Per-processor information.
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*/
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struct arm64_cpu {
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struct pmc_hw *pc_arm64pmcs;
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};
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static struct arm64_cpu **arm64_pcpu;
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/*
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* Interrupt Enable Set Register
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*/
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static __inline void
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arm64_interrupt_enable(uint32_t pmc)
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{
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uint32_t reg;
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reg = (1 << pmc);
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WRITE_SPECIALREG(PMINTENSET_EL1, reg);
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isb();
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}
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/*
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* Interrupt Clear Set Register
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*/
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static __inline void
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arm64_interrupt_disable(uint32_t pmc)
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{
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uint32_t reg;
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reg = (1 << pmc);
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WRITE_SPECIALREG(PMINTENCLR_EL1, reg);
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isb();
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}
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/*
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* Counter Set Enable Register
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*/
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static __inline void
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arm64_counter_enable(unsigned int pmc)
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{
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uint32_t reg;
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reg = (1 << pmc);
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WRITE_SPECIALREG(PMCNTENSET_EL0, reg);
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isb();
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}
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/*
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* Counter Clear Enable Register
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*/
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static __inline void
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arm64_counter_disable(unsigned int pmc)
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{
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uint32_t reg;
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reg = (1 << pmc);
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WRITE_SPECIALREG(PMCNTENCLR_EL0, reg);
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isb();
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}
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/*
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* Performance Monitors Control Register
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*/
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static uint32_t
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arm64_pmcr_read(void)
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{
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uint32_t reg;
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reg = READ_SPECIALREG(PMCR_EL0);
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return (reg);
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}
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static void
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arm64_pmcr_write(uint32_t reg)
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{
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WRITE_SPECIALREG(PMCR_EL0, reg);
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isb();
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}
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/*
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* Performance Count Register N
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*/
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static uint32_t
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arm64_pmcn_read(unsigned int pmc)
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{
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KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc));
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WRITE_SPECIALREG(PMSELR_EL0, pmc);
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isb();
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return (READ_SPECIALREG(PMXEVCNTR_EL0));
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}
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static void
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arm64_pmcn_write(unsigned int pmc, uint32_t reg)
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{
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KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc));
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WRITE_SPECIALREG(PMSELR_EL0, pmc);
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WRITE_SPECIALREG(PMXEVCNTR_EL0, reg);
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isb();
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}
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static int
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arm64_allocate_pmc(int cpu, int ri, struct pmc *pm,
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const struct pmc_op_pmcallocate *a)
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{
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uint32_t caps, config;
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struct arm64_cpu *pac;
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enum pmc_event pe;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[arm64,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < arm64_npmcs,
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("[arm64,%d] illegal row index %d", __LINE__, ri));
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pac = arm64_pcpu[cpu];
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caps = a->pm_caps;
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if (a->pm_class != PMC_CLASS_ARMV8) {
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return (EINVAL);
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}
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pe = a->pm_ev;
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config = (pe & EVENT_ID_MASK);
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pm->pm_md.pm_arm64.pm_arm64_evsel = config;
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PMCDBG2(MDP, ALL, 2, "arm64-allocate ri=%d -> config=0x%x", ri, config);
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return 0;
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}
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static int
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arm64_read_pmc(int cpu, int ri, pmc_value_t *v)
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{
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pmc_value_t tmp;
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struct pmc *pm;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[arm64,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < arm64_npmcs,
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("[arm64,%d] illegal row index %d", __LINE__, ri));
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pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc;
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tmp = arm64_pmcn_read(ri);
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PMCDBG2(MDP, REA, 2, "arm64-read id=%d -> %jd", ri, tmp);
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if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
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*v = ARMV8_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
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else
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*v = tmp;
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return 0;
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}
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static int
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arm64_write_pmc(int cpu, int ri, pmc_value_t v)
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{
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struct pmc *pm;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[arm64,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < arm64_npmcs,
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("[arm64,%d] illegal row-index %d", __LINE__, ri));
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pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc;
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if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
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v = ARMV8_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
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PMCDBG3(MDP, WRI, 1, "arm64-write cpu=%d ri=%d v=%jx", cpu, ri, v);
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arm64_pmcn_write(ri, v);
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return 0;
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}
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static int
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arm64_config_pmc(int cpu, int ri, struct pmc *pm)
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{
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struct pmc_hw *phw;
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PMCDBG3(MDP, CFG, 1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[arm64,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < arm64_npmcs,
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("[arm64,%d] illegal row-index %d", __LINE__, ri));
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phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri];
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KASSERT(pm == NULL || phw->phw_pmc == NULL,
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("[arm64,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
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__LINE__, pm, phw->phw_pmc));
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phw->phw_pmc = pm;
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return 0;
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}
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static int
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arm64_start_pmc(int cpu, int ri)
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{
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struct pmc_hw *phw;
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uint32_t config;
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struct pmc *pm;
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phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri];
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pm = phw->phw_pmc;
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config = pm->pm_md.pm_arm64.pm_arm64_evsel;
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/*
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* Configure the event selection.
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*/
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WRITE_SPECIALREG(PMSELR_EL0, ri);
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WRITE_SPECIALREG(PMXEVTYPER_EL0, config);
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isb();
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/*
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* Enable the PMC.
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*/
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arm64_interrupt_enable(ri);
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arm64_counter_enable(ri);
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return 0;
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}
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static int
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arm64_stop_pmc(int cpu, int ri)
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{
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struct pmc_hw *phw;
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struct pmc *pm;
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phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri];
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pm = phw->phw_pmc;
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/*
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* Disable the PMCs.
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*/
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arm64_counter_disable(ri);
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arm64_interrupt_disable(ri);
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return 0;
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}
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static int
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arm64_release_pmc(int cpu, int ri, struct pmc *pmc)
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{
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struct pmc_hw *phw;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[arm64,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < arm64_npmcs,
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("[arm64,%d] illegal row-index %d", __LINE__, ri));
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phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri];
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KASSERT(phw->phw_pmc == NULL,
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("[arm64,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
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return 0;
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}
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static int
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arm64_intr(int cpu, struct trapframe *tf)
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{
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struct arm64_cpu *pc;
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int retval, ri;
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struct pmc *pm;
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int error;
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int reg;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[arm64,%d] CPU %d out of range", __LINE__, cpu));
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retval = 0;
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pc = arm64_pcpu[cpu];
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for (ri = 0; ri < arm64_npmcs; ri++) {
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pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc;
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if (pm == NULL)
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continue;
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if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
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continue;
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/* Check if counter is overflowed */
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reg = (1 << ri);
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if ((READ_SPECIALREG(PMOVSCLR_EL0) & reg) == 0)
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continue;
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/* Clear Overflow Flag */
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WRITE_SPECIALREG(PMOVSCLR_EL0, reg);
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isb();
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retval = 1; /* Found an interrupting PMC. */
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if (pm->pm_state != PMC_STATE_RUNNING)
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continue;
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error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
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TRAPF_USERMODE(tf));
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if (error)
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arm64_stop_pmc(cpu, ri);
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/* Reload sampling count */
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arm64_write_pmc(cpu, ri, pm->pm_sc.pm_reloadcount);
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}
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return (retval);
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}
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static int
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arm64_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
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{
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char arm64_name[PMC_NAME_MAX];
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struct pmc_hw *phw;
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int error;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[arm64,%d], illegal CPU %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < arm64_npmcs,
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("[arm64,%d] row-index %d out of range", __LINE__, ri));
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phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri];
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snprintf(arm64_name, sizeof(arm64_name), "ARMV8-%d", ri);
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if ((error = copystr(arm64_name, pi->pm_name, PMC_NAME_MAX,
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NULL)) != 0)
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return (error);
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pi->pm_class = PMC_CLASS_ARMV8;
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if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
|
||
|
|
pi->pm_enabled = TRUE;
|
||
|
|
*ppmc = phw->phw_pmc;
|
||
|
|
} else {
|
||
|
|
pi->pm_enabled = FALSE;
|
||
|
|
*ppmc = NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
return (0);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int
|
||
|
|
arm64_get_config(int cpu, int ri, struct pmc **ppm)
|
||
|
|
{
|
||
|
|
|
||
|
|
*ppm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc;
|
||
|
|
|
||
|
|
return (0);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* XXX don't know what we should do here.
|
||
|
|
*/
|
||
|
|
static int
|
||
|
|
arm64_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
|
||
|
|
{
|
||
|
|
|
||
|
|
return (0);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int
|
||
|
|
arm64_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
|
||
|
|
{
|
||
|
|
|
||
|
|
return (0);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int
|
||
|
|
arm64_pcpu_init(struct pmc_mdep *md, int cpu)
|
||
|
|
{
|
||
|
|
struct arm64_cpu *pac;
|
||
|
|
struct pmc_hw *phw;
|
||
|
|
struct pmc_cpu *pc;
|
||
|
|
uint64_t pmcr;
|
||
|
|
int first_ri;
|
||
|
|
int i;
|
||
|
|
|
||
|
|
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
|
||
|
|
("[arm64,%d] wrong cpu number %d", __LINE__, cpu));
|
||
|
|
PMCDBG1(MDP, INI, 1, "arm64-init cpu=%d", cpu);
|
||
|
|
|
||
|
|
arm64_pcpu[cpu] = pac = malloc(sizeof(struct arm64_cpu), M_PMC,
|
||
|
|
M_WAITOK | M_ZERO);
|
||
|
|
|
||
|
|
pac->pc_arm64pmcs = malloc(sizeof(struct pmc_hw) * arm64_npmcs,
|
||
|
|
M_PMC, M_WAITOK | M_ZERO);
|
||
|
|
pc = pmc_pcpu[cpu];
|
||
|
|
first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8].pcd_ri;
|
||
|
|
KASSERT(pc != NULL, ("[arm64,%d] NULL per-cpu pointer", __LINE__));
|
||
|
|
|
||
|
|
for (i = 0, phw = pac->pc_arm64pmcs; i < arm64_npmcs; i++, phw++) {
|
||
|
|
phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
|
||
|
|
PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i);
|
||
|
|
phw->phw_pmc = NULL;
|
||
|
|
pc->pc_hwpmcs[i + first_ri] = phw;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Enable unit */
|
||
|
|
pmcr = arm64_pmcr_read();
|
||
|
|
pmcr |= PMCR_E;
|
||
|
|
arm64_pmcr_write(pmcr);
|
||
|
|
|
||
|
|
return (0);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int
|
||
|
|
arm64_pcpu_fini(struct pmc_mdep *md, int cpu)
|
||
|
|
{
|
||
|
|
uint32_t pmcr;
|
||
|
|
|
||
|
|
pmcr = arm64_pmcr_read();
|
||
|
|
pmcr &= ~PMCR_E;
|
||
|
|
arm64_pmcr_write(pmcr);
|
||
|
|
|
||
|
|
return (0);
|
||
|
|
}
|
||
|
|
|
||
|
|
struct pmc_mdep *
|
||
|
|
pmc_arm64_initialize()
|
||
|
|
{
|
||
|
|
struct pmc_mdep *pmc_mdep;
|
||
|
|
struct pmc_classdep *pcd;
|
||
|
|
int idcode;
|
||
|
|
int reg;
|
||
|
|
|
||
|
|
reg = arm64_pmcr_read();
|
||
|
|
arm64_npmcs = (reg & PMCR_N_MASK) >> PMCR_N_SHIFT;
|
||
|
|
idcode = (reg & PMCR_IDCODE_MASK) >> PMCR_IDCODE_SHIFT;
|
||
|
|
|
||
|
|
PMCDBG1(MDP, INI, 1, "arm64-init npmcs=%d", arm64_npmcs);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Allocate space for pointers to PMC HW descriptors and for
|
||
|
|
* the MDEP structure used by MI code.
|
||
|
|
*/
|
||
|
|
arm64_pcpu = malloc(sizeof(struct arm64_cpu *) * pmc_cpu_max(),
|
||
|
|
M_PMC, M_WAITOK | M_ZERO);
|
||
|
|
|
||
|
|
/* Just one class */
|
||
|
|
pmc_mdep = pmc_mdep_alloc(1);
|
||
|
|
|
||
|
|
switch (idcode) {
|
||
|
|
case PMCR_IDCODE_CORTEX_A57:
|
||
|
|
case PMCR_IDCODE_CORTEX_A72:
|
||
|
|
pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A57;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
case PMCR_IDCODE_CORTEX_A53:
|
||
|
|
pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8];
|
||
|
|
pcd->pcd_caps = ARMV8_PMC_CAPS;
|
||
|
|
pcd->pcd_class = PMC_CLASS_ARMV8;
|
||
|
|
pcd->pcd_num = arm64_npmcs;
|
||
|
|
pcd->pcd_ri = pmc_mdep->pmd_npmc;
|
||
|
|
pcd->pcd_width = 32;
|
||
|
|
|
||
|
|
pcd->pcd_allocate_pmc = arm64_allocate_pmc;
|
||
|
|
pcd->pcd_config_pmc = arm64_config_pmc;
|
||
|
|
pcd->pcd_pcpu_fini = arm64_pcpu_fini;
|
||
|
|
pcd->pcd_pcpu_init = arm64_pcpu_init;
|
||
|
|
pcd->pcd_describe = arm64_describe;
|
||
|
|
pcd->pcd_get_config = arm64_get_config;
|
||
|
|
pcd->pcd_read_pmc = arm64_read_pmc;
|
||
|
|
pcd->pcd_release_pmc = arm64_release_pmc;
|
||
|
|
pcd->pcd_start_pmc = arm64_start_pmc;
|
||
|
|
pcd->pcd_stop_pmc = arm64_stop_pmc;
|
||
|
|
pcd->pcd_write_pmc = arm64_write_pmc;
|
||
|
|
|
||
|
|
pmc_mdep->pmd_intr = arm64_intr;
|
||
|
|
pmc_mdep->pmd_switch_in = arm64_switch_in;
|
||
|
|
pmc_mdep->pmd_switch_out = arm64_switch_out;
|
||
|
|
|
||
|
|
pmc_mdep->pmd_npmc += arm64_npmcs;
|
||
|
|
|
||
|
|
return (pmc_mdep);
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
pmc_arm64_finalize(struct pmc_mdep *md)
|
||
|
|
{
|
||
|
|
|
||
|
|
}
|