2008-11-28 00:03:41 +00:00
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/*
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* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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2010-03-03 17:32:32 +00:00
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* $FreeBSD$
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2008-11-28 00:03:41 +00:00
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_internal.h"
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#include "ar5212/ar5212.h"
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#include "ar5212/ar5212reg.h"
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#include "ar5212/ar5212desc.h"
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2011-09-08 01:23:05 +00:00
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/*
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* Return the hardware NextTBTT in TSF
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*/
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uint64_t
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ar5212GetNextTBTT(struct ath_hal *ah)
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{
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#define TU_TO_TSF(_tu) (((uint64_t)(_tu)) << 10)
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return TU_TO_TSF(OS_REG_READ(ah, AR_TIMER0));
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#undef TU_TO_TSF
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}
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2008-11-28 00:03:41 +00:00
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/*
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* Initialize all of the hardware registers used to
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* send beacons. Note that for station operation the
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* driver calls ar5212SetStaBeaconTimers instead.
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*/
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void
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ar5212SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt)
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{
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2011-09-28 03:03:23 +00:00
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struct ath_hal_5212 *ahp = AH5212(ah);
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2008-11-28 00:03:41 +00:00
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2012-11-27 02:18:41 +00:00
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/*
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* Limit the timers to their specific resolutions:
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*
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* + Timer 0 - 0..15 0xffff TU
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* + Timer 1 - 0..18 0x7ffff TU/8
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* + Timer 2 - 0..24 0x1ffffff TU/8
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* + Timer 3 - 0..15 0xffff TU
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*/
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OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt & 0xffff);
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OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba & 0x7ffff);
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OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba & 0x1ffffff);
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/* XXX force nextatim to be non-zero? */
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OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim & 0xffff);
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2008-11-28 00:03:41 +00:00
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/*
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* Set the Beacon register after setting all timers.
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*/
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if (bt->bt_intval & AR_BEACON_RESET_TSF) {
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/*
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* When resetting the TSF,
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* write twice to the corresponding register; each
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* write to the RESET_TSF bit toggles the internal
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* signal to cause a reset of the TSF - but if the signal
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* is left high, it will reset the TSF on the next
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* chip reset also! writing the bit an even number
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* of times fixes this issue
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*/
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OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_RESET_TSF);
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}
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OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);
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2011-09-28 03:03:23 +00:00
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ahp->ah_beaconInterval = (bt->bt_intval & HAL_BEACON_PERIOD);
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2008-11-28 00:03:41 +00:00
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}
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/*
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* Old api for setting up beacon timer registers when
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* operating in !station mode. Note the fixed constants
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* adjusting the DBA and SWBA timers and the fixed ATIM
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* window.
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*/
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void
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ar5212BeaconInit(struct ath_hal *ah,
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uint32_t next_beacon, uint32_t beacon_period)
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{
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HAL_BEACON_TIMERS bt;
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bt.bt_nexttbtt = next_beacon;
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/*
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* TIMER1: in AP/adhoc mode this controls the DMA beacon
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* alert timer; otherwise it controls the next wakeup time.
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* TIMER2: in AP mode, it controls the SBA beacon alert
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* interrupt; otherwise it sets the start of the next CFP.
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*/
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switch (AH_PRIVATE(ah)->ah_opmode) {
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case HAL_M_STA:
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case HAL_M_MONITOR:
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bt.bt_nextdba = 0xffff;
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bt.bt_nextswba = 0x7ffff;
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break;
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case HAL_M_HOSTAP:
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case HAL_M_IBSS:
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bt.bt_nextdba = (next_beacon -
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2011-06-23 06:53:13 +00:00
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ah->ah_config.ah_dma_beacon_response_time) << 3; /* 1/8 TU */
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2008-11-28 00:03:41 +00:00
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bt.bt_nextswba = (next_beacon -
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2011-06-23 06:53:13 +00:00
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ah->ah_config.ah_sw_beacon_response_time) << 3; /* 1/8 TU */
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2008-11-28 00:03:41 +00:00
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break;
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}
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/*
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* Set the ATIM window
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* Our hardware does not support an ATIM window of 0
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* (beacons will not work). If the ATIM windows is 0,
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* force it to 1.
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*/
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bt.bt_nextatim = next_beacon + 1;
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bt.bt_intval = beacon_period &
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(AR_BEACON_PERIOD | AR_BEACON_RESET_TSF | AR_BEACON_EN);
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ar5212SetBeaconTimers(ah, &bt);
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}
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void
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ar5212ResetStaBeaconTimers(struct ath_hal *ah)
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{
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uint32_t val;
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OS_REG_WRITE(ah, AR_TIMER0, 0); /* no beacons */
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val = OS_REG_READ(ah, AR_STA_ID1);
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val |= AR_STA_ID1_PWR_SAV; /* XXX */
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/* tell the h/w that the associated AP is not PCF capable */
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OS_REG_WRITE(ah, AR_STA_ID1,
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val & ~(AR_STA_ID1_USE_DEFANT | AR_STA_ID1_PCF));
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OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD);
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}
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/*
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* Set all the beacon related bits on the h/w for stations
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* i.e. initializes the corresponding h/w timers;
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* also tells the h/w whether to anticipate PCF beacons
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*/
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void
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ar5212SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs)
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{
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struct ath_hal_5212 *ahp = AH5212(ah);
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uint32_t nextTbtt, nextdtim,beaconintval, dtimperiod;
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HALASSERT(bs->bs_intval != 0);
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/* if the AP will do PCF */
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if (bs->bs_cfpmaxduration != 0) {
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/* tell the h/w that the associated AP is PCF capable */
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OS_REG_WRITE(ah, AR_STA_ID1,
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OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PCF);
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/* set CFP_PERIOD(1.024ms) register */
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OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod);
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/* set CFP_DUR(1.024ms) register to max cfp duration */
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OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration);
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/* set TIMER2(128us) to anticipated time of next CFP */
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OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3);
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} else {
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/* tell the h/w that the associated AP is not PCF capable */
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OS_REG_WRITE(ah, AR_STA_ID1,
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OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_PCF);
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}
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/*
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* Set TIMER0(1.024ms) to the anticipated time of the next beacon.
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*/
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OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt);
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/*
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* Start the beacon timers by setting the BEACON register
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* to the beacon interval; also write the tim offset which
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* we should know by now. The code, in ar5211WriteAssocid,
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* also sets the tim offset once the AID is known which can
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* be left as such for now.
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*/
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OS_REG_WRITE(ah, AR_BEACON,
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(OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
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| SM(bs->bs_intval, AR_BEACON_PERIOD)
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| SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM)
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);
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/*
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* Configure the BMISS interrupt. Note that we
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* assume the caller blocks interrupts while enabling
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* the threshold.
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*/
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HALASSERT(bs->bs_bmissthreshold <= MS(0xffffffff, AR_RSSI_THR_BM_THR));
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ahp->ah_rssiThr = (ahp->ah_rssiThr &~ AR_RSSI_THR_BM_THR)
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| SM(bs->bs_bmissthreshold, AR_RSSI_THR_BM_THR);
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OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
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/*
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* Program the sleep registers to correlate with the beacon setup.
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*/
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/*
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* Oahu beacons timers on the station were used for power
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* save operation (waking up in anticipation of a beacon)
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* and any CFP function; Venice does sleep/power-save timers
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* differently - so this is the right place to set them up;
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* don't think the beacon timers are used by venice sta hw
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* for any useful purpose anymore
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* Setup venice's sleep related timers
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* Current implementation assumes sw processing of beacons -
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* assuming an interrupt is generated every beacon which
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* causes the hardware to become awake until the sw tells
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* it to go to sleep again; beacon timeout is to allow for
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* beacon jitter; cab timeout is max time to wait for cab
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* after seeing the last DTIM or MORE CAB bit
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*/
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#define CAB_TIMEOUT_VAL 10 /* in TU */
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#define BEACON_TIMEOUT_VAL 10 /* in TU */
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#define SLEEP_SLOP 3 /* in TU */
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/*
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* For max powersave mode we may want to sleep for longer than a
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* beacon period and not want to receive all beacons; modify the
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* timers accordingly; make sure to align the next TIM to the
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* next DTIM if we decide to wake for DTIMs only
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*/
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beaconintval = bs->bs_intval & HAL_BEACON_PERIOD;
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HALASSERT(beaconintval != 0);
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if (bs->bs_sleepduration > beaconintval) {
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HALASSERT(roundup(bs->bs_sleepduration, beaconintval) ==
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bs->bs_sleepduration);
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beaconintval = bs->bs_sleepduration;
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}
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dtimperiod = bs->bs_dtimperiod;
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if (bs->bs_sleepduration > dtimperiod) {
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HALASSERT(dtimperiod == 0 ||
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roundup(bs->bs_sleepduration, dtimperiod) ==
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bs->bs_sleepduration);
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dtimperiod = bs->bs_sleepduration;
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}
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HALASSERT(beaconintval <= dtimperiod);
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if (beaconintval == dtimperiod)
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nextTbtt = bs->bs_nextdtim;
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else
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nextTbtt = bs->bs_nexttbtt;
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nextdtim = bs->bs_nextdtim;
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OS_REG_WRITE(ah, AR_SLEEP1,
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SM((nextdtim - SLEEP_SLOP) << 3, AR_SLEEP1_NEXT_DTIM)
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| SM(CAB_TIMEOUT_VAL, AR_SLEEP1_CAB_TIMEOUT)
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| AR_SLEEP1_ASSUME_DTIM
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| AR_SLEEP1_ENH_SLEEP_ENA
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);
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OS_REG_WRITE(ah, AR_SLEEP2,
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SM((nextTbtt - SLEEP_SLOP) << 3, AR_SLEEP2_NEXT_TIM)
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| SM(BEACON_TIMEOUT_VAL, AR_SLEEP2_BEACON_TIMEOUT)
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);
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OS_REG_WRITE(ah, AR_SLEEP3,
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SM(beaconintval, AR_SLEEP3_TIM_PERIOD)
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| SM(dtimperiod, AR_SLEEP3_DTIM_PERIOD)
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);
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HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next DTIM %d\n",
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__func__, bs->bs_nextdtim);
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HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next beacon %d\n",
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__func__, nextTbtt);
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HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: beacon period %d\n",
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__func__, beaconintval);
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HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: DTIM period %d\n",
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__func__, dtimperiod);
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#undef CAB_TIMEOUT_VAL
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#undef BEACON_TIMEOUT_VAL
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#undef SLEEP_SLOP
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}
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