2000-12-01 09:36:25 +00:00
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/******************************************************************************
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*
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* Name: actbl1.h - ACPI 1.0 tables
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2000-12-21 06:56:46 +00:00
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* $Revision: 16 $
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2000-12-01 09:36:25 +00:00
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*
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*****************************************************************************/
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/******************************************************************************
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*
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* 1. Copyright Notice
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*
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2000-12-21 06:56:46 +00:00
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* Some or all of this work - Copyright (c) 1999, 2000, Intel Corp.
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* All rights reserved.
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2000-12-01 09:36:25 +00:00
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*
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* 2. License
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*
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* 2.1. This is your license from Intel Corp. under its intellectual property
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* rights. You may have additional license terms from the party that provided
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* you this software, covering your right to use that party's intellectual
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* property rights.
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*
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* 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a
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* copy of the source code appearing in this file ("Covered Code") an
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* irrevocable, perpetual, worldwide license under Intel's copyrights in the
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* base code distributed originally by Intel ("Original Intel Code") to copy,
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* make derivatives, distribute, use and display any portion of the Covered
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* Code in any form, with the right to sublicense such rights; and
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*
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* 2.3. Intel grants Licensee a non-exclusive and non-transferable patent
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* license (with the right to sublicense), under only those claims of Intel
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* patents that are infringed by the Original Intel Code, to make, use, sell,
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* offer to sell, and import the Covered Code and derivative works thereof
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* solely to the minimum extent necessary to exercise the above copyright
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* license, and in no event shall the patent license extend to any additions
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* to or modifications of the Original Intel Code. No other license or right
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* is granted directly or by implication, estoppel or otherwise;
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*
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* The above copyright and patent license is granted only if the following
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* conditions are met:
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*
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* 3. Conditions
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*
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* 3.1. Redistribution of Source with Rights to Further Distribute Source.
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* Redistribution of source code of any substantial portion of the Covered
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* Code or modification with rights to further distribute source must include
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* the above Copyright Notice, the above License, this list of Conditions,
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* and the following Disclaimer and Export Compliance provision. In addition,
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* Licensee must cause all Covered Code to which Licensee contributes to
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* contain a file documenting the changes Licensee made to create that Covered
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* Code and the date of any change. Licensee must include in that file the
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* documentation of any changes made by any predecessor Licensee. Licensee
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* must include a prominent statement that the modification is derived,
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* directly or indirectly, from Original Intel Code.
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*
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* 3.2. Redistribution of Source with no Rights to Further Distribute Source.
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* Redistribution of source code of any substantial portion of the Covered
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* Code or modification without rights to further distribute source must
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* include the following Disclaimer and Export Compliance provision in the
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* documentation and/or other materials provided with distribution. In
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* addition, Licensee may not authorize further sublicense of source of any
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* portion of the Covered Code, and must include terms to the effect that the
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* license from Licensee to its licensee is limited to the intellectual
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* property embodied in the software Licensee provides to its licensee, and
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* not to intellectual property embodied in modifications its licensee may
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* make.
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*
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* 3.3. Redistribution of Executable. Redistribution in executable form of any
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* substantial portion of the Covered Code or modification must reproduce the
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* above Copyright Notice, and the following Disclaimer and Export Compliance
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* provision in the documentation and/or other materials provided with the
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* distribution.
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*
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* 3.4. Intel retains all right, title, and interest in and to the Original
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* Intel Code.
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*
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* 3.5. Neither the name Intel nor any other trademark owned or controlled by
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* Intel shall be used in advertising or otherwise to promote the sale, use or
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* other dealings in products derived from or relating to the Covered Code
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* without prior written authorization from Intel.
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*
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* 4. Disclaimer and Export Compliance
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*
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* 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED
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* HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE
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* IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE,
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* INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY
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* UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY
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* IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A
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* PARTICULAR PURPOSE.
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*
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* 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES
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* OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR
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* COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT,
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* SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY
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* CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL
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* HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS
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* SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY
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* LIMITED REMEDY.
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*
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* 4.3. Licensee shall not export, either directly or indirectly, any of this
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* software or system incorporating such software without first obtaining any
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* required license or other approval from the U. S. Department of Commerce or
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* any other agency or department of the United States Government. In the
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* event Licensee exports any such software from the United States or
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* re-exports any such software from a foreign destination, Licensee shall
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* ensure that the distribution and export/re-export of the software is in
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* compliance with all laws, regulations, orders, or other restrictions of the
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* U.S. Export Administration Regulations. Licensee agrees that neither it nor
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* any of its subsidiaries will export/re-export any technical data, process,
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* software, or service, directly or indirectly, to any country for which the
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* United States government or any agency thereof requires an export license,
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* other governmental approval, or letter of assurance, without first obtaining
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* such license, approval or letter.
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*
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*****************************************************************************/
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#ifndef __ACTBL1_H__
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#define __ACTBL1_H__
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#pragma pack(1)
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/*************************************/
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/* ACPI Specification Rev 1.0 for */
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/* the Root System Description Table */
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/*************************************/
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typedef struct
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{
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ACPI_TABLE_HEADER header; /* Table header */
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UINT32 TableOffsetEntry [1]; /* Array of pointers to other */
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/* ACPI tables */
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} RSDT_DESCRIPTOR_REV1;
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/***************************************/
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/* ACPI Specification Rev 1.0 for */
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/* the Firmware ACPI Control Structure */
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/***************************************/
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typedef struct
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{
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NATIVE_CHAR Signature[4]; /* signature "FACS" */
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UINT32 Length; /* length of structure, in bytes */
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UINT32 HardwareSignature; /* hardware configuration signature */
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UINT32 FirmwareWakingVector; /* ACPI OS waking vector */
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UINT32 GlobalLock; /* Global Lock */
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UINT32_BIT S4Bios_f : 1; /* Indicates if S4BIOS support is present */
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UINT32_BIT Reserved1 : 31; /* must be 0 */
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UINT8 Resverved3 [40]; /* reserved - must be zero */
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} FACS_DESCRIPTOR_REV1;
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/************************************/
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/* ACPI Specification Rev 1.0 for */
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/* the Fixed ACPI Description Table */
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/************************************/
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typedef struct
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{
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ACPI_TABLE_HEADER header; /* table header */
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UINT32 FirmwareCtrl; /* Physical address of FACS */
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UINT32 Dsdt; /* Physical address of DSDT */
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UINT8 Model; /* System Interrupt Model */
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UINT8 Reserved1; /* reserved */
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UINT16 SciInt; /* System vector of SCI interrupt */
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UINT32 SmiCmd; /* Port address of SMI command port */
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UINT8 AcpiEnable; /* value to write to smi_cmd to enable ACPI */
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UINT8 AcpiDisable; /* value to write to smi_cmd to disable ACPI */
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UINT8 S4BiosReq; /* Value to write to SMI CMD to enter S4BIOS state */
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UINT8 Reserved2; /* reserved - must be zero */
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UINT32 Pm1aEvtBlk; /* Port address of Power Mgt 1a AcpiEvent Reg Blk */
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UINT32 Pm1bEvtBlk; /* Port address of Power Mgt 1b AcpiEvent Reg Blk */
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UINT32 Pm1aCntBlk; /* Port address of Power Mgt 1a Control Reg Blk */
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UINT32 Pm1bCntBlk; /* Port address of Power Mgt 1b Control Reg Blk */
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UINT32 Pm2CntBlk; /* Port address of Power Mgt 2 Control Reg Blk */
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UINT32 PmTmrBlk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
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UINT32 Gpe0Blk; /* Port addr of General Purpose AcpiEvent 0 Reg Blk */
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UINT32 Gpe1Blk; /* Port addr of General Purpose AcpiEvent 1 Reg Blk */
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UINT8 Pm1EvtLen; /* Byte Length of ports at pm1X_evt_blk */
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UINT8 Pm1CntLen; /* Byte Length of ports at pm1X_cnt_blk */
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UINT8 Pm2CntLen; /* Byte Length of ports at pm2_cnt_blk */
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UINT8 PmTmLen; /* Byte Length of ports at pm_tm_blk */
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UINT8 Gpe0BlkLen; /* Byte Length of ports at gpe0_blk */
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UINT8 Gpe1BlkLen; /* Byte Length of ports at gpe1_blk */
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UINT8 Gpe1Base; /* offset in gpe model where gpe1 events start */
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UINT8 Reserved3; /* reserved */
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UINT16 Plvl2Lat; /* worst case HW latency to enter/exit C2 state */
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UINT16 Plvl3Lat; /* worst case HW latency to enter/exit C3 state */
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UINT16 FlushSize; /* Size of area read to flush caches */
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UINT16 FlushStride; /* Stride used in flushing caches */
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UINT8 DutyOffset; /* bit location of duty cycle field in p_cnt reg */
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UINT8 DutyWidth; /* bit width of duty cycle field in p_cnt reg */
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UINT8 DayAlrm; /* index to day-of-month alarm in RTC CMOS RAM */
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UINT8 MonAlrm; /* index to month-of-year alarm in RTC CMOS RAM */
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UINT8 Century; /* index to century in RTC CMOS RAM */
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UINT8 Reserved4; /* reserved */
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UINT8 Reserved4a; /* reserved */
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UINT8 Reserved4b; /* reserved */
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UINT32_BIT WbInvd : 1; /* wbinvd instruction works properly */
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UINT32_BIT WbInvdFlush : 1; /* wbinvd flushes but does not invalidate */
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UINT32_BIT ProcC1 : 1; /* all processors support C1 state */
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UINT32_BIT Plvl2Up : 1; /* C2 state works on MP system */
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UINT32_BIT PwrButton : 1; /* Power button is handled as a generic feature */
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UINT32_BIT SleepButton : 1; /* Sleep button is handled as a generic feature, or not present */
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UINT32_BIT FixedRTC : 1; /* RTC wakeup stat not in fixed register space */
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UINT32_BIT Rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
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UINT32_BIT TmrValExt : 1; /* tmr_val is 32 bits */
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UINT32_BIT Reserved5 : 23; /* reserved - must be zero */
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} FADT_DESCRIPTOR_REV1;
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#pragma pack()
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#endif /* __ACTBL1_H__ */
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