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freebsd-dev/sys/conf/Makefile.riscv

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Welcome the RISC-V 64-bit kernel. This is the final step required allowing to compile and to run RISC-V kernel and userland from HEAD. RISC-V is a completely open ISA that is freely available to academia and industry. Thanks to all the people involved! Special thanks to Andrew Turner, David Chisnall, Ed Maste, Konstantin Belousov, John Baldwin and Arun Thomas for their help. Thanks to Robert Watson for organizing this project. This project sponsored by UK Higher Education Innovation Fund (HEIF5) and DARPA CTSRD project at the University of Cambridge Computer Laboratory. FreeBSD/RISC-V project home: https://wiki.freebsd.org/riscv Reviewed by: andrew, emaste, kib Relnotes: Yes Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D4982
2016-01-29 15:12:31 +00:00
# Makefile.riscv -- with config changes.
# Copyright 1990 W. Jolitz
# from: @(#)Makefile.i386 7.1 5/10/91
# from FreeBSD: src/sys/conf/Makefile.i386,v 1.255 2002/02/20 23:35:49
# $FreeBSD$
#
# Makefile for FreeBSD
#
# RISCVTODO: copy pasted from aarch64, needs to be
# constructed from a machine description:
# config machineid
# Most changes should be made in the machine description
# /sys/riscv/conf/``machineid''
# after which you should do
# config machineid
# Generic makefile changes should be made in
# /sys/conf/Makefile.riscv
# after which config should be rerun for all machines.
#
# Which version of config(8) is required.
Retire the GENERICSF kernel config. Now that hw.machine_arch handles soft-float vs hard-float there is no longer a reason for this config. Submitted by: mhorne (kern.mk hunk) Reviewed by: imp (earlier version), kp Sponsored by: DARPA Differential Revision: https://reviews.freebsd.org/D24544
2020-04-27 21:51:22 +00:00
%VERSREQ= 600012
Welcome the RISC-V 64-bit kernel. This is the final step required allowing to compile and to run RISC-V kernel and userland from HEAD. RISC-V is a completely open ISA that is freely available to academia and industry. Thanks to all the people involved! Special thanks to Andrew Turner, David Chisnall, Ed Maste, Konstantin Belousov, John Baldwin and Arun Thomas for their help. Thanks to Robert Watson for organizing this project. This project sponsored by UK Higher Education Innovation Fund (HEIF5) and DARPA CTSRD project at the University of Cambridge Computer Laboratory. FreeBSD/RISC-V project home: https://wiki.freebsd.org/riscv Reviewed by: andrew, emaste, kib Relnotes: Yes Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D4982
2016-01-29 15:12:31 +00:00
.if !defined(S)
S= ../../..
.endif
.include "$S/conf/kern.pre.mk"
INCLUDES+= -I$S/contrib/libfdt
Set the LMA of the riscv kernel to the OpenSBI jump target by default This allows us to boot FreeBSD RISCV on QEMU using the -kernel command line options. When using that option, QEMU maps the kernel ELF file to the addresses specified in the LMAs in the program headers. Since version 4.2 QEMU ships with OpenSBI fw_jump by default so this allows booting FreeBSD using the following command line: qemu-system-riscv64 -bios default -kernel /.../boot/kernel/kernel -nographic -M virt Without this change the -kernel option cannot be used since the LMAs start at address zero and QEMU already maps a ROM to these low physical addresses. For targets that require a different kernel LMA the make variable KERNEL_LMA can be overwritten in the config file. For example, adding `makeoptions KERNEL_LMA=0xc0200000` will create an ELF file that will be loaded at 0xc0200000. Before: There are 4 program headers, starting at offset 64 Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x001000 0xffffffc000000000 0x0000000000000000 0x75e598 0x8be318 RWE 0x1000 DYNAMIC 0x71fb20 0xffffffc00071eb20 0x000000000071eb20 0x000100 0x000100 RW 0x8 GNU_STACK 0x000000 0x0000000000000000 0x0000000000000000 0x000000 0x000000 RW 0x0 NOTE 0x693400 0xffffffc000692400 0x0000000000692400 0x000024 0x000024 R 0x4 After: There are 4 program headers, starting at offset 64 Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x001000 0xffffffc000000000 0x0000000080200000 0x734198 0x893e18 RWE 0x1000 DYNAMIC 0x6f7810 0xffffffc0006f6810 0x00000000808f6810 0x000100 0x000100 RW 0x8 GNU_STACK 0x000000 0x0000000000000000 0x0000000000000000 0x000000 0x000000 RW 0x0 NOTE 0x66ca70 0xffffffc00066ba70 0x000000008086ba70 0x000024 0x000024 R 0x4 Reviewed By: br, mhorne (earlier version) Differential Revision: https://reviews.freebsd.org/D23436
2020-02-04 00:06:16 +00:00
# Set the ELF LMA to the address that OpenSBI's fw_jump jumps to. This allows
# us to load the kernel with the -kernel flag in QEMU without having to embed
# it inside BBL or OpenSBI's fw_payload first.
# Note: For rv32 the start address is different (0x80400000).
# We set this value using --defsym rather than hardcoding it in ldscript.riscv
# so that different kernel configs can override the load address.
KERNEL_LMA?= 0x80200000
Simplify the RISC-V kernel linker invocation Remove our custom SYSTEM_LD definition. This generates program headers that are more consistent with other architectures, and more importantly, are in line with what loader(8) expects when loading a kernel. As noted in https://reviews.freebsd.org/D22920, there is no apparent reason why the kernel would need a writable text segment, so removal of the -N flag isn't likely to cause issue. Reviewed by: kp, br MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D24909
2020-05-22 18:54:56 +00:00
LDFLAGS+= --defsym='kernel_lma=${KERNEL_LMA}'
Support for v1.10 (latest) of RISC-V privilege specification. New version is not compatible on supervisor mode with v1.9.1 (previous version). Highlights: o BBL (Berkeley Boot Loader) provides no initial page tables anymore allowing us to choose VM, to build page tables manually and enable MMU in S-mode. o SBI interface changed. o GENERIC kernel. FDT is now chosen standard for RISC-V hardware description. DTB is now provided by Spike (golden model simulator). This allows us to introduce GENERIC kernel. However, description for console and timer devices is not provided in DTB, so move these devices temporary to nexus bus. o Supervisor can't access userspace by default. Solution is to set SUM (permit Supervisor User Memory access) bit in sstatus register. o Compressed extension is now turned on by default. o External GCC 7.1 compiler used. o _gp renamed to __global_pointer$ o Compiler -march= string is now in use allowing us to choose required extensions (compressed, FPU, atomic, etc). Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D11800
2017-08-10 14:18:09 +00:00
Welcome the RISC-V 64-bit kernel. This is the final step required allowing to compile and to run RISC-V kernel and userland from HEAD. RISC-V is a completely open ISA that is freely available to academia and industry. Thanks to all the people involved! Special thanks to Andrew Turner, David Chisnall, Ed Maste, Konstantin Belousov, John Baldwin and Arun Thomas for their help. Thanks to Robert Watson for organizing this project. This project sponsored by UK Higher Education Innovation Fund (HEIF5) and DARPA CTSRD project at the University of Cambridge Computer Laboratory. FreeBSD/RISC-V project home: https://wiki.freebsd.org/riscv Reviewed by: andrew, emaste, kib Relnotes: Yes Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D4982
2016-01-29 15:12:31 +00:00
.if !empty(DDB_ENABLED)
Add support for ddb(4). Sponsored by: DARPA, AFRL Sponsored by: HEIF5
2016-03-10 15:51:43 +00:00
CFLAGS += -fno-omit-frame-pointer -fno-optimize-sibling-calls
Welcome the RISC-V 64-bit kernel. This is the final step required allowing to compile and to run RISC-V kernel and userland from HEAD. RISC-V is a completely open ISA that is freely available to academia and industry. Thanks to all the people involved! Special thanks to Andrew Turner, David Chisnall, Ed Maste, Konstantin Belousov, John Baldwin and Arun Thomas for their help. Thanks to Robert Watson for organizing this project. This project sponsored by UK Higher Education Innovation Fund (HEIF5) and DARPA CTSRD project at the University of Cambridge Computer Laboratory. FreeBSD/RISC-V project home: https://wiki.freebsd.org/riscv Reviewed by: andrew, emaste, kib Relnotes: Yes Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D4982
2016-01-29 15:12:31 +00:00
.endif
Set dependencies for genassym.c. This fixes non-parallel build.
2016-05-24 16:30:05 +00:00
# hack because genassym.c includes sys/bus.h which includes these.
genassym.o: bus_if.h device_if.h
Welcome the RISC-V 64-bit kernel. This is the final step required allowing to compile and to run RISC-V kernel and userland from HEAD. RISC-V is a completely open ISA that is freely available to academia and industry. Thanks to all the people involved! Special thanks to Andrew Turner, David Chisnall, Ed Maste, Konstantin Belousov, John Baldwin and Arun Thomas for their help. Thanks to Robert Watson for organizing this project. This project sponsored by UK Higher Education Innovation Fund (HEIF5) and DARPA CTSRD project at the University of Cambridge Computer Laboratory. FreeBSD/RISC-V project home: https://wiki.freebsd.org/riscv Reviewed by: andrew, emaste, kib Relnotes: Yes Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D4982
2016-01-29 15:12:31 +00:00
%BEFORE_DEPEND
%OBJS
%FILES.c
%FILES.s
%FILES.m
%CLEAN
%RULES
.include "$S/conf/kern.post.mk"
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