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freebsd-dev/sys/x86/isa/atpic.c

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Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
/*-
sys/x86: further adoption of SPDX licensing ID tags. Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
2017-11-27 15:11:47 +00:00
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
* Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* PIC driver for the 8259A Master and Slave PICs in PC/AT machines.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "opt_auto_eoi.h"
#include "opt_isa.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/interrupt.h>
#include <sys/kernel.h>
#include <sys/lock.h>
Add some missing <sys/module.h> includes which are masked by the one on death-row in <sys/kernel.h>
2004-05-30 17:57:46 +00:00
#include <sys/module.h>
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
#include <machine/cpufunc.h>
#include <machine/frame.h>
#include <machine/intr_machdep.h>
#include <machine/md_var.h>
#include <machine/resource.h>
#include <machine/segments.h>
- Use i8259A register defines from shared sys/dev/ic/i8259.h rather than from the i386-specific icu.h. - Replace PC98 magic numbers with equivalent register define values along with comments about PC-98 "quirks".
2004-01-06 19:07:08 +00:00
#include <dev/ic/i8259.h>
Introduce the new kernel sub-tree x86 which should contain all the code shared and generalized between our current amd64, i386 and pc98. This is just an initial step that should lead to a more complete effort. For the moment, a very simple porting of cpufreq modules, BIOS calls and the whole MD specific ISA bus part is added to the sub-tree but ideally a lot of code might be added and more shared support should grow. Sponsored by: Sandvine Incorporated Reviewed by: emaste, kib, jhb, imp Discussed on: arch MFC: 3 weeks
2010-02-25 14:13:39 +00:00
#include <x86/isa/icu.h>
Remove vestiges of knowing the ISA bus, which we gave up on around 20 years ago. Remove redunant copy of isaregs.h.
2014-03-19 21:03:04 +00:00
#include <isa/isareg.h>
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
#include <isa/isavar.h>
Introduce the new kernel sub-tree x86 which should contain all the code shared and generalized between our current amd64, i386 and pc98. This is just an initial step that should lead to a more complete effort. For the moment, a very simple porting of cpufreq modules, BIOS calls and the whole MD specific ISA bus part is added to the sub-tree but ideally a lot of code might be added and more shared support should grow. Sponsored by: Sandvine Incorporated Reviewed by: emaste, kib, jhb, imp Discussed on: arch MFC: 3 weeks
2010-02-25 14:13:39 +00:00
#ifdef __amd64__
#define SDT_ATPIC SDT_SYSIGT
#define GSEL_ATPIC 0
#else
#define SDT_ATPIC SDT_SYS386IGT
#define GSEL_ATPIC GSEL(GCODE_SEL, SEL_KPL)
#endif
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
#define MASTER 0
#define SLAVE 1
- Add an IMEN_MASK macro that returns the 8-bit bitmask of an atpic interrupt source. - Only do an outb() to the PIC to clear a bit in imen if the bit is set. - Add a NUM_ISA_IRQS macro to replace uglier 'sizeof(array) / sizeof(member)' expressions along with a CTASSERT() to ensure that the macro is correct.
2004-05-03 14:52:41 +00:00
Remove 'imen' global variable from atpic(4). In pre-SMPng, the global 'imen' was used to track mask state of the hardware interrupts and was aligned to the masks used by spl*(). When the atpic code was converted to using the x86 interrupt source abstraction, the global 'imen' was preserved by having each PIC instance point to an invididual byte in the global 'imen' to hold its 8-bit interrupt mask. The global 'imen' is no longer used for anything however, so rather than storing pointers in 'struct atpic', just store the individual 8-bit mask for each PIC as a char. While here, convert the ATPIC macro to using C99 initializers. Reviewed by: kib, imp MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D16827
2018-08-21 17:13:51 +00:00
#define IMEN_MASK(ai) (IRQ_MASK((ai)->at_irq))
- Add an IMEN_MASK macro that returns the 8-bit bitmask of an atpic interrupt source. - Only do an outb() to the PIC to clear a bit in imen if the bit is set. - Add a NUM_ISA_IRQS macro to replace uglier 'sizeof(array) / sizeof(member)' expressions along with a CTASSERT() to ensure that the macro is correct.
2004-05-03 14:52:41 +00:00
#define NUM_ISA_IRQS 16
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
static void atpic_init(void *dummy);
inthand_t
IDTVEC(atpic_intr0), IDTVEC(atpic_intr1), IDTVEC(atpic_intr2),
IDTVEC(atpic_intr3), IDTVEC(atpic_intr4), IDTVEC(atpic_intr5),
IDTVEC(atpic_intr6), IDTVEC(atpic_intr7), IDTVEC(atpic_intr8),
IDTVEC(atpic_intr9), IDTVEC(atpic_intr10), IDTVEC(atpic_intr11),
IDTVEC(atpic_intr12), IDTVEC(atpic_intr13), IDTVEC(atpic_intr14),
IDTVEC(atpic_intr15);
PTI for amd64. The implementation of the Kernel Page Table Isolation (KPTI) for amd64, first version. It provides a workaround for the 'meltdown' vulnerability. PTI is turned off by default for now, enable with the loader tunable vm.pmap.pti=1. The pmap page table is split into kernel-mode table and user-mode table. Kernel-mode table is identical to the non-PTI table, while usermode table is obtained from kernel table by leaving userspace mappings intact, but only leaving the following parts of the kernel mapped: kernel text (but not modules text) PCPU GDT/IDT/user LDT/task structures IST stacks for NMI and doublefault handlers. Kernel switches to user page table before returning to usermode, and restores full kernel page table on the entry. Initial kernel-mode stack for PTI trampoline is allocated in PCPU, it is only 16 qwords. Kernel entry trampoline switches page tables. then the hardware trap frame is copied to the normal kstack, and execution continues. IST stacks are kept mapped and no trampoline is needed for NMI/doublefault, but of course page table switch is performed. On return to usermode, the trampoline is used again, iret frame is copied to the trampoline stack, page tables are switched and iretq is executed. The case of iretq faulting due to the invalid usermode context is tricky, since the frame for fault is appended to the trampoline frame. Besides copying the fault frame and original (corrupted) frame to kstack, the fault frame must be patched to make it look as if the fault occured on the kstack, see the comment in doret_iret detection code in trap(). Currently kernel pages which are mapped during trampoline operation are identical for all pmaps. They are registered using pmap_pti_add_kva(). Besides initial registrations done during boot, LDT and non-common TSS segments are registered if user requested their use. In principle, they can be installed into kernel page table per pmap with some work. Similarly, PCPU can be hidden from userspace mapping using trampoline PCPU page, but again I do not see much benefits besides complexity. PDPE pages for the kernel half of the user page tables are pre-allocated during boot because we need to know pml4 entries which are copied to the top-level paging structure page, in advance on a new pmap creation. I enforce this to avoid iterating over the all existing pmaps if a new PDPE page is needed for PTI kernel mappings. The iteration is a known problematic operation on i386. The need to flush hidden kernel translations on the switch to user mode make global tables (PG_G) meaningless and even harming, so PG_G use is disabled for PTI case. Our existing use of PCID is incompatible with PTI and is automatically disabled if PTI is enabled. PCID can be forced on only for developer's benefit. MCE is known to be broken, it requires IST stack to operate completely correctly even for non-PTI case, and absolutely needs dedicated IST stack because MCE delivery while trampoline did not switched from PTI stack is fatal. The fix is pending. Reviewed by: markj (partially) Tested by: pho (previous version) Discussed with: jeff, jhb Sponsored by: The FreeBSD Foundation MFC after: 2 weeks
2018-01-17 11:44:21 +00:00
/* XXXKIB i386 uses stubs until pti comes */
inthand_t
IDTVEC(atpic_intr0_pti), IDTVEC(atpic_intr1_pti),
IDTVEC(atpic_intr2_pti), IDTVEC(atpic_intr3_pti),
IDTVEC(atpic_intr4_pti), IDTVEC(atpic_intr5_pti),
IDTVEC(atpic_intr6_pti), IDTVEC(atpic_intr7_pti),
IDTVEC(atpic_intr8_pti), IDTVEC(atpic_intr9_pti),
IDTVEC(atpic_intr10_pti), IDTVEC(atpic_intr11_pti),
IDTVEC(atpic_intr12_pti), IDTVEC(atpic_intr13_pti),
IDTVEC(atpic_intr14_pti), IDTVEC(atpic_intr15_pti);
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
#define IRQ(ap, ai) ((ap)->at_irqbase + (ai)->at_irq)
Remove 'imen' global variable from atpic(4). In pre-SMPng, the global 'imen' was used to track mask state of the hardware interrupts and was aligned to the masks used by spl*(). When the atpic code was converted to using the x86 interrupt source abstraction, the global 'imen' was preserved by having each PIC instance point to an invididual byte in the global 'imen' to hold its 8-bit interrupt mask. The global 'imen' is no longer used for anything however, so rather than storing pointers in 'struct atpic', just store the individual 8-bit mask for each PIC as a char. While here, convert the ATPIC macro to using C99 initializers. Reviewed by: kib, imp MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D16827
2018-08-21 17:13:51 +00:00
#define ATPIC(io, base, eoi) { \
.at_pic = { \
Dynamically allocate IRQ ranges on x86. Previously, x86 used static ranges of IRQ values for different types of I/O interrupts. Interrupt pins on I/O APICs and 8259A PICs used IRQ values from 0 to 254. MSI interrupts used a compile-time-defined range starting at 256, and Xen event channels used a compile-time-defined range after MSI. Some recent systems have more than 255 I/O APIC interrupt pins which resulted in those IRQ values overflowing into the MSI range triggering an assertion failure. Replace statically assigned ranges with dynamic ranges. Do a single pass computing the sizes of the IRQ ranges (PICs, MSI, Xen) to determine the total number of IRQs required. Allocate the interrupt source and interrupt count arrays dynamically once this pass has completed. To minimize runtime complexity these arrays are only sized once during bootup. The PIC range is determined by the PICs present in the system. The MSI and Xen ranges continue to use a fixed size, though this does make it possible to turn the MSI range size into a tunable in the future. As a result, various places are updated to use dynamic limits instead of constants. In addition, the vmstat(8) utility has been taught to understand that some kernels may treat 'intrcnt' and 'intrnames' as pointers rather than arrays when extracting interrupt stats from a crashdump. This is determined by the presence (vs absence) of a global 'nintrcnt' symbol. This change reverts r189404 which worked around a buggy BIOS which enumerated an I/O APIC twice (using the same memory mapped address for both entries but using an IRQ base of 256 for one entry and a valid IRQ base for the second entry). Making the "base" of MSI IRQ values dynamic avoids the panic that r189404 worked around, and there may now be valid I/O APICs with an IRQ base above 256 which this workaround would incorrectly skip. If in the future the issue reported in PR 130483 reoccurs, we will have to add a pass over the I/O APIC entries in the MADT to detect duplicates using the memory mapped address and use some strategy to choose the "correct" one. While here, reserve room in intrcnts for the Hyper-V counters. PR: 229429, 130483 Reviewed by: kib, royger, cem Tested by: royger (Xen), kib (DMAR) Approved by: re (gjb) MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D16861
2018-08-28 21:09:19 +00:00
.pic_register_sources = atpic_register_sources, \
Remove 'imen' global variable from atpic(4). In pre-SMPng, the global 'imen' was used to track mask state of the hardware interrupts and was aligned to the masks used by spl*(). When the atpic code was converted to using the x86 interrupt source abstraction, the global 'imen' was preserved by having each PIC instance point to an invididual byte in the global 'imen' to hold its 8-bit interrupt mask. The global 'imen' is no longer used for anything however, so rather than storing pointers in 'struct atpic', just store the individual 8-bit mask for each PIC as a char. While here, convert the ATPIC macro to using C99 initializers. Reviewed by: kib, imp MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D16827
2018-08-21 17:13:51 +00:00
.pic_enable_source = atpic_enable_source, \
.pic_disable_source = atpic_disable_source, \
.pic_eoi_source = (eoi), \
.pic_enable_intr = atpic_enable_intr, \
.pic_disable_intr = atpic_disable_intr, \
.pic_vector = atpic_vector, \
.pic_source_pending = atpic_source_pending, \
.pic_resume = atpic_resume, \
.pic_config_intr = atpic_config_intr, \
.pic_assign_cpu = atpic_assign_cpu \
}, \
.at_ioaddr = (io), \
.at_irqbase = (base), \
.at_intbase = IDT_IO_INTS + (base), \
.at_imen = 0xff, \
}
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
#define INTSRC(irq) \
- Add a member to the atpic interrupt source structures to indicate if the IRQ is edge triggered or level triggered. For ISA interrupts, we assume that edge triggered interrupts are always active high and that level triggered interrupts are always active low. - Don't disable an edge triggered interrupt in the PIC. This avoids outb instructions to the actual PIC for traditional ISA IRQs such as IRQ 1, 6, 14, and 15. (Fast interrupts such as IRQs 0 and 8 don't mask their source, so this doesn't change anything for them.) - For MCA systems we assume that all interrupts are level triggered and thus need masking. Otherwise, we probe the ELCR. If it exists we trust what it tells us regarding which interrupts are level triggered. If it does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered and that all other IRQs are level triggered and need masking. - Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
{ { &atpics[(irq) / 8].at_pic }, IDTVEC(atpic_intr ## irq ), \
PTI for amd64. The implementation of the Kernel Page Table Isolation (KPTI) for amd64, first version. It provides a workaround for the 'meltdown' vulnerability. PTI is turned off by default for now, enable with the loader tunable vm.pmap.pti=1. The pmap page table is split into kernel-mode table and user-mode table. Kernel-mode table is identical to the non-PTI table, while usermode table is obtained from kernel table by leaving userspace mappings intact, but only leaving the following parts of the kernel mapped: kernel text (but not modules text) PCPU GDT/IDT/user LDT/task structures IST stacks for NMI and doublefault handlers. Kernel switches to user page table before returning to usermode, and restores full kernel page table on the entry. Initial kernel-mode stack for PTI trampoline is allocated in PCPU, it is only 16 qwords. Kernel entry trampoline switches page tables. then the hardware trap frame is copied to the normal kstack, and execution continues. IST stacks are kept mapped and no trampoline is needed for NMI/doublefault, but of course page table switch is performed. On return to usermode, the trampoline is used again, iret frame is copied to the trampoline stack, page tables are switched and iretq is executed. The case of iretq faulting due to the invalid usermode context is tricky, since the frame for fault is appended to the trampoline frame. Besides copying the fault frame and original (corrupted) frame to kstack, the fault frame must be patched to make it look as if the fault occured on the kstack, see the comment in doret_iret detection code in trap(). Currently kernel pages which are mapped during trampoline operation are identical for all pmaps. They are registered using pmap_pti_add_kva(). Besides initial registrations done during boot, LDT and non-common TSS segments are registered if user requested their use. In principle, they can be installed into kernel page table per pmap with some work. Similarly, PCPU can be hidden from userspace mapping using trampoline PCPU page, but again I do not see much benefits besides complexity. PDPE pages for the kernel half of the user page tables are pre-allocated during boot because we need to know pml4 entries which are copied to the top-level paging structure page, in advance on a new pmap creation. I enforce this to avoid iterating over the all existing pmaps if a new PDPE page is needed for PTI kernel mappings. The iteration is a known problematic operation on i386. The need to flush hidden kernel translations on the switch to user mode make global tables (PG_G) meaningless and even harming, so PG_G use is disabled for PTI case. Our existing use of PCID is incompatible with PTI and is automatically disabled if PTI is enabled. PCID can be forced on only for developer's benefit. MCE is known to be broken, it requires IST stack to operate completely correctly even for non-PTI case, and absolutely needs dedicated IST stack because MCE delivery while trampoline did not switched from PTI stack is fatal. The fix is pending. Reviewed by: markj (partially) Tested by: pho (previous version) Discussed with: jeff, jhb Sponsored by: The FreeBSD Foundation MFC after: 2 weeks
2018-01-17 11:44:21 +00:00
IDTVEC(atpic_intr ## irq ## _pti), (irq) % 8 }
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
struct atpic {
struct pic at_pic;
int at_ioaddr;
int at_irqbase;
uint8_t at_intbase;
Remove 'imen' global variable from atpic(4). In pre-SMPng, the global 'imen' was used to track mask state of the hardware interrupts and was aligned to the masks used by spl*(). When the atpic code was converted to using the x86 interrupt source abstraction, the global 'imen' was preserved by having each PIC instance point to an invididual byte in the global 'imen' to hold its 8-bit interrupt mask. The global 'imen' is no longer used for anything however, so rather than storing pointers in 'struct atpic', just store the individual 8-bit mask for each PIC as a char. While here, convert the ATPIC macro to using C99 initializers. Reviewed by: kib, imp MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D16827
2018-08-21 17:13:51 +00:00
uint8_t at_imen;
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
};
struct atpic_intsrc {
struct intsrc at_intsrc;
PTI for amd64. The implementation of the Kernel Page Table Isolation (KPTI) for amd64, first version. It provides a workaround for the 'meltdown' vulnerability. PTI is turned off by default for now, enable with the loader tunable vm.pmap.pti=1. The pmap page table is split into kernel-mode table and user-mode table. Kernel-mode table is identical to the non-PTI table, while usermode table is obtained from kernel table by leaving userspace mappings intact, but only leaving the following parts of the kernel mapped: kernel text (but not modules text) PCPU GDT/IDT/user LDT/task structures IST stacks for NMI and doublefault handlers. Kernel switches to user page table before returning to usermode, and restores full kernel page table on the entry. Initial kernel-mode stack for PTI trampoline is allocated in PCPU, it is only 16 qwords. Kernel entry trampoline switches page tables. then the hardware trap frame is copied to the normal kstack, and execution continues. IST stacks are kept mapped and no trampoline is needed for NMI/doublefault, but of course page table switch is performed. On return to usermode, the trampoline is used again, iret frame is copied to the trampoline stack, page tables are switched and iretq is executed. The case of iretq faulting due to the invalid usermode context is tricky, since the frame for fault is appended to the trampoline frame. Besides copying the fault frame and original (corrupted) frame to kstack, the fault frame must be patched to make it look as if the fault occured on the kstack, see the comment in doret_iret detection code in trap(). Currently kernel pages which are mapped during trampoline operation are identical for all pmaps. They are registered using pmap_pti_add_kva(). Besides initial registrations done during boot, LDT and non-common TSS segments are registered if user requested their use. In principle, they can be installed into kernel page table per pmap with some work. Similarly, PCPU can be hidden from userspace mapping using trampoline PCPU page, but again I do not see much benefits besides complexity. PDPE pages for the kernel half of the user page tables are pre-allocated during boot because we need to know pml4 entries which are copied to the top-level paging structure page, in advance on a new pmap creation. I enforce this to avoid iterating over the all existing pmaps if a new PDPE page is needed for PTI kernel mappings. The iteration is a known problematic operation on i386. The need to flush hidden kernel translations on the switch to user mode make global tables (PG_G) meaningless and even harming, so PG_G use is disabled for PTI case. Our existing use of PCID is incompatible with PTI and is automatically disabled if PTI is enabled. PCID can be forced on only for developer's benefit. MCE is known to be broken, it requires IST stack to operate completely correctly even for non-PTI case, and absolutely needs dedicated IST stack because MCE delivery while trampoline did not switched from PTI stack is fatal. The fix is pending. Reviewed by: markj (partially) Tested by: pho (previous version) Discussed with: jeff, jhb Sponsored by: The FreeBSD Foundation MFC after: 2 weeks
2018-01-17 11:44:21 +00:00
inthand_t *at_intr, *at_intr_pti;
- Add a member to the atpic interrupt source structures to indicate if the IRQ is edge triggered or level triggered. For ISA interrupts, we assume that edge triggered interrupts are always active high and that level triggered interrupts are always active low. - Don't disable an edge triggered interrupt in the PIC. This avoids outb instructions to the actual PIC for traditional ISA IRQs such as IRQ 1, 6, 14, and 15. (Fast interrupts such as IRQs 0 and 8 don't mask their source, so this doesn't change anything for them.) - For MCA systems we assume that all interrupts are level triggered and thus need masking. Otherwise, we probe the ELCR. If it exists we trust what it tells us regarding which interrupts are level triggered. If it does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered and that all other IRQs are level triggered and need masking. - Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
int at_irq; /* Relative to PIC base. */
enum intr_trigger at_trigger;
- Add counts to the ATPIC interrupt sources and point the ATPIC interrupt source count pointers at them so that intr_execute_handlers() won't choke when it tries to handle an unregisterd ATPIC interrupt source. - Install the low-level ATPIC interrupt handlers when we first program the ATPIC in atpic_startup() rather than at SI_SUB_INTR. This is only necessary to work around buggy code that enables interrupts too early in the boot process (namely, the vm86 code). Approved by: re (rwatson)
2003-11-19 15:38:56 +00:00
u_long at_count;
u_long at_straycount;
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
};
Dynamically allocate IRQ ranges on x86. Previously, x86 used static ranges of IRQ values for different types of I/O interrupts. Interrupt pins on I/O APICs and 8259A PICs used IRQ values from 0 to 254. MSI interrupts used a compile-time-defined range starting at 256, and Xen event channels used a compile-time-defined range after MSI. Some recent systems have more than 255 I/O APIC interrupt pins which resulted in those IRQ values overflowing into the MSI range triggering an assertion failure. Replace statically assigned ranges with dynamic ranges. Do a single pass computing the sizes of the IRQ ranges (PICs, MSI, Xen) to determine the total number of IRQs required. Allocate the interrupt source and interrupt count arrays dynamically once this pass has completed. To minimize runtime complexity these arrays are only sized once during bootup. The PIC range is determined by the PICs present in the system. The MSI and Xen ranges continue to use a fixed size, though this does make it possible to turn the MSI range size into a tunable in the future. As a result, various places are updated to use dynamic limits instead of constants. In addition, the vmstat(8) utility has been taught to understand that some kernels may treat 'intrcnt' and 'intrnames' as pointers rather than arrays when extracting interrupt stats from a crashdump. This is determined by the presence (vs absence) of a global 'nintrcnt' symbol. This change reverts r189404 which worked around a buggy BIOS which enumerated an I/O APIC twice (using the same memory mapped address for both entries but using an IRQ base of 256 for one entry and a valid IRQ base for the second entry). Making the "base" of MSI IRQ values dynamic avoids the panic that r189404 worked around, and there may now be valid I/O APICs with an IRQ base above 256 which this workaround would incorrectly skip. If in the future the issue reported in PR 130483 reoccurs, we will have to add a pass over the I/O APIC entries in the MADT to detect duplicates using the memory mapped address and use some strategy to choose the "correct" one. While here, reserve room in intrcnts for the Hyper-V counters. PR: 229429, 130483 Reviewed by: kib, royger, cem Tested by: royger (Xen), kib (DMAR) Approved by: re (gjb) MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D16861
2018-08-28 21:09:19 +00:00
static void atpic_register_sources(struct pic *pic);
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
static void atpic_enable_source(struct intsrc *isrc);
Optimize intr_execute_handlers() by combining the pic_disable_source() and pic_eoi_source() into one call. This halves the number of spinlock operations and indirect function calls in the normal case of handling a normal (ithread) interrupt. Optimize the atpic and ioapic drivers to use inlines where appropriate in supporting the intr_execute_handlers() change. This knocks 900ns, or roughly 1350 cycles, off of the time spent servicing an interrupt in the common case on my 1.5GHz P4 uniprocessor system. SMP systems likely won't see as much of a gain due to the ioapic being more efficient than the atpic. I'll investigate porting this to amd64 soon. Reviewed by: jhb
2004-08-02 15:31:10 +00:00
static void atpic_disable_source(struct intsrc *isrc, int eoi);
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
static void atpic_eoi_master(struct intsrc *isrc);
static void atpic_eoi_slave(struct intsrc *isrc);
static void atpic_enable_intr(struct intsrc *isrc);
Minor fixes and tweaks to the x86 interrupt code: - Split the intr_table_lock into an sx lock used for most things, and a spin lock to protect intrcnt_index. Originally I had this as a spin lock so interrupt code could use it to lookup sources. However, we don't actually do that because it would add a lot of overhead to interrupts, and if we ever do support removing interrupt sources, we can use other means to safely do so w/o locking in the interrupt handling code. - Replace is_enabled (boolean) with is_handlers (a count of handlers) to determine if a source is enabled or not. This allows us to notice when a source is no longer in use. When that happens, we now invoke a new PIC method (pic_disable_intr()) to inform the PIC driver that the source is no longer in use. The I/O APIC driver frees the APIC IDT vector when this happens. The MSI driver no longer needs to have a hack to clear is_enabled during msi_alloc() and msix_alloc() as a result of this change as well. - Add an apic_disable_vector() to reset an IDT vector back to Xrsvd to complement apic_enable_vector() and use it in the I/O APIC and MSI code when freeing an IDT vector. - Add a new nexus hook: nexus_add_irq() to ask the nexus driver to add an IRQ to its irq_rman. The MSI code uses this when it creates new interrupt sources to let the nexus know about newly valid IRQs. Previously the msi_alloc() and msix_alloc() passed some extra stuff back to the nexus methods which then added the IRQs. This approach is a bit cleaner. - Change the MSI sx lock to a mutex. If we need to create new sources, drop the lock, create the required number of sources, then get the lock and try the allocation again.
2007-05-08 21:29:14 +00:00
static void atpic_disable_intr(struct intsrc *isrc);
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
static int atpic_vector(struct intsrc *isrc);
Add support for suspend/resume/migration operations when running as a Xen PVHVM guest. Submitted by: Roger Pau Monné Sponsored by: Citrix Systems R&D Reviewed by: gibbs Approved by: re (blanket Xen) MFC after: 2 weeks sys/amd64/amd64/mp_machdep.c: sys/i386/i386/mp_machdep.c: - Make sure that are no MMU related IPIs pending on migration. - Reset pending IPI_BITMAP on resume. - Init vcpu_info on resume. sys/amd64/include/intr_machdep.h: sys/i386/include/intr_machdep.h: sys/x86/acpica/acpi_wakeup.c: sys/x86/x86/intr_machdep.c: sys/x86/isa/atpic.c: sys/x86/x86/io_apic.c: sys/x86/x86/local_apic.c: - Add a "suspend_cancelled" parameter to pic_resume(). For the Xen PIC, restoration of interrupt services differs between the aborted suspend and normal resume cases, so we must provide this information. sys/dev/acpica/acpi_timer.c: sys/dev/xen/timer/timer.c: sys/timetc.h: - Don't swap out "suspend safe" timers across a suspend/resume cycle. This includes the Xen PV and ACPI timers. sys/dev/xen/control/control.c: - Perform proper suspend/resume process for PVHVM: - Suspend all APs before going into suspension, this allows us to reset the vcpu_info on resume for each AP. - Reset shared info page and callback on resume. sys/dev/xen/timer/timer.c: - Implement suspend/resume support for the PV timer. Since FreeBSD doesn't perform a per-cpu resume of the timer, we need to call smp_rendezvous in order to correctly resume the timer on each CPU. sys/dev/xen/xenpci/xenpci.c: - Don't reset the PCI interrupt on each suspend/resume. sys/kern/subr_smp.c: - When suspending a PVHVM domain make sure there are no MMU IPIs in-flight, or we will get a lockup on resume due to the fact that pending event channels are not carried over on migration. - Implement a generic version of restart_cpus that can be used by suspended and stopped cpus. sys/x86/xen/hvm.c: - Implement resume support for the hypercall page and shared info. - Clear vcpu_info so it can be reset by APs when resuming from suspension. sys/dev/xen/xenpci/xenpci.c: sys/x86/xen/hvm.c: sys/x86/xen/xen_intr.c: - Support UP kernel configurations. sys/x86/xen/xen_intr.c: - Properly rebind per-cpus VIRQs and IPIs on resume.
2013-09-20 05:06:03 +00:00
static void atpic_resume(struct pic *pic, bool suspend_cancelled);
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
static int atpic_source_pending(struct intsrc *isrc);
- Add a new pic method pic_config_intr() to set the trigger mode and polarity for a specified IRQ. The intr_config_intr() function wraps this pic method hiding the IRQ to interrupt source lookup. - Add a config_intr() method to the atpic(4) driver that reconfigures the interrupt using the ELCR if possible and returns an error otherwise. - Add a config_intr() method to the apic(4) driver that just logs any requests that would change the existing programming under bootverbose. Currently, the only changes the apic(4) driver receives are due to bugs in the acpi(4) driver and its handling of link devices, hence the reason for such requests currently being ignored. - Have the nexus(4) driver on i386 implement the bus_config_intr() function by calling intr_config_intr().
2004-05-04 21:02:56 +00:00
static int atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
enum intr_polarity pol);
Improve the handling of cpuset with interrupts. - For x86, change the interrupt source method to assign an interrupt source to a specific CPU to return an error value instead of void, thus allowing it to fail. - If moving an interrupt to a CPU fails due to a lack of IDT vectors in the destination CPU, fail the request with ENOSPC rather than panicing. - For MSI interrupts on x86 (but not MSI-X), only allow cpuset to be used on the first interrupt in a group. Moving the first interrupt in a group moves the entire group. - Use the icu_lock to protect intr_next_cpu() on x86 instead of the intr_table_lock to fix a LOR introduced in the last set of MSI changes. - Add a new privilege PRIV_SCHED_CPUSET_INTR for using cpuset with interrupts. Previously, binding an interrupt to a CPU only performed a privilege check if the interrupt had an interrupt thread. Interrupts without a thread could be bound by non-root users as a result. - If an interrupt event's assign_cpu method fails, then restore the original cpuset mask for the associated interrupt thread. Approved by: re (kib)
2009-07-01 17:20:07 +00:00
static int atpic_assign_cpu(struct intsrc *isrc, u_int apic_id);
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
static void i8259_init(struct atpic *pic, int slave);
static struct atpic atpics[] = {
Remove 'imen' global variable from atpic(4). In pre-SMPng, the global 'imen' was used to track mask state of the hardware interrupts and was aligned to the masks used by spl*(). When the atpic code was converted to using the x86 interrupt source abstraction, the global 'imen' was preserved by having each PIC instance point to an invididual byte in the global 'imen' to hold its 8-bit interrupt mask. The global 'imen' is no longer used for anything however, so rather than storing pointers in 'struct atpic', just store the individual 8-bit mask for each PIC as a char. While here, convert the ATPIC macro to using C99 initializers. Reviewed by: kib, imp MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D16827
2018-08-21 17:13:51 +00:00
ATPIC(IO_ICU1, 0, atpic_eoi_master),
ATPIC(IO_ICU2, 8, atpic_eoi_slave)
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
};
static struct atpic_intsrc atintrs[] = {
INTSRC(0),
INTSRC(1),
INTSRC(2),
INTSRC(3),
INTSRC(4),
INTSRC(5),
INTSRC(6),
INTSRC(7),
INTSRC(8),
INTSRC(9),
INTSRC(10),
INTSRC(11),
INTSRC(12),
INTSRC(13),
INTSRC(14),
INTSRC(15),
};
X86: use our nitems() macro when it is avaliable through param.h. No functional change, only trivial cases are done in this sweep, Discussed in: freebsd-current
2016-04-19 23:41:46 +00:00
CTASSERT(nitems(atintrs) == NUM_ISA_IRQS);
- Add an IMEN_MASK macro that returns the 8-bit bitmask of an atpic interrupt source. - Only do an outb() to the PIC to clear a bit in imen if the bit is set. - Add a NUM_ISA_IRQS macro to replace uglier 'sizeof(array) / sizeof(member)' expressions along with a CTASSERT() to ensure that the macro is correct.
2004-05-03 14:52:41 +00:00
Optimize intr_execute_handlers() by combining the pic_disable_source() and pic_eoi_source() into one call. This halves the number of spinlock operations and indirect function calls in the normal case of handling a normal (ithread) interrupt. Optimize the atpic and ioapic drivers to use inlines where appropriate in supporting the intr_execute_handlers() change. This knocks 900ns, or roughly 1350 cycles, off of the time spent servicing an interrupt in the common case on my 1.5GHz P4 uniprocessor system. SMP systems likely won't see as much of a gain due to the ioapic being more efficient than the atpic. I'll investigate porting this to amd64 soon. Reviewed by: jhb
2004-08-02 15:31:10 +00:00
static __inline void
_atpic_eoi_master(struct intsrc *isrc)
{
KASSERT(isrc->is_pic == &atpics[MASTER].at_pic,
("%s: mismatched pic", __func__));
#ifndef AUTO_EOI_1
outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
#endif
}
/*
* The data sheet says no auto-EOI on slave, but it sometimes works.
* So, if AUTO_EOI_2 is enabled, we use it.
*/
static __inline void
_atpic_eoi_slave(struct intsrc *isrc)
{
KASSERT(isrc->is_pic == &atpics[SLAVE].at_pic,
("%s: mismatched pic", __func__));
#ifndef AUTO_EOI_2
outb(atpics[SLAVE].at_ioaddr, OCW2_EOI);
#ifndef AUTO_EOI_1
outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
#endif
#endif
}
Dynamically allocate IRQ ranges on x86. Previously, x86 used static ranges of IRQ values for different types of I/O interrupts. Interrupt pins on I/O APICs and 8259A PICs used IRQ values from 0 to 254. MSI interrupts used a compile-time-defined range starting at 256, and Xen event channels used a compile-time-defined range after MSI. Some recent systems have more than 255 I/O APIC interrupt pins which resulted in those IRQ values overflowing into the MSI range triggering an assertion failure. Replace statically assigned ranges with dynamic ranges. Do a single pass computing the sizes of the IRQ ranges (PICs, MSI, Xen) to determine the total number of IRQs required. Allocate the interrupt source and interrupt count arrays dynamically once this pass has completed. To minimize runtime complexity these arrays are only sized once during bootup. The PIC range is determined by the PICs present in the system. The MSI and Xen ranges continue to use a fixed size, though this does make it possible to turn the MSI range size into a tunable in the future. As a result, various places are updated to use dynamic limits instead of constants. In addition, the vmstat(8) utility has been taught to understand that some kernels may treat 'intrcnt' and 'intrnames' as pointers rather than arrays when extracting interrupt stats from a crashdump. This is determined by the presence (vs absence) of a global 'nintrcnt' symbol. This change reverts r189404 which worked around a buggy BIOS which enumerated an I/O APIC twice (using the same memory mapped address for both entries but using an IRQ base of 256 for one entry and a valid IRQ base for the second entry). Making the "base" of MSI IRQ values dynamic avoids the panic that r189404 worked around, and there may now be valid I/O APICs with an IRQ base above 256 which this workaround would incorrectly skip. If in the future the issue reported in PR 130483 reoccurs, we will have to add a pass over the I/O APIC entries in the MADT to detect duplicates using the memory mapped address and use some strategy to choose the "correct" one. While here, reserve room in intrcnts for the Hyper-V counters. PR: 229429, 130483 Reviewed by: kib, royger, cem Tested by: royger (Xen), kib (DMAR) Approved by: re (gjb) MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D16861
2018-08-28 21:09:19 +00:00
static void
atpic_register_sources(struct pic *pic)
{
struct atpic *ap = (struct atpic *)pic;
struct atpic_intsrc *ai;
int i;
/*
* If any of the ISA IRQs have an interrupt source already, then
* assume that the I/O APICs are being used and don't register any
* of our interrupt sources. This makes sure we don't accidentally
* use mixed mode. The "accidental" use could otherwise occur on
* machines that route the ACPI SCI interrupt to a different ISA
* IRQ (at least one machine routes it to IRQ 13) thus disabling
* that APIC ISA routing and allowing the ATPIC source for that IRQ
* to leak through. We used to depend on this feature for routing
* IRQ0 via mixed mode, but now we don't use mixed mode at all.
Fix a regression in r338360 when booting an x86 machine without APIC. The atpic_register_sources callback tries to avoid registering interrupt sources that would collide with an I/O APIC. However, the previous implementation was failing to register IRQs 8-15 since the slave PIC saw valid IRQs from the master and assumed an I/O APIC was present. To fix, go back to registering all 8259A interrupt sources in one loop when the master's register_sources method is invoked. PR: 231291 Approved by: re (kib) MFC after: 1 month
2018-09-17 17:18:54 +00:00
*
* To avoid the slave not register sources after the master
* registers its sources, register all IRQs when this function is
* called on the master.
Dynamically allocate IRQ ranges on x86. Previously, x86 used static ranges of IRQ values for different types of I/O interrupts. Interrupt pins on I/O APICs and 8259A PICs used IRQ values from 0 to 254. MSI interrupts used a compile-time-defined range starting at 256, and Xen event channels used a compile-time-defined range after MSI. Some recent systems have more than 255 I/O APIC interrupt pins which resulted in those IRQ values overflowing into the MSI range triggering an assertion failure. Replace statically assigned ranges with dynamic ranges. Do a single pass computing the sizes of the IRQ ranges (PICs, MSI, Xen) to determine the total number of IRQs required. Allocate the interrupt source and interrupt count arrays dynamically once this pass has completed. To minimize runtime complexity these arrays are only sized once during bootup. The PIC range is determined by the PICs present in the system. The MSI and Xen ranges continue to use a fixed size, though this does make it possible to turn the MSI range size into a tunable in the future. As a result, various places are updated to use dynamic limits instead of constants. In addition, the vmstat(8) utility has been taught to understand that some kernels may treat 'intrcnt' and 'intrnames' as pointers rather than arrays when extracting interrupt stats from a crashdump. This is determined by the presence (vs absence) of a global 'nintrcnt' symbol. This change reverts r189404 which worked around a buggy BIOS which enumerated an I/O APIC twice (using the same memory mapped address for both entries but using an IRQ base of 256 for one entry and a valid IRQ base for the second entry). Making the "base" of MSI IRQ values dynamic avoids the panic that r189404 worked around, and there may now be valid I/O APICs with an IRQ base above 256 which this workaround would incorrectly skip. If in the future the issue reported in PR 130483 reoccurs, we will have to add a pass over the I/O APIC entries in the MADT to detect duplicates using the memory mapped address and use some strategy to choose the "correct" one. While here, reserve room in intrcnts for the Hyper-V counters. PR: 229429, 130483 Reviewed by: kib, royger, cem Tested by: royger (Xen), kib (DMAR) Approved by: re (gjb) MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D16861
2018-08-28 21:09:19 +00:00
*/
Fix a regression in r338360 when booting an x86 machine without APIC. The atpic_register_sources callback tries to avoid registering interrupt sources that would collide with an I/O APIC. However, the previous implementation was failing to register IRQs 8-15 since the slave PIC saw valid IRQs from the master and assumed an I/O APIC was present. To fix, go back to registering all 8259A interrupt sources in one loop when the master's register_sources method is invoked. PR: 231291 Approved by: re (kib) MFC after: 1 month
2018-09-17 17:18:54 +00:00
if (ap != &atpics[MASTER])
return;
Dynamically allocate IRQ ranges on x86. Previously, x86 used static ranges of IRQ values for different types of I/O interrupts. Interrupt pins on I/O APICs and 8259A PICs used IRQ values from 0 to 254. MSI interrupts used a compile-time-defined range starting at 256, and Xen event channels used a compile-time-defined range after MSI. Some recent systems have more than 255 I/O APIC interrupt pins which resulted in those IRQ values overflowing into the MSI range triggering an assertion failure. Replace statically assigned ranges with dynamic ranges. Do a single pass computing the sizes of the IRQ ranges (PICs, MSI, Xen) to determine the total number of IRQs required. Allocate the interrupt source and interrupt count arrays dynamically once this pass has completed. To minimize runtime complexity these arrays are only sized once during bootup. The PIC range is determined by the PICs present in the system. The MSI and Xen ranges continue to use a fixed size, though this does make it possible to turn the MSI range size into a tunable in the future. As a result, various places are updated to use dynamic limits instead of constants. In addition, the vmstat(8) utility has been taught to understand that some kernels may treat 'intrcnt' and 'intrnames' as pointers rather than arrays when extracting interrupt stats from a crashdump. This is determined by the presence (vs absence) of a global 'nintrcnt' symbol. This change reverts r189404 which worked around a buggy BIOS which enumerated an I/O APIC twice (using the same memory mapped address for both entries but using an IRQ base of 256 for one entry and a valid IRQ base for the second entry). Making the "base" of MSI IRQ values dynamic avoids the panic that r189404 worked around, and there may now be valid I/O APICs with an IRQ base above 256 which this workaround would incorrectly skip. If in the future the issue reported in PR 130483 reoccurs, we will have to add a pass over the I/O APIC entries in the MADT to detect duplicates using the memory mapped address and use some strategy to choose the "correct" one. While here, reserve room in intrcnts for the Hyper-V counters. PR: 229429, 130483 Reviewed by: kib, royger, cem Tested by: royger (Xen), kib (DMAR) Approved by: re (gjb) MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D16861
2018-08-28 21:09:19 +00:00
for (i = 0; i < NUM_ISA_IRQS; i++)
if (intr_lookup_source(i) != NULL)
return;
/* Loop through all interrupt sources and add them. */
Fix a regression in r338360 when booting an x86 machine without APIC. The atpic_register_sources callback tries to avoid registering interrupt sources that would collide with an I/O APIC. However, the previous implementation was failing to register IRQs 8-15 since the slave PIC saw valid IRQs from the master and assumed an I/O APIC was present. To fix, go back to registering all 8259A interrupt sources in one loop when the master's register_sources method is invoked. PR: 231291 Approved by: re (kib) MFC after: 1 month
2018-09-17 17:18:54 +00:00
for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
if (i == ICU_SLAVEID)
Dynamically allocate IRQ ranges on x86. Previously, x86 used static ranges of IRQ values for different types of I/O interrupts. Interrupt pins on I/O APICs and 8259A PICs used IRQ values from 0 to 254. MSI interrupts used a compile-time-defined range starting at 256, and Xen event channels used a compile-time-defined range after MSI. Some recent systems have more than 255 I/O APIC interrupt pins which resulted in those IRQ values overflowing into the MSI range triggering an assertion failure. Replace statically assigned ranges with dynamic ranges. Do a single pass computing the sizes of the IRQ ranges (PICs, MSI, Xen) to determine the total number of IRQs required. Allocate the interrupt source and interrupt count arrays dynamically once this pass has completed. To minimize runtime complexity these arrays are only sized once during bootup. The PIC range is determined by the PICs present in the system. The MSI and Xen ranges continue to use a fixed size, though this does make it possible to turn the MSI range size into a tunable in the future. As a result, various places are updated to use dynamic limits instead of constants. In addition, the vmstat(8) utility has been taught to understand that some kernels may treat 'intrcnt' and 'intrnames' as pointers rather than arrays when extracting interrupt stats from a crashdump. This is determined by the presence (vs absence) of a global 'nintrcnt' symbol. This change reverts r189404 which worked around a buggy BIOS which enumerated an I/O APIC twice (using the same memory mapped address for both entries but using an IRQ base of 256 for one entry and a valid IRQ base for the second entry). Making the "base" of MSI IRQ values dynamic avoids the panic that r189404 worked around, and there may now be valid I/O APICs with an IRQ base above 256 which this workaround would incorrectly skip. If in the future the issue reported in PR 130483 reoccurs, we will have to add a pass over the I/O APIC entries in the MADT to detect duplicates using the memory mapped address and use some strategy to choose the "correct" one. While here, reserve room in intrcnts for the Hyper-V counters. PR: 229429, 130483 Reviewed by: kib, royger, cem Tested by: royger (Xen), kib (DMAR) Approved by: re (gjb) MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D16861
2018-08-28 21:09:19 +00:00
continue;
intr_register_source(&ai->at_intsrc);
}
}
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
static void
atpic_enable_source(struct intsrc *isrc)
{
struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
struct atpic *ap = (struct atpic *)isrc->is_pic;
Explicitly use spinlock_enter/exit rather than locking the icu_lock spin lock in the 8259A drivers as these drivers are only used on UP systems. This slightly reduces the penalty of an SMP kernel (such as GENERIC) on a UP x86 machine.
2008-03-20 21:53:27 +00:00
spinlock_enter();
Remove 'imen' global variable from atpic(4). In pre-SMPng, the global 'imen' was used to track mask state of the hardware interrupts and was aligned to the masks used by spl*(). When the atpic code was converted to using the x86 interrupt source abstraction, the global 'imen' was preserved by having each PIC instance point to an invididual byte in the global 'imen' to hold its 8-bit interrupt mask. The global 'imen' is no longer used for anything however, so rather than storing pointers in 'struct atpic', just store the individual 8-bit mask for each PIC as a char. While here, convert the ATPIC macro to using C99 initializers. Reviewed by: kib, imp MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D16827
2018-08-21 17:13:51 +00:00
if (ap->at_imen & IMEN_MASK(ai)) {
ap->at_imen &= ~IMEN_MASK(ai);
outb(ap->at_ioaddr + ICU_IMR_OFFSET, ap->at_imen);
- Add an IMEN_MASK macro that returns the 8-bit bitmask of an atpic interrupt source. - Only do an outb() to the PIC to clear a bit in imen if the bit is set. - Add a NUM_ISA_IRQS macro to replace uglier 'sizeof(array) / sizeof(member)' expressions along with a CTASSERT() to ensure that the macro is correct.
2004-05-03 14:52:41 +00:00
}
Explicitly use spinlock_enter/exit rather than locking the icu_lock spin lock in the 8259A drivers as these drivers are only used on UP systems. This slightly reduces the penalty of an SMP kernel (such as GENERIC) on a UP x86 machine.
2008-03-20 21:53:27 +00:00
spinlock_exit();
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
}
static void
Optimize intr_execute_handlers() by combining the pic_disable_source() and pic_eoi_source() into one call. This halves the number of spinlock operations and indirect function calls in the normal case of handling a normal (ithread) interrupt. Optimize the atpic and ioapic drivers to use inlines where appropriate in supporting the intr_execute_handlers() change. This knocks 900ns, or roughly 1350 cycles, off of the time spent servicing an interrupt in the common case on my 1.5GHz P4 uniprocessor system. SMP systems likely won't see as much of a gain due to the ioapic being more efficient than the atpic. I'll investigate porting this to amd64 soon. Reviewed by: jhb
2004-08-02 15:31:10 +00:00
atpic_disable_source(struct intsrc *isrc, int eoi)
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
{
struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
struct atpic *ap = (struct atpic *)isrc->is_pic;
Explicitly use spinlock_enter/exit rather than locking the icu_lock spin lock in the 8259A drivers as these drivers are only used on UP systems. This slightly reduces the penalty of an SMP kernel (such as GENERIC) on a UP x86 machine.
2008-03-20 21:53:27 +00:00
spinlock_enter();
Optimize intr_execute_handlers() by combining the pic_disable_source() and pic_eoi_source() into one call. This halves the number of spinlock operations and indirect function calls in the normal case of handling a normal (ithread) interrupt. Optimize the atpic and ioapic drivers to use inlines where appropriate in supporting the intr_execute_handlers() change. This knocks 900ns, or roughly 1350 cycles, off of the time spent servicing an interrupt in the common case on my 1.5GHz P4 uniprocessor system. SMP systems likely won't see as much of a gain due to the ioapic being more efficient than the atpic. I'll investigate porting this to amd64 soon. Reviewed by: jhb
2004-08-02 15:31:10 +00:00
if (ai->at_trigger != INTR_TRIGGER_EDGE) {
Remove 'imen' global variable from atpic(4). In pre-SMPng, the global 'imen' was used to track mask state of the hardware interrupts and was aligned to the masks used by spl*(). When the atpic code was converted to using the x86 interrupt source abstraction, the global 'imen' was preserved by having each PIC instance point to an invididual byte in the global 'imen' to hold its 8-bit interrupt mask. The global 'imen' is no longer used for anything however, so rather than storing pointers in 'struct atpic', just store the individual 8-bit mask for each PIC as a char. While here, convert the ATPIC macro to using C99 initializers. Reviewed by: kib, imp MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D16827
2018-08-21 17:13:51 +00:00
ap->at_imen |= IMEN_MASK(ai);
outb(ap->at_ioaddr + ICU_IMR_OFFSET, ap->at_imen);
Optimize intr_execute_handlers() by combining the pic_disable_source() and pic_eoi_source() into one call. This halves the number of spinlock operations and indirect function calls in the normal case of handling a normal (ithread) interrupt. Optimize the atpic and ioapic drivers to use inlines where appropriate in supporting the intr_execute_handlers() change. This knocks 900ns, or roughly 1350 cycles, off of the time spent servicing an interrupt in the common case on my 1.5GHz P4 uniprocessor system. SMP systems likely won't see as much of a gain due to the ioapic being more efficient than the atpic. I'll investigate porting this to amd64 soon. Reviewed by: jhb
2004-08-02 15:31:10 +00:00
}
/*
* Take care to call these functions directly instead of through
* a function pointer. All of the referenced variables should
* still be hot in the cache.
*/
if (eoi == PIC_EOI) {
if (isrc->is_pic == &atpics[MASTER].at_pic)
_atpic_eoi_master(isrc);
else
_atpic_eoi_slave(isrc);
}
Explicitly use spinlock_enter/exit rather than locking the icu_lock spin lock in the 8259A drivers as these drivers are only used on UP systems. This slightly reduces the penalty of an SMP kernel (such as GENERIC) on a UP x86 machine.
2008-03-20 21:53:27 +00:00
spinlock_exit();
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
}
static void
atpic_eoi_master(struct intsrc *isrc)
{
#ifndef AUTO_EOI_1
Explicitly use spinlock_enter/exit rather than locking the icu_lock spin lock in the 8259A drivers as these drivers are only used on UP systems. This slightly reduces the penalty of an SMP kernel (such as GENERIC) on a UP x86 machine.
2008-03-20 21:53:27 +00:00
spinlock_enter();
Optimize intr_execute_handlers() by combining the pic_disable_source() and pic_eoi_source() into one call. This halves the number of spinlock operations and indirect function calls in the normal case of handling a normal (ithread) interrupt. Optimize the atpic and ioapic drivers to use inlines where appropriate in supporting the intr_execute_handlers() change. This knocks 900ns, or roughly 1350 cycles, off of the time spent servicing an interrupt in the common case on my 1.5GHz P4 uniprocessor system. SMP systems likely won't see as much of a gain due to the ioapic being more efficient than the atpic. I'll investigate porting this to amd64 soon. Reviewed by: jhb
2004-08-02 15:31:10 +00:00
_atpic_eoi_master(isrc);
Explicitly use spinlock_enter/exit rather than locking the icu_lock spin lock in the 8259A drivers as these drivers are only used on UP systems. This slightly reduces the penalty of an SMP kernel (such as GENERIC) on a UP x86 machine.
2008-03-20 21:53:27 +00:00
spinlock_exit();
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
#endif
}
static void
atpic_eoi_slave(struct intsrc *isrc)
{
#ifndef AUTO_EOI_2
Explicitly use spinlock_enter/exit rather than locking the icu_lock spin lock in the 8259A drivers as these drivers are only used on UP systems. This slightly reduces the penalty of an SMP kernel (such as GENERIC) on a UP x86 machine.
2008-03-20 21:53:27 +00:00
spinlock_enter();
Optimize intr_execute_handlers() by combining the pic_disable_source() and pic_eoi_source() into one call. This halves the number of spinlock operations and indirect function calls in the normal case of handling a normal (ithread) interrupt. Optimize the atpic and ioapic drivers to use inlines where appropriate in supporting the intr_execute_handlers() change. This knocks 900ns, or roughly 1350 cycles, off of the time spent servicing an interrupt in the common case on my 1.5GHz P4 uniprocessor system. SMP systems likely won't see as much of a gain due to the ioapic being more efficient than the atpic. I'll investigate porting this to amd64 soon. Reviewed by: jhb
2004-08-02 15:31:10 +00:00
_atpic_eoi_slave(isrc);
Explicitly use spinlock_enter/exit rather than locking the icu_lock spin lock in the 8259A drivers as these drivers are only used on UP systems. This slightly reduces the penalty of an SMP kernel (such as GENERIC) on a UP x86 machine.
2008-03-20 21:53:27 +00:00
spinlock_exit();
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
#endif
}
static void
atpic_enable_intr(struct intsrc *isrc)
{
}
Minor fixes and tweaks to the x86 interrupt code: - Split the intr_table_lock into an sx lock used for most things, and a spin lock to protect intrcnt_index. Originally I had this as a spin lock so interrupt code could use it to lookup sources. However, we don't actually do that because it would add a lot of overhead to interrupts, and if we ever do support removing interrupt sources, we can use other means to safely do so w/o locking in the interrupt handling code. - Replace is_enabled (boolean) with is_handlers (a count of handlers) to determine if a source is enabled or not. This allows us to notice when a source is no longer in use. When that happens, we now invoke a new PIC method (pic_disable_intr()) to inform the PIC driver that the source is no longer in use. The I/O APIC driver frees the APIC IDT vector when this happens. The MSI driver no longer needs to have a hack to clear is_enabled during msi_alloc() and msix_alloc() as a result of this change as well. - Add an apic_disable_vector() to reset an IDT vector back to Xrsvd to complement apic_enable_vector() and use it in the I/O APIC and MSI code when freeing an IDT vector. - Add a new nexus hook: nexus_add_irq() to ask the nexus driver to add an IRQ to its irq_rman. The MSI code uses this when it creates new interrupt sources to let the nexus know about newly valid IRQs. Previously the msi_alloc() and msix_alloc() passed some extra stuff back to the nexus methods which then added the IRQs. This approach is a bit cleaner. - Change the MSI sx lock to a mutex. If we need to create new sources, drop the lock, create the required number of sources, then get the lock and try the allocation again.
2007-05-08 21:29:14 +00:00
static void
atpic_disable_intr(struct intsrc *isrc)
{
}
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
static int
atpic_vector(struct intsrc *isrc)
{
struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
struct atpic *ap = (struct atpic *)isrc->is_pic;
return (IRQ(ap, ai));
}
static int
atpic_source_pending(struct intsrc *isrc)
{
struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
struct atpic *ap = (struct atpic *)isrc->is_pic;
- Add an IMEN_MASK macro that returns the 8-bit bitmask of an atpic interrupt source. - Only do an outb() to the PIC to clear a bit in imen if the bit is set. - Add a NUM_ISA_IRQS macro to replace uglier 'sizeof(array) / sizeof(member)' expressions along with a CTASSERT() to ensure that the macro is correct.
2004-05-03 14:52:41 +00:00
return (inb(ap->at_ioaddr) & IMEN_MASK(ai));
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
}
static void
Add support for suspend/resume/migration operations when running as a Xen PVHVM guest. Submitted by: Roger Pau Monné Sponsored by: Citrix Systems R&D Reviewed by: gibbs Approved by: re (blanket Xen) MFC after: 2 weeks sys/amd64/amd64/mp_machdep.c: sys/i386/i386/mp_machdep.c: - Make sure that are no MMU related IPIs pending on migration. - Reset pending IPI_BITMAP on resume. - Init vcpu_info on resume. sys/amd64/include/intr_machdep.h: sys/i386/include/intr_machdep.h: sys/x86/acpica/acpi_wakeup.c: sys/x86/x86/intr_machdep.c: sys/x86/isa/atpic.c: sys/x86/x86/io_apic.c: sys/x86/x86/local_apic.c: - Add a "suspend_cancelled" parameter to pic_resume(). For the Xen PIC, restoration of interrupt services differs between the aborted suspend and normal resume cases, so we must provide this information. sys/dev/acpica/acpi_timer.c: sys/dev/xen/timer/timer.c: sys/timetc.h: - Don't swap out "suspend safe" timers across a suspend/resume cycle. This includes the Xen PV and ACPI timers. sys/dev/xen/control/control.c: - Perform proper suspend/resume process for PVHVM: - Suspend all APs before going into suspension, this allows us to reset the vcpu_info on resume for each AP. - Reset shared info page and callback on resume. sys/dev/xen/timer/timer.c: - Implement suspend/resume support for the PV timer. Since FreeBSD doesn't perform a per-cpu resume of the timer, we need to call smp_rendezvous in order to correctly resume the timer on each CPU. sys/dev/xen/xenpci/xenpci.c: - Don't reset the PCI interrupt on each suspend/resume. sys/kern/subr_smp.c: - When suspending a PVHVM domain make sure there are no MMU IPIs in-flight, or we will get a lockup on resume due to the fact that pending event channels are not carried over on migration. - Implement a generic version of restart_cpus that can be used by suspended and stopped cpus. sys/x86/xen/hvm.c: - Implement resume support for the hypercall page and shared info. - Clear vcpu_info so it can be reset by APs when resuming from suspension. sys/dev/xen/xenpci/xenpci.c: sys/x86/xen/hvm.c: sys/x86/xen/xen_intr.c: - Support UP kernel configurations. sys/x86/xen/xen_intr.c: - Properly rebind per-cpus VIRQs and IPIs on resume.
2013-09-20 05:06:03 +00:00
atpic_resume(struct pic *pic, bool suspend_cancelled)
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
{
Change the x86 interrupt code to suspend/resume interrupt controllers (PICs) rather than interrupt sources. This allows interrupt controllers with no interrupt pics (such as the 8259As when APIC is in use) to participate in suspend/resume. - Always register the 8259A PICs even if we don't use any of their pins. - Explicitly reset the 8259As on resume on amd64 if 'device atpic' isn't included. - Add a "dummy" PIC for the local APIC on the BSP to reset the local APIC on resume. This gets suspend/resume working with APIC on UP systems. SMP still needs more work to bring the APs back to life. The MFC after is tentative. Tested by: anholt (i386) Submitted by: Andrea Bittau <a.bittau at cs.ucl.ac.uk> (3) MFC after: 1 week
2006-10-10 23:23:12 +00:00
struct atpic *ap = (struct atpic *)pic;
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
Change the x86 interrupt code to suspend/resume interrupt controllers (PICs) rather than interrupt sources. This allows interrupt controllers with no interrupt pics (such as the 8259As when APIC is in use) to participate in suspend/resume. - Always register the 8259A PICs even if we don't use any of their pins. - Explicitly reset the 8259As on resume on amd64 if 'device atpic' isn't included. - Add a "dummy" PIC for the local APIC on the BSP to reset the local APIC on resume. This gets suspend/resume working with APIC on UP systems. SMP still needs more work to bring the APs back to life. The MFC after is tentative. Tested by: anholt (i386) Submitted by: Andrea Bittau <a.bittau at cs.ucl.ac.uk> (3) MFC after: 1 week
2006-10-10 23:23:12 +00:00
i8259_init(ap, ap == &atpics[SLAVE]);
if (ap == &atpics[SLAVE] && elcr_found)
elcr_resume();
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
}
- Add a new pic method pic_config_intr() to set the trigger mode and polarity for a specified IRQ. The intr_config_intr() function wraps this pic method hiding the IRQ to interrupt source lookup. - Add a config_intr() method to the atpic(4) driver that reconfigures the interrupt using the ELCR if possible and returns an error otherwise. - Add a config_intr() method to the apic(4) driver that just logs any requests that would change the existing programming under bootverbose. Currently, the only changes the apic(4) driver receives are due to bugs in the acpi(4) driver and its handling of link devices, hence the reason for such requests currently being ignored. - Have the nexus(4) driver on i386 implement the bus_config_intr() function by calling intr_config_intr().
2004-05-04 21:02:56 +00:00
static int
atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
enum intr_polarity pol)
{
struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
u_int vector;
/* Map conforming values to edge/hi and sanity check the values. */
if (trig == INTR_TRIGGER_CONFORM)
trig = INTR_TRIGGER_EDGE;
if (pol == INTR_POLARITY_CONFORM)
pol = INTR_POLARITY_HIGH;
vector = atpic_vector(isrc);
if ((trig == INTR_TRIGGER_EDGE && pol == INTR_POLARITY_LOW) ||
(trig == INTR_TRIGGER_LEVEL && pol == INTR_POLARITY_HIGH)) {
printf(
"atpic: Mismatched config for IRQ%u: trigger %s, polarity %s\n",
vector, trig == INTR_TRIGGER_EDGE ? "edge" : "level",
pol == INTR_POLARITY_HIGH ? "high" : "low");
return (EINVAL);
}
/* If there is no change, just return. */
if (ai->at_trigger == trig)
return (0);
/*
* Certain IRQs can never be level/lo, so don't try to set them
* that way if asked. At least some ELCR registers ignore setting
* these bits as well.
*/
if ((vector == 0 || vector == 1 || vector == 2 || vector == 13) &&
trig == INTR_TRIGGER_LEVEL) {
if (bootverbose)
printf(
"atpic: Ignoring invalid level/low configuration for IRQ%u\n",
vector);
return (EINVAL);
}
Tweak the ELCR support slightly. Explicitly probe the ELCR during boot instead of burying that in the atpic(4) code as atpic(4) is not the only user of elcr(4). Change the elcr(4) code to export a global elcr_found variable that other code can check to see if a valid ELCR was found. MFC after: 1 month
2005-01-18 20:24:47 +00:00
if (!elcr_found) {
- Add a new pic method pic_config_intr() to set the trigger mode and polarity for a specified IRQ. The intr_config_intr() function wraps this pic method hiding the IRQ to interrupt source lookup. - Add a config_intr() method to the atpic(4) driver that reconfigures the interrupt using the ELCR if possible and returns an error otherwise. - Add a config_intr() method to the apic(4) driver that just logs any requests that would change the existing programming under bootverbose. Currently, the only changes the apic(4) driver receives are due to bugs in the acpi(4) driver and its handling of link devices, hence the reason for such requests currently being ignored. - Have the nexus(4) driver on i386 implement the bus_config_intr() function by calling intr_config_intr().
2004-05-04 21:02:56 +00:00
if (bootverbose)
printf("atpic: No ELCR to configure IRQ%u as %s\n",
vector, trig == INTR_TRIGGER_EDGE ? "edge/high" :
"level/low");
return (ENXIO);
}
if (bootverbose)
printf("atpic: Programming IRQ%u as %s\n", vector,
trig == INTR_TRIGGER_EDGE ? "edge/high" : "level/low");
Explicitly use spinlock_enter/exit rather than locking the icu_lock spin lock in the 8259A drivers as these drivers are only used on UP systems. This slightly reduces the penalty of an SMP kernel (such as GENERIC) on a UP x86 machine.
2008-03-20 21:53:27 +00:00
spinlock_enter();
- Add a new pic method pic_config_intr() to set the trigger mode and polarity for a specified IRQ. The intr_config_intr() function wraps this pic method hiding the IRQ to interrupt source lookup. - Add a config_intr() method to the atpic(4) driver that reconfigures the interrupt using the ELCR if possible and returns an error otherwise. - Add a config_intr() method to the apic(4) driver that just logs any requests that would change the existing programming under bootverbose. Currently, the only changes the apic(4) driver receives are due to bugs in the acpi(4) driver and its handling of link devices, hence the reason for such requests currently being ignored. - Have the nexus(4) driver on i386 implement the bus_config_intr() function by calling intr_config_intr().
2004-05-04 21:02:56 +00:00
elcr_write_trigger(atpic_vector(isrc), trig);
ai->at_trigger = trig;
Explicitly use spinlock_enter/exit rather than locking the icu_lock spin lock in the 8259A drivers as these drivers are only used on UP systems. This slightly reduces the penalty of an SMP kernel (such as GENERIC) on a UP x86 machine.
2008-03-20 21:53:27 +00:00
spinlock_exit();
- Add a new pic method pic_config_intr() to set the trigger mode and polarity for a specified IRQ. The intr_config_intr() function wraps this pic method hiding the IRQ to interrupt source lookup. - Add a config_intr() method to the atpic(4) driver that reconfigures the interrupt using the ELCR if possible and returns an error otherwise. - Add a config_intr() method to the apic(4) driver that just logs any requests that would change the existing programming under bootverbose. Currently, the only changes the apic(4) driver receives are due to bugs in the acpi(4) driver and its handling of link devices, hence the reason for such requests currently being ignored. - Have the nexus(4) driver on i386 implement the bus_config_intr() function by calling intr_config_intr().
2004-05-04 21:02:56 +00:00
return (0);
}
Improve the handling of cpuset with interrupts. - For x86, change the interrupt source method to assign an interrupt source to a specific CPU to return an error value instead of void, thus allowing it to fail. - If moving an interrupt to a CPU fails due to a lack of IDT vectors in the destination CPU, fail the request with ENOSPC rather than panicing. - For MSI interrupts on x86 (but not MSI-X), only allow cpuset to be used on the first interrupt in a group. Moving the first interrupt in a group moves the entire group. - Use the icu_lock to protect intr_next_cpu() on x86 instead of the intr_table_lock to fix a LOR introduced in the last set of MSI changes. - Add a new privilege PRIV_SCHED_CPUSET_INTR for using cpuset with interrupts. Previously, binding an interrupt to a CPU only performed a privilege check if the interrupt had an interrupt thread. Interrupts without a thread could be bound by non-root users as a result. - If an interrupt event's assign_cpu method fails, then restore the original cpuset mask for the associated interrupt thread. Approved by: re (kib)
2009-07-01 17:20:07 +00:00
static int
Rework how we wire up interrupt sources to CPUs: - Throw out all of the logical APIC ID stuff. The Intel docs are somewhat ambiguous, but it seems that the "flat" cluster model we are currently using is only supported on Pentium and P6 family CPUs. The other "hierarchy" cluster model that is supported on all Intel CPUs with local APICs is severely underdocumented. For example, it's not clear if the OS needs to glean the topology of the APIC hierarchy from somewhere (neither ACPI nor MP Table include it) and setup the logical clusters based on the physical hierarchy or not. Not only that, but on certain Intel chipsets, even though there were 4 CPUs in a logical cluster, all the interrupts were only sent to one CPU anyway. - We now bind interrupts to individual CPUs using physical addressing via the local APIC IDs. This code has also moved out of the ioapic PIC driver and into the common interrupt source code so that it can be shared with MSI interrupt sources since MSI is addressed to APICs the same way that I/O APIC pins are. - Interrupt source classes grow a new method pic_assign_cpu() to bind an interrupt source to a specific local APIC ID. - The SMP code now tells the interrupt code which CPUs are avaiable to handle interrupts in a simpler and more intuitive manner. For one thing, it means we could now choose to not route interrupts to HT cores if we wanted to (this code is currently in place in fact, but under an #if 0 for now). - For now we simply do static round-robin of IRQs to CPUs when the first interrupt handler just as before, with the change that IRQs are now bound to individual CPUs rather than groups of up to 4 CPUs. - Because the IRQ to CPU mapping has now been moved up a layer, it would be easier to manage this mapping from higher levels. For example, we could allow drivers to specify a CPU affinity map for their interrupts, or we could allow a userland tool to bind IRQs to specific CPUs. The MFC is tentative, but I want to see if this fixes problems some folks had with UP APIC kernels on 6.0 on SMP machines (an SMP kernel would work fine, but a UP APIC kernel (such as GENERIC in RELENG_6) would lose interrupts). MFC after: 1 week
2006-02-28 22:24:55 +00:00
atpic_assign_cpu(struct intsrc *isrc, u_int apic_id)
{
/*
* 8259A's are only used in UP in which case all interrupts always
* go to the sole CPU and this function shouldn't even be called.
*/
panic("%s: bad cookie", __func__);
}
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
static void
i8259_init(struct atpic *pic, int slave)
{
int imr_addr;
/* Reset the PIC and program with next four bytes. */
Explicitly use spinlock_enter/exit rather than locking the icu_lock spin lock in the 8259A drivers as these drivers are only used on UP systems. This slightly reduces the penalty of an SMP kernel (such as GENERIC) on a UP x86 machine.
2008-03-20 21:53:27 +00:00
spinlock_enter();
Remove Micro Channel Architecture support. Of the commonly available machines, only a few 486 machines that used it, and those haven't had enough memory to run FreeBSD for quite some time (often limited to 16MB). Not to be confused with the Machine Check Architecture, which is still very much alive and used (and untouched by this commit). No Objection From: arch@
2017-02-15 23:04:25 +00:00
outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4);
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
imr_addr = pic->at_ioaddr + ICU_IMR_OFFSET;
/* Start vector. */
outb(imr_addr, pic->at_intbase);
/*
* Setup slave links. For the master pic, indicate what line
* the slave is configured on. For the slave indicate
* which line on the master we are connected to.
*/
if (slave)
- Move some macros from icu.h into atpic.c as that is the only place they are used. - Reduce duplication of a couple of macros removing the duplicates from ich.h. - Remove unused macros from icu.h as well as locore protection as this header is no longer included in assembly sources.
2004-05-11 20:23:24 +00:00
outb(imr_addr, ICU_SLAVEID);
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
else
- Move some macros from icu.h into atpic.c as that is the only place they are used. - Reduce duplication of a couple of macros removing the duplicates from ich.h. - Remove unused macros from icu.h as well as locore protection as this header is no longer included in assembly sources.
2004-05-11 20:23:24 +00:00
outb(imr_addr, IRQ_MASK(ICU_SLAVEID));
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
/* Set mode. */
if (slave)
outb(imr_addr, SLAVE_MODE);
else
outb(imr_addr, MASTER_MODE);
/* Set interrupt enable mask. */
Remove 'imen' global variable from atpic(4). In pre-SMPng, the global 'imen' was used to track mask state of the hardware interrupts and was aligned to the masks used by spl*(). When the atpic code was converted to using the x86 interrupt source abstraction, the global 'imen' was preserved by having each PIC instance point to an invididual byte in the global 'imen' to hold its 8-bit interrupt mask. The global 'imen' is no longer used for anything however, so rather than storing pointers in 'struct atpic', just store the individual 8-bit mask for each PIC as a char. While here, convert the ATPIC macro to using C99 initializers. Reviewed by: kib, imp MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D16827
2018-08-21 17:13:51 +00:00
outb(imr_addr, pic->at_imen);
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
/* Reset is finished, default to IRR on read. */
Replace magic numbers with macros for i8259A register constants. Still need the ICW4 bits for PC98 though.
2003-11-14 19:13:06 +00:00
outb(pic->at_ioaddr, OCW3_SEL | OCW3_RR);
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
Replace magic numbers with macros for i8259A register constants. Still need the ICW4 bits for PC98 though.
2003-11-14 19:13:06 +00:00
/* OCW2_L1 sets priority order to 3-7, 0-2 (com2 first). */
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
if (!slave)
Replace magic numbers with macros for i8259A register constants. Still need the ICW4 bits for PC98 though.
2003-11-14 19:13:06 +00:00
outb(pic->at_ioaddr, OCW2_R | OCW2_SL | OCW2_L1);
Remove pc98 support completely. I thank all developers and contributors for pc98. Relnotes: yes
2017-01-28 02:22:15 +00:00
Explicitly use spinlock_enter/exit rather than locking the icu_lock spin lock in the 8259A drivers as these drivers are only used on UP systems. This slightly reduces the penalty of an SMP kernel (such as GENERIC) on a UP x86 machine.
2008-03-20 21:53:27 +00:00
spinlock_exit();
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
}
void
atpic_startup(void)
{
- Add counts to the ATPIC interrupt sources and point the ATPIC interrupt source count pointers at them so that intr_execute_handlers() won't choke when it tries to handle an unregisterd ATPIC interrupt source. - Install the low-level ATPIC interrupt handlers when we first program the ATPIC in atpic_startup() rather than at SI_SUB_INTR. This is only necessary to work around buggy code that enables interrupts too early in the boot process (namely, the vm86 code). Approved by: re (rwatson)
2003-11-19 15:38:56 +00:00
struct atpic_intsrc *ai;
int i;
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
/* Start off with all interrupts disabled. */
i8259_init(&atpics[MASTER], 0);
i8259_init(&atpics[SLAVE], 1);
atpic_enable_source((struct intsrc *)&atintrs[ICU_SLAVEID]);
- Add counts to the ATPIC interrupt sources and point the ATPIC interrupt source count pointers at them so that intr_execute_handlers() won't choke when it tries to handle an unregisterd ATPIC interrupt source. - Install the low-level ATPIC interrupt handlers when we first program the ATPIC in atpic_startup() rather than at SI_SUB_INTR. This is only necessary to work around buggy code that enables interrupts too early in the boot process (namely, the vm86 code). Approved by: re (rwatson)
2003-11-19 15:38:56 +00:00
/* Install low-level interrupt handlers for all of our IRQs. */
- Add an IMEN_MASK macro that returns the 8-bit bitmask of an atpic interrupt source. - Only do an outb() to the PIC to clear a bit in imen if the bit is set. - Add a NUM_ISA_IRQS macro to replace uglier 'sizeof(array) / sizeof(member)' expressions along with a CTASSERT() to ensure that the macro is correct.
2004-05-03 14:52:41 +00:00
for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
- Add counts to the ATPIC interrupt sources and point the ATPIC interrupt source count pointers at them so that intr_execute_handlers() won't choke when it tries to handle an unregisterd ATPIC interrupt source. - Install the low-level ATPIC interrupt handlers when we first program the ATPIC in atpic_startup() rather than at SI_SUB_INTR. This is only necessary to work around buggy code that enables interrupts too early in the boot process (namely, the vm86 code). Approved by: re (rwatson)
2003-11-19 15:38:56 +00:00
if (i == ICU_SLAVEID)
continue;
ai->at_intsrc.is_count = &ai->at_count;
ai->at_intsrc.is_straycount = &ai->at_straycount;
setidt(((struct atpic *)ai->at_intsrc.is_pic)->at_intbase +
PTI for amd64. The implementation of the Kernel Page Table Isolation (KPTI) for amd64, first version. It provides a workaround for the 'meltdown' vulnerability. PTI is turned off by default for now, enable with the loader tunable vm.pmap.pti=1. The pmap page table is split into kernel-mode table and user-mode table. Kernel-mode table is identical to the non-PTI table, while usermode table is obtained from kernel table by leaving userspace mappings intact, but only leaving the following parts of the kernel mapped: kernel text (but not modules text) PCPU GDT/IDT/user LDT/task structures IST stacks for NMI and doublefault handlers. Kernel switches to user page table before returning to usermode, and restores full kernel page table on the entry. Initial kernel-mode stack for PTI trampoline is allocated in PCPU, it is only 16 qwords. Kernel entry trampoline switches page tables. then the hardware trap frame is copied to the normal kstack, and execution continues. IST stacks are kept mapped and no trampoline is needed for NMI/doublefault, but of course page table switch is performed. On return to usermode, the trampoline is used again, iret frame is copied to the trampoline stack, page tables are switched and iretq is executed. The case of iretq faulting due to the invalid usermode context is tricky, since the frame for fault is appended to the trampoline frame. Besides copying the fault frame and original (corrupted) frame to kstack, the fault frame must be patched to make it look as if the fault occured on the kstack, see the comment in doret_iret detection code in trap(). Currently kernel pages which are mapped during trampoline operation are identical for all pmaps. They are registered using pmap_pti_add_kva(). Besides initial registrations done during boot, LDT and non-common TSS segments are registered if user requested their use. In principle, they can be installed into kernel page table per pmap with some work. Similarly, PCPU can be hidden from userspace mapping using trampoline PCPU page, but again I do not see much benefits besides complexity. PDPE pages for the kernel half of the user page tables are pre-allocated during boot because we need to know pml4 entries which are copied to the top-level paging structure page, in advance on a new pmap creation. I enforce this to avoid iterating over the all existing pmaps if a new PDPE page is needed for PTI kernel mappings. The iteration is a known problematic operation on i386. The need to flush hidden kernel translations on the switch to user mode make global tables (PG_G) meaningless and even harming, so PG_G use is disabled for PTI case. Our existing use of PCID is incompatible with PTI and is automatically disabled if PTI is enabled. PCID can be forced on only for developer's benefit. MCE is known to be broken, it requires IST stack to operate completely correctly even for non-PTI case, and absolutely needs dedicated IST stack because MCE delivery while trampoline did not switched from PTI stack is fatal. The fix is pending. Reviewed by: markj (partially) Tested by: pho (previous version) Discussed with: jeff, jhb Sponsored by: The FreeBSD Foundation MFC after: 2 weeks
2018-01-17 11:44:21 +00:00
ai->at_irq, pti ? ai->at_intr_pti : ai->at_intr, SDT_ATPIC,
SEL_KPL, GSEL_ATPIC);
- Add counts to the ATPIC interrupt sources and point the ATPIC interrupt source count pointers at them so that intr_execute_handlers() won't choke when it tries to handle an unregisterd ATPIC interrupt source. - Install the low-level ATPIC interrupt handlers when we first program the ATPIC in atpic_startup() rather than at SI_SUB_INTR. This is only necessary to work around buggy code that enables interrupts too early in the boot process (namely, the vm86 code). Approved by: re (rwatson)
2003-11-19 15:38:56 +00:00
}
- Add a member to the atpic interrupt source structures to indicate if the IRQ is edge triggered or level triggered. For ISA interrupts, we assume that edge triggered interrupts are always active high and that level triggered interrupts are always active low. - Don't disable an edge triggered interrupt in the PIC. This avoids outb instructions to the actual PIC for traditional ISA IRQs such as IRQ 1, 6, 14, and 15. (Fast interrupts such as IRQs 0 and 8 don't mask their source, so this doesn't change anything for them.) - For MCA systems we assume that all interrupts are level triggered and thus need masking. Otherwise, we probe the ELCR. If it exists we trust what it tells us regarding which interrupts are level triggered. If it does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered and that all other IRQs are level triggered and need masking. - Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
/*
* Look for an ELCR. If we find one, update the trigger modes.
* If we don't find one, assume that IRQs 0, 1, 2, and 13 are
* edge triggered and that everything else is level triggered.
* We only use the trigger information to reprogram the ELCR if
* we have one and as an optimization to avoid masking edge
* triggered interrupts. For the case that we don't have an ELCR,
* it doesn't hurt to mask an edge triggered interrupt, so we
- Simplify the sizeof expression in the CTASSERT() for NUM_ISA_IRQS. - Fixup grammar in a comment. Submitted by: bde (1)
2004-05-10 18:33:52 +00:00
* assume level trigger for any interrupt that we aren't sure is
* edge triggered.
- Add a member to the atpic interrupt source structures to indicate if the IRQ is edge triggered or level triggered. For ISA interrupts, we assume that edge triggered interrupts are always active high and that level triggered interrupts are always active low. - Don't disable an edge triggered interrupt in the PIC. This avoids outb instructions to the actual PIC for traditional ISA IRQs such as IRQ 1, 6, 14, and 15. (Fast interrupts such as IRQs 0 and 8 don't mask their source, so this doesn't change anything for them.) - For MCA systems we assume that all interrupts are level triggered and thus need masking. Otherwise, we probe the ELCR. If it exists we trust what it tells us regarding which interrupts are level triggered. If it does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered and that all other IRQs are level triggered and need masking. - Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
*/
Tweak the ELCR support slightly. Explicitly probe the ELCR during boot instead of burying that in the atpic(4) code as atpic(4) is not the only user of elcr(4). Change the elcr(4) code to export a global elcr_found variable that other code can check to see if a valid ELCR was found. MFC after: 1 month
2005-01-18 20:24:47 +00:00
if (elcr_found) {
- Add a member to the atpic interrupt source structures to indicate if the IRQ is edge triggered or level triggered. For ISA interrupts, we assume that edge triggered interrupts are always active high and that level triggered interrupts are always active low. - Don't disable an edge triggered interrupt in the PIC. This avoids outb instructions to the actual PIC for traditional ISA IRQs such as IRQ 1, 6, 14, and 15. (Fast interrupts such as IRQs 0 and 8 don't mask their source, so this doesn't change anything for them.) - For MCA systems we assume that all interrupts are level triggered and thus need masking. Otherwise, we probe the ELCR. If it exists we trust what it tells us regarding which interrupts are level triggered. If it does not exist, we assume that IRQs 0, 1, 2, and 8 are edge triggered and that all other IRQs are level triggered and need masking. - Instruct the ELCR mini-driver to restore its saved state during resume.
2004-05-04 20:12:52 +00:00
for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
ai->at_trigger = elcr_read_trigger(i);
} else {
for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
switch (i) {
case 0:
case 1:
case 2:
case 8:
case 13:
ai->at_trigger = INTR_TRIGGER_EDGE;
break;
default:
ai->at_trigger = INTR_TRIGGER_LEVEL;
break;
}
}
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
}
static void
atpic_init(void *dummy __unused)
{
Change the x86 interrupt code to suspend/resume interrupt controllers (PICs) rather than interrupt sources. This allows interrupt controllers with no interrupt pics (such as the 8259As when APIC is in use) to participate in suspend/resume. - Always register the 8259A PICs even if we don't use any of their pins. - Explicitly reset the 8259As on resume on amd64 if 'device atpic' isn't included. - Add a "dummy" PIC for the local APIC on the BSP to reset the local APIC on resume. This gets suspend/resume working with APIC on UP systems. SMP still needs more work to bring the APs back to life. The MFC after is tentative. Tested by: anholt (i386) Submitted by: Andrea Bittau <a.bittau at cs.ucl.ac.uk> (3) MFC after: 1 week
2006-10-10 23:23:12 +00:00
/*
* Register our PICs, even if we aren't going to use any of their
* pins so that they are suspended and resumed.
*/
if (intr_register_pic(&atpics[0].at_pic) != 0 ||
intr_register_pic(&atpics[1].at_pic) != 0)
panic("Unable to register ATPICs");
Dynamically allocate IRQ ranges on x86. Previously, x86 used static ranges of IRQ values for different types of I/O interrupts. Interrupt pins on I/O APICs and 8259A PICs used IRQ values from 0 to 254. MSI interrupts used a compile-time-defined range starting at 256, and Xen event channels used a compile-time-defined range after MSI. Some recent systems have more than 255 I/O APIC interrupt pins which resulted in those IRQ values overflowing into the MSI range triggering an assertion failure. Replace statically assigned ranges with dynamic ranges. Do a single pass computing the sizes of the IRQ ranges (PICs, MSI, Xen) to determine the total number of IRQs required. Allocate the interrupt source and interrupt count arrays dynamically once this pass has completed. To minimize runtime complexity these arrays are only sized once during bootup. The PIC range is determined by the PICs present in the system. The MSI and Xen ranges continue to use a fixed size, though this does make it possible to turn the MSI range size into a tunable in the future. As a result, various places are updated to use dynamic limits instead of constants. In addition, the vmstat(8) utility has been taught to understand that some kernels may treat 'intrcnt' and 'intrnames' as pointers rather than arrays when extracting interrupt stats from a crashdump. This is determined by the presence (vs absence) of a global 'nintrcnt' symbol. This change reverts r189404 which worked around a buggy BIOS which enumerated an I/O APIC twice (using the same memory mapped address for both entries but using an IRQ base of 256 for one entry and a valid IRQ base for the second entry). Making the "base" of MSI IRQ values dynamic avoids the panic that r189404 worked around, and there may now be valid I/O APICs with an IRQ base above 256 which this workaround would incorrectly skip. If in the future the issue reported in PR 130483 reoccurs, we will have to add a pass over the I/O APIC entries in the MADT to detect duplicates using the memory mapped address and use some strategy to choose the "correct" one. While here, reserve room in intrcnts for the Hyper-V counters. PR: 229429, 130483 Reviewed by: kib, royger, cem Tested by: royger (Xen), kib (DMAR) Approved by: re (gjb) MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D16861
2018-08-28 21:09:19 +00:00
if (num_io_irqs == 0)
num_io_irqs = NUM_ISA_IRQS;
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
}
atpic: make sure atpic_init is called after IO APIC initialization After r269510 the IO APIC and ATPIC initialization is done at the same order, which means atpic_init can be called before the IO APIC has been initalized. In that case the ATPIC will take over the interrupt sources, preventing the IO APIC from registering them. Reported by: David Wolfskill <david@catwhisker.org> Tested by: David Wolfskill <david@catwhisker.org>, Trond Endrestøl <Trond.Endrestol@fagskolen.gjovik.no> Sponsored by: Citrix Systems R&D
2014-08-07 17:00:50 +00:00
SYSINIT(atpic_init, SI_SUB_INTR, SI_ORDER_FOURTH, atpic_init, NULL);
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
void
Evidently FreeBSD has long relied on the compiler to treat structures passed by value (trap frames) as if they were in fact being passed by reference. For better or worse, this incorrect behaviour is no longer present in gcc 4.1. In this patch I convert all trapframe arguments to be explicitly pass by reference. I also remove vm86_initflags, pushing the very little work that it actually does up into vm86_prepcall. Reviewed by: kan Tested by: kan
2006-12-17 05:07:01 +00:00
atpic_handle_intr(u_int vector, struct trapframe *frame)
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
{
struct intsrc *isrc;
Whitespace: reduce diffs with amd64.
2005-12-08 18:33:48 +00:00
KASSERT(vector < NUM_ISA_IRQS, ("unknown int %u\n", vector));
Change the i386 code to pass the interrupt vector as a separate argument rather than embedding it in the intrframe as if_vec. This reduces diffs with amd64 somewhat. - Remove cf_vec from clockframe (it wasn't used anyway) and stop pushing dummy vector arguments for ipi_bitmap_handler() and lapic_handle_timer() since clockframe == trapframe now. - Fix ddb to handle stack traces across interrupt entry points that just have a trapframe on their stack and not a trapframe + vector. - Change intr_execute_handlers() to take a trapframe rather than an intrframe pointer. - Change lapic_handle_intr() and atpic_handle_intr() to take a vector and trapframe rather than an intrframe. - GC struct intrframe now that nothing uses it anymore. - GC CLOCK_TO_TRAPFRAME() and INTR_TO_TRAPFRAME(). Reviewed by: bde Requested by: peter
2005-12-05 22:39:09 +00:00
isrc = &atintrs[vector].at_intsrc;
Add a special check for a stray IRQ 7 or IRQ 15 to see if it is actually a spurious interrupt from one of the 8259As. If so, don't log it as a stray IRQ, but just silently ignore it. Approved by: re (rwatson)
2003-11-19 15:40:23 +00:00
/*
Reorganize the interrupt handling code a bit to make a few things cleaner and increase flexibility to allow various different approaches to be tried in the future. - Split struct ithd up into two pieces. struct intr_event holds the list of interrupt handlers associated with interrupt sources. struct intr_thread contains the data relative to an interrupt thread. Currently we still provide a 1:1 relationship of events to threads with the exception that events only have an associated thread if there is at least one threaded interrupt handler attached to the event. This means that on x86 we no longer have 4 bazillion interrupt threads with no handlers. It also means that interrupt events with only INTR_FAST handlers no longer have an associated thread either. - Renamed struct intrhand to struct intr_handler to follow the struct intr_foo naming convention. This did require renaming the powerpc MD struct intr_handler to struct ppc_intr_handler. - INTR_FAST no longer implies INTR_EXCL on all architectures except for powerpc. This means that multiple INTR_FAST handlers can attach to the same interrupt and that INTR_FAST and non-INTR_FAST handlers can attach to the same interrupt. Sharing INTR_FAST handlers may not always be desirable, but having sio(4) and uhci(4) fight over an IRQ isn't fun either. Drivers can always still use INTR_EXCL to ask for an interrupt exclusively. The way this sharing works is that when an interrupt comes in, all the INTR_FAST handlers are executed first, and if any threaded handlers exist, the interrupt thread is scheduled afterwards. This type of layout also makes it possible to investigate using interrupt filters ala OS X where the filter determines whether or not its companion threaded handler should run. - Aside from the INTR_FAST changes above, the impact on MD interrupt code is mostly just 's/ithread/intr_event/'. - A new MI ddb command 'show intrs' walks the list of interrupt events dumping their state. It also has a '/v' verbose switch which dumps info about all of the handlers attached to each event. - We currently don't destroy an interrupt thread when the last threaded handler is removed because it would suck for things like ppbus(8)'s braindead behavior. The code is present, though, it is just under #if 0 for now. - Move the code to actually execute the threaded handlers for an interrrupt event into a separate function so that ithread_loop() becomes more readable. Previously this code was all in the middle of ithread_loop() and indented halfway across the screen. - Made struct intr_thread private to kern_intr.c and replaced td_ithd with a thread private flag TDP_ITHREAD. - In statclock, check curthread against idlethread directly rather than curthread's proc against idlethread's proc. (Not really related to intr changes) Tested on: alpha, amd64, i386, sparc64 Tested on: arm, ia64 (older version of patch by cognet and marcel)
2005-10-25 19:48:48 +00:00
* If we don't have an event, see if this is a spurious
Add a special check for a stray IRQ 7 or IRQ 15 to see if it is actually a spurious interrupt from one of the 8259As. If so, don't log it as a stray IRQ, but just silently ignore it. Approved by: re (rwatson)
2003-11-19 15:40:23 +00:00
* interrupt.
*/
Change the i386 code to pass the interrupt vector as a separate argument rather than embedding it in the intrframe as if_vec. This reduces diffs with amd64 somewhat. - Remove cf_vec from clockframe (it wasn't used anyway) and stop pushing dummy vector arguments for ipi_bitmap_handler() and lapic_handle_timer() since clockframe == trapframe now. - Fix ddb to handle stack traces across interrupt entry points that just have a trapframe on their stack and not a trapframe + vector. - Change intr_execute_handlers() to take a trapframe rather than an intrframe pointer. - Change lapic_handle_intr() and atpic_handle_intr() to take a vector and trapframe rather than an intrframe. - GC struct intrframe now that nothing uses it anymore. - GC CLOCK_TO_TRAPFRAME() and INTR_TO_TRAPFRAME(). Reviewed by: bde Requested by: peter
2005-12-05 22:39:09 +00:00
if (isrc->is_event == NULL && (vector == 7 || vector == 15)) {
Add a special check for a stray IRQ 7 or IRQ 15 to see if it is actually a spurious interrupt from one of the 8259As. If so, don't log it as a stray IRQ, but just silently ignore it. Approved by: re (rwatson)
2003-11-19 15:40:23 +00:00
int port, isr;
/*
* Read the ISR register to see if IRQ 7/15 is really
* pending. Reset read register back to IRR when done.
*/
port = ((struct atpic *)isrc->is_pic)->at_ioaddr;
Explicitly use spinlock_enter/exit rather than locking the icu_lock spin lock in the 8259A drivers as these drivers are only used on UP systems. This slightly reduces the penalty of an SMP kernel (such as GENERIC) on a UP x86 machine.
2008-03-20 21:53:27 +00:00
spinlock_enter();
Add a special check for a stray IRQ 7 or IRQ 15 to see if it is actually a spurious interrupt from one of the 8259As. If so, don't log it as a stray IRQ, but just silently ignore it. Approved by: re (rwatson)
2003-11-19 15:40:23 +00:00
outb(port, OCW3_SEL | OCW3_RR | OCW3_RIS);
isr = inb(port);
outb(port, OCW3_SEL | OCW3_RR);
Explicitly use spinlock_enter/exit rather than locking the icu_lock spin lock in the 8259A drivers as these drivers are only used on UP systems. This slightly reduces the penalty of an SMP kernel (such as GENERIC) on a UP x86 machine.
2008-03-20 21:53:27 +00:00
spinlock_exit();
- Move some macros from icu.h into atpic.c as that is the only place they are used. - Reduce duplication of a couple of macros removing the duplicates from ich.h. - Remove unused macros from icu.h as well as locore protection as this header is no longer included in assembly sources.
2004-05-11 20:23:24 +00:00
if ((isr & IRQ_MASK(7)) == 0)
Add a special check for a stray IRQ 7 or IRQ 15 to see if it is actually a spurious interrupt from one of the 8259As. If so, don't log it as a stray IRQ, but just silently ignore it. Approved by: re (rwatson)
2003-11-19 15:40:23 +00:00
return;
}
Evidently FreeBSD has long relied on the compiler to treat structures passed by value (trap frames) as if they were in fact being passed by reference. For better or worse, this incorrect behaviour is no longer present in gcc 4.1. In this patch I convert all trapframe arguments to be explicitly pass by reference. I also remove vm86_initflags, pushing the very little work that it actually does up into vm86_prepcall. Reviewed by: kan Tested by: kan
2006-12-17 05:07:01 +00:00
intr_execute_handlers(isrc, frame);
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
}
#ifdef DEV_ISA
/*
* Bus attachment for the ISA PIC.
*/
static struct isa_pnp_id atpic_ids[] = {
{ 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
{ 0 }
};
static int
atpic_probe(device_t dev)
{
int result;
x86: clean up empty lines in .c and .h files
2020-09-01 21:23:59 +00:00
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids);
if (result <= 0)
device_quiet(dev);
return (result);
}
/*
* We might be granted IRQ 2, as this is typically consumed by chaining
* between the two PIC components. If we're using the APIC, however,
* this may not be the case, and as such we should free the resource.
* (XXX untested)
*
* The generic ISA attachment code will handle allocating any other resources
* that we don't explicitly claim here.
*/
static int
atpic_attach(device_t dev)
{
struct resource *res;
int rid;
/* Try to allocate our IRQ and then free it. */
rid = 0;
Convert callers to the new bus_alloc_resource_any(9) API. Submitted by: Mark Santcroos <marks@ripe.net> Reviewed by: imp, dfr, bde
2004-03-17 17:50:55 +00:00
res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 0);
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
if (res != NULL)
bus_release_resource(dev, SYS_RES_IRQ, rid, res);
return (0);
}
Add ISA PNP tables to ISA drivers. Fix a few incidental comments. ACPI ISA PBP tables not tagged, there's bigger issues with them.
2018-01-29 00:22:30 +00:00
/*
* Return a bitmap of the current interrupt requests. This is 8259-specific
* and is only suitable for use at probe time.
*/
intrmask_t
isa_irq_pending(void)
{
u_char irr1;
u_char irr2;
irr1 = inb(IO_ICU1);
irr2 = inb(IO_ICU2);
return ((irr2 << 8) | irr1);
}
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
static device_method_t atpic_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, atpic_probe),
DEVMETHOD(device_attach, atpic_attach),
DEVMETHOD(device_detach, bus_generic_detach),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
DEVMETHOD(device_suspend, bus_generic_suspend),
DEVMETHOD(device_resume, bus_generic_resume),
{ 0, 0 }
};
static driver_t atpic_driver = {
"atpic",
atpic_methods,
1, /* no softc */
};
static devclass_t atpic_devclass;
DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0);
DRIVER_MODULE(atpic, acpi, atpic_driver, atpic_devclass, 0, 0);
Add ISA PNP tables to ISA drivers. Fix a few incidental comments. ACPI ISA PBP tables not tagged, there's bigger issues with them.
2018-01-29 00:22:30 +00:00
ISA_PNP_INFO(atpic_ids);
Add the new atpic(4) driver for the 8259A master and slave PICs. By default we provide 16 interrupt sources for IRQs 0 through 15. However, if the I/O APIC driver has already registered sources for any of those IRQs then we will silently fail to register our own source for that IRQ. Note that i386/isa/icu.h is now specific to the 8259A and no longer contains any info relevant to APICs. Also note that fast interrupts no longer use a separate entry point. Instead, both fast and threaded interrupts share the same entry point which merely looks up the appropriate source and passes control to intr_execute_handlers().
2003-11-03 21:34:45 +00:00
#endif /* DEV_ISA */
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