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freebsd-dev/contrib/gcc/ChangeLog.gcc43

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GCC: bring back experimental support for amdfam10/barcelona CPUs. Initial support for the AMD amdfam10 chipsets has been available in the gcc43 branch under GPLv2. AMD and some linux distributions (OpenSUSE) did a backport of the amdfam10 support and made it available. This is a revised subset of the support initially brought in in r236962 and later reverted. The collateral efects seem to have disappeared but it is still recommended to set the CPUTYPE with caution. Reviewed by: jkim (ages ago) MFC after: 3 weeks
2013-06-01 01:02:24 +00:00
2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124341)
* doc/invoke.texi: Fix typo, 'AMD Family 10h core' instead of
'AMD Family 10 core'.
Add ChangeLog.gcc43 for backported changes from gcc 4.3 MFC after: 3 days
2011-04-30 23:00:41 +00:00
2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124339)
* config/i386/i386.c (override_options): Accept k8-sse3, opteron-sse3
and athlon64-sse3 as improved versions of k8, opteron and athlon64
with SSE3 instruction set support.
* doc/invoke.texi: Likewise.
GCC: bring back experimental support for amdfam10/barcelona CPUs. Initial support for the AMD amdfam10 chipsets has been available in the gcc43 branch under GPLv2. AMD and some linux distributions (OpenSUSE) did a backport of the amdfam10 support and made it available. This is a revised subset of the support initially brought in in r236962 and later reverted. The collateral efects seem to have disappeared but it is still recommended to set the CPUTYPE with caution. Reviewed by: jkim (ages ago) MFC after: 3 weeks
2013-06-01 01:02:24 +00:00
2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124330)
* config/i386/i386.c (override_options): Tuning 32-byte loop
alignment for amdfam10 architecture. Increasing the max loop
alignment to 24 bytes.
Bring a couple of fixes for gcc optimizations. The GCC4.3 branch contains some optimization fixes that were not considered regressions and therefore were never backported. We are bringing a couple of them that are under GPLv2 since they were made before the license switch upstream. While here, add the GCC revision numbers in the log. Discussed with: jkim MFC after: 1 week
2012-06-21 16:49:20 +00:00
2007-04-12 Richard Guenther <rguenther@suse.de> (r123736)
PR tree-optimization/24689
PR tree-optimization/31307
* fold-const.c (operand_equal_p): Compare INTEGER_CST array
indices by value.
* gimplify.c (canonicalize_addr_expr): To be consistent with
gimplify_compound_lval only set operands two and three of
ARRAY_REFs if they are not gimple_min_invariant. This makes
it never at this place.
* tree-ssa-ccp.c (maybe_fold_offset_to_array_ref): Likewise.
Add ChangeLog.gcc43 for backported changes from gcc 4.3 MFC after: 3 days
2011-04-30 23:00:41 +00:00
2007-04-07 H.J. Lu <hongjiu.lu@intel.com> (r123639)
* config/i386/i386.c (ix86_handle_option): Handle SSSE3.
GCC: bring back experimental support for amdfam10/barcelona CPUs. Initial support for the AMD amdfam10 chipsets has been available in the gcc43 branch under GPLv2. AMD and some linux distributions (OpenSUSE) did a backport of the amdfam10 support and made it available. This is a revised subset of the support initially brought in in r236962 and later reverted. The collateral efects seem to have disappeared but it is still recommended to set the CPUTYPE with caution. Reviewed by: jkim (ages ago) MFC after: 3 weeks
2013-06-01 01:02:24 +00:00
2007-03-28 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r123313)
* config.gcc: Accept barcelona as a variant of amdfam10.
* config/i386/i386.c (override_options): Likewise.
* doc/invoke.texi: Likewise.
2007-02-09 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r121763)
* config/i386/driver-i386.c: Turn on -mtune=native for AMDFAM10.
(bit_SSE4a): New.
Add ChangeLog.gcc43 for backported changes from gcc 4.3 MFC after: 3 days
2011-04-30 23:00:41 +00:00
2007-02-08 Harsha Jagasia <harsha.jagasia@amd.com> (r121726)
* config/i386/xmmintrin.h: Make inclusion of emmintrin.h
conditional to __SSE2__.
(Entries below should have been added to first ChangeLog
entry for amdfam10 dated 2007-02-05)
* config/i386/emmintrin.h: Generate #error if __SSE2__ is not
defined.
* config/i386/pmmintrin.h: Generate #error if __SSE3__ is not
defined.
* config/i386/tmmintrin.h: Generate #error if __SSSE3__ is not
defined.
2007-02-07 Jakub Jelinek <jakub@redhat.com> (r121687)
* config/i386/i386.c (override_options): Set PTA_SSSE3 for core2.
GCC: bring back experimental support for amdfam10/barcelona CPUs. Initial support for the AMD amdfam10 chipsets has been available in the gcc43 branch under GPLv2. AMD and some linux distributions (OpenSUSE) did a backport of the amdfam10 support and made it available. This is a revised subset of the support initially brought in in r236962 and later reverted. The collateral efects seem to have disappeared but it is still recommended to set the CPUTYPE with caution. Reviewed by: jkim (ages ago) MFC after: 3 weeks
2013-06-01 01:02:24 +00:00
2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
* config/i386/athlon.md (athlon_fldxf_k8, athlon_fld_k8,
athlon_fstxf_k8, athlon_fst_k8, athlon_fist, athlon_fmov,
athlon_fadd_load, athlon_fadd_load_k8, athlon_fadd, athlon_fmul,
athlon_fmul_load, athlon_fmul_load_k8, athlon_fsgn,
athlon_fdiv_load, athlon_fdiv_load_k8, athlon_fdiv_k8,
athlon_fpspc_load, athlon_fpspc, athlon_fcmov_load,
athlon_fcmov_load_k8, athlon_fcmov_k8, athlon_fcomi_load_k8,
athlon_fcomi, athlon_fcom_load_k8, athlon_fcom): Added amdfam10.
2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
* config/i386/i386.md (x86_sahf_1, cmpfp_i_mixed, cmpfp_i_sse,
cmpfp_i_i387, cmpfp_iu_mixed, cmpfp_iu_sse, cmpfp_iu_387,
swapsi, swaphi_1, swapqi_1, swapdi_rex64, fix_truncsfdi_sse,
fix_truncdfdi_sse, fix_truncsfsi_sse, fix_truncdfsi_sse,
x86_fldcw_1, floatsisf2_mixed, floatsisf2_sse, floatdisf2_mixed,
floatdisf2_sse, floatsidf2_mixed, floatsidf2_sse,
floatdidf2_mixed, floatdidf2_sse, muldi3_1_rex64, mulsi3_1,
mulsi3_1_zext, mulhi3_1, mulqi3_1, umulqihi3_1, mulqihi3_insn,
umulditi3_insn, umulsidi3_insn, mulditi3_insn, mulsidi3_insn,
umuldi3_highpart_rex64, umulsi3_highpart_insn,
umulsi3_highpart_zext, smuldi3_highpart_rex64,
smulsi3_highpart_insn, smulsi3_highpart_zext, x86_64_shld,
x86_shld_1, x86_64_shrd, sqrtsf2_mixed, sqrtsf2_sse,
sqrtsf2_i387, sqrtdf2_mixed, sqrtdf2_sse, sqrtdf2_i387,
sqrtextendsfdf2_i387, sqrtxf2, sqrtextendsfxf2_i387,
sqrtextenddfxf2_i387): Added amdfam10_decode.
* config/i386/athlon.md (athlon_idirect_amdfam10,
athlon_ivector_amdfam10, athlon_idirect_load_amdfam10,
athlon_ivector_load_amdfam10, athlon_idirect_both_amdfam10,
athlon_ivector_both_amdfam10, athlon_idirect_store_amdfam10,
athlon_ivector_store_amdfam10): New define_insn_reservation.
(athlon_idirect_loadmov, athlon_idirect_movstore): Added
amdfam10.
2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
* config/i386/athlon.md (athlon_call_amdfam10,
athlon_pop_amdfam10, athlon_lea_amdfam10): New
define_insn_reservation.
(athlon_branch, athlon_push, athlon_leave_k8, athlon_imul_k8,
athlon_imul_k8_DI, athlon_imul_mem_k8, athlon_imul_mem_k8_DI,
athlon_idiv, athlon_idiv_mem, athlon_str): Added amdfam10.
2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
* config/i386/athlon.md (athlon_sseld_amdfam10,
athlon_mmxld_amdfam10, athlon_ssest_amdfam10,
athlon_mmxssest_short_amdfam10): New define_insn_reservation.
2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
* config/i386/athlon.md (athlon_sseins_amdfam10): New
define_insn_reservation.
* config/i386/i386.md (sseins): Added sseins to define_attr type
and define_attr unit.
* config/i386/sse.md: Set type attribute to sseins for insertq
and insertqi.
2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
* config/i386/athlon.md (sselog_load_amdfam10, sselog_amdfam10,
ssecmpvector_load_amdfam10, ssecmpvector_amdfam10,
ssecomi_load_amdfam10, ssecomi_amdfam10,
sseaddvector_load_amdfam10, sseaddvector_amdfam10): New
define_insn_reservation.
(ssecmp_load_k8, ssecmp, sseadd_load_k8, seadd): Added amdfam10.
2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
* config/i386/athlon.md (cvtss2sd_load_amdfam10,
cvtss2sd_amdfam10, cvtps2pd_load_amdfam10, cvtps2pd_amdfam10,
cvtsi2sd_load_amdfam10, cvtsi2ss_load_amdfam10,
cvtsi2sd_amdfam10, cvtsi2ss_amdfam10, cvtsd2ss_load_amdfam10,
cvtsd2ss_amdfam10, cvtpd2ps_load_amdfam10, cvtpd2ps_amdfam10,
cvtsX2si_load_amdfam10, cvtsX2si_amdfam10): New
define_insn_reservation.
* config/i386/sse.md (cvtsi2ss, cvtsi2ssq, cvtss2si,
cvtss2siq, cvttss2si, cvttss2siq, cvtsi2sd, cvtsi2sdq,
cvtsd2si, cvtsd2siq, cvttsd2si, cvttsd2siq,
cvtpd2dq, cvttpd2dq, cvtsd2ss, cvtss2sd,
cvtpd2ps, cvtps2pd): Added amdfam10_decode attribute.
2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
* config/i386/athlon.md (athlon_ssedivvector_amdfam10,
athlon_ssedivvector_load_amdfam10, athlon_ssemulvector_amdfam10,
athlon_ssemulvector_load_amdfam10): New define_insn_reservation.
(athlon_ssediv, athlon_ssediv_load_k8, athlon_ssemul,
athlon_ssemul_load_k8): Added amdfam10.
2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
* config/i386/i386.h (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL): New macro.
(x86_sse_unaligned_move_optimal): New variable.
* config/i386/i386.c (x86_sse_unaligned_move_optimal): Enable for
m_AMDFAM10.
(ix86_expand_vector_move_misalign): Add code to generate movupd/movups
for unaligned vector SSE double/single precision loads for AMDFAM10.
2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
* config/i386/i386.h (TARGET_AMDFAM10): New macro.
(TARGET_CPU_CPP_BUILTINS): Add code for amdfam10.
Define TARGET_CPU_DEFAULT_amdfam10.
(TARGET_CPU_DEFAULT_NAMES): Add amdfam10.
(processor_type): Add PROCESSOR_AMDFAM10.
* config/i386/i386.md: Add amdfam10 as a new cpu attribute to match
processor_type in config/i386/i386.h.
Enable imul peepholes for TARGET_AMDFAM10.
* config.gcc: Add support for --with-cpu option for amdfam10.
* config/i386/i386.c (amdfam10_cost): New variable.
(m_AMDFAM10): New macro.
(m_ATHLON_K8_AMDFAM10): New macro.
(x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen,
x86_cmove, x86_3dnow_a, x86_deep_branch, x86_use_simode_fiop,
x86_promote_QImode, x86_integer_DFmode_moves,
x86_partial_reg_dependency, x86_memory_mismatch_stall,
x86_accumulate_outgoing_args, x86_arch_always_fancy_math_387,
x86_sse_partial_reg_dependency, x86_sse_typeless_stores,
x86_use_ffreep, x86_use_incdec, x86_four_jump_limit,
x86_schedule, x86_use_bt, x86_cmpxchg16b, x86_pad_returns):
Enable/disable for amdfam10.
(override_options): Add amdfam10_cost to processor_target_table.
Set up PROCESSOR_AMDFAM10 for amdfam10 entry in
processor_alias_table.
(ix86_issue_rate): Add PROCESSOR_AMDFAM10.
(ix86_adjust_cost): Add code for amdfam10.
2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625)
* config/i386/i386.opt: Add new Advanced Bit Manipulation (-mabm)
instruction set feature flag. Add new (-mpopcnt) flag for popcnt
instruction. Add new SSE4A (-msse4a) instruction set feature flag.
* config/i386/i386.h: Add builtin definition for SSE4A.
* config/i386/i386.md: Add support for ABM instructions
(popcnt and lzcnt).
* config/i386/sse.md: Add support for SSE4A instructions
(movntss, movntsd, extrq, insertq).
* config/i386/i386.c: Add support for ABM and SSE4A builtins.
Add -march=amdfam10 flag.
* config/i386/ammintrin.h: Add support for SSE4A intrinsics.
* doc/invoke.texi: Add documentation on flags for sse4a, abm, popcnt
and amdfam10.
* doc/extend.texi: Add documentation for SSE4A builtins.
2007-01-24 Jakub Jelinek <jakub@redhat.com> (r121140)
* config/i386/i386.h (x86_cmpxchg16b): Remove const.
(TARGET_CMPXCHG16B): Define to x86_cmpxchg16b.
* config/i386/i386.c (x86_cmpxchg16b): Remove const.
(override_options): Add PTA_CX16 flag. Set x86_cmpxchg16b
for CPUs that have PTA_CX16 set.
Add ChangeLog.gcc43 for backported changes from gcc 4.3 MFC after: 3 days
2011-04-30 23:00:41 +00:00
2007-01-17 Eric Christopher <echristo@apple.com> (r120846)
* config.gcc: Support core2 processor.
2006-12-02 H.J. Lu <hongjiu.lu@intel.com> (r119454 - partial)
PR target/30040
* config/i386/driver-i386.c (bit_SSSE3): New.
GCC: bring back experimental support for amdfam10/barcelona CPUs. Initial support for the AMD amdfam10 chipsets has been available in the gcc43 branch under GPLv2. AMD and some linux distributions (OpenSUSE) did a backport of the amdfam10 support and made it available. This is a revised subset of the support initially brought in in r236962 and later reverted. The collateral efects seem to have disappeared but it is still recommended to set the CPUTYPE with caution. Reviewed by: jkim (ages ago) MFC after: 3 weeks
2013-06-01 01:02:24 +00:00
2006-11-27 Uros Bizjak <ubizjak@gmail.com> (r119260)
* config/i386/i386.c (x86_ext_80387_constants): Add m_K8, m_CORE2
and m_GENERIC64.
Add ChangeLog.gcc43 for backported changes from gcc 4.3 MFC after: 3 days
2011-04-30 23:00:41 +00:00
2006-11-18 Vladimir Makarov <vmakarov@redhat.com> (r118973)
* doc/invoke.texi (core2): Add item.
* config/i386/i386.h (TARGET_CORE2, TARGET_CPU_DEFAULT_core2): New
macros.
(TARGET_CPU_CPP_BUILTINS): Add code for core2.
(TARGET_CPU_DEFAULT_generic): Change value.
(TARGET_CPU_DEFAULT_NAMES): Add core2.
(processor_type): Add new constant PROCESSOR_CORE2.
* config/i386/i386.md (cpu): Add core2.
* config/i386/i386.c (core2_cost): New initialized variable.
(m_CORE2): New macro.
(x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen,
x86_deep_branch, x86_partial_reg_stall, x86_use_simode_fiop,
x86_use_cltd, x86_promote_QImode, x86_sub_esp_4, x86_sub_esp_8,
x86_add_esp_4, x86_add_esp_8, x86_integer_DFmode_moves,
x86_partial_reg_dependency, x86_memory_mismatch_stall,
x86_accumulate_outgoing_args, x86_prologue_using_move,
x86_epilogue_using_move, x86_arch_always_fancy_math_387,
x86_sse_partial_reg_dependency, x86_rep_movl_optimal,
x86_use_incdec, x86_four_jump_limit, x86_schedule,
x86_pad_returns): Add m_CORE2.
(override_options): Add entries for Core2.
(ix86_issue_rate): Add case for Core2.
2006-10-27 Vladimir Makarov <vmakarov@redhat.com> (r118090)
* config/i386/i386.h (TARGET_GEODE):
(TARGET_CPU_CPP_BUILTINS): Add code for geode.
(TARGET_CPU_DEFAULT_geode): New macro.
(TARGET_CPU_DEFAULT_k6, TARGET_CPU_DEFAULT_k6_2,
TARGET_CPU_DEFAULT_k6_3, TARGET_CPU_DEFAULT_athlon,
TARGET_CPU_DEFAULT_athlon_sse, TARGET_CPU_DEFAULT_k8,
TARGET_CPU_DEFAULT_pentium_m, TARGET_CPU_DEFAULT_prescott,
TARGET_CPU_DEFAULT_nocona, TARGET_CPU_DEFAULT_generic): Increase
the macro values.
(TARGET_CPU_DEFAULT_NAMES): Add geode.
(processor_type): Add PROCESSOR_GEODE.
* config/i386/i386.md: Include geode.md.
(cpu): Add geode.
* config/i386/i386.c (geode_cost): New initialized global
variable.
(m_GEODE, m_K6_GEODE): New macros.
(x86_use_leave, x86_push_memory, x86_deep_branch, x86_use_sahf,
x86_use_himode_fiop, x86_promote_QImode, x86_add_esp_4,
x86_add_esp_8, x86_rep_movl_optimal, x86_ext_80387_constants,
x86_schedule): Use m_K6_GEODE instead of m_K6.
(x86_movx, x86_cmove): Set up m_GEODE.
(x86_integer_DFmode_moves): Clear m_GEODE.
(processor_target_table): Add entry for geode.
(processor_alias_table): Ditto.
* config/i386/geode.md: New file.
* doc/invoke.texi: Add entry about geode processor.
Revert r236962 - Experimental amdfam10/barcelona support. The patches are unexpectedly causing gcc to fail while building ports/graphics/ImageMagick even when the cpu flags are not used. Reported by: Andreas Tobler
2012-06-13 20:21:08 +00:00
Bring a couple of fixes for gcc optimizations. The GCC4.3 branch contains some optimization fixes that were not considered regressions and therefore were never backported. We are bringing a couple of them that are under GPLv2 since they were made before the license switch upstream. While here, add the GCC revision numbers in the log. Discussed with: jkim MFC after: 1 week
2012-06-21 16:49:20 +00:00
2006-10-24 Richard Guenther <rguenther@suse.de> (r118001)
Clean an inconsistency with -ffinite-math-only. Backported from the gcc-4_3-branch, revision 118001, under the GPLv2. This issue was also fixed in Apple's gcc. PR: 157025 Reviewed by: mm Approved by: jhb (mentor) MFC: 2 weeks
2011-12-21 01:58:35 +00:00
PR middle-end/28796
* builtins.c (fold_builtin_classify): Use HONOR_INFINITIES
and HONOR_NANS instead of MODE_HAS_INFINITIES and MODE_HAS_NANS
for deciding optimizations in consistency with fold-const.c
(fold_builtin_unordered_cmp): Likewise.
Add ChangeLog.gcc43 for backported changes from gcc 4.3 MFC after: 3 days
2011-04-30 23:00:41 +00:00
2006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117958)
* config.gcc (i[34567]86-*-*): Add tmmintrin.h to extra_headers.
(x86_64-*-*): Likewise.
* config/i386/i386.c (pta_flags): Add PTA_SSSE3.
(override_options): Check SSSE3.
(ix86_builtins): Add IX86_BUILTIN_PHADDW, IX86_BUILTIN_PHADDD,
IX86_BUILTIN_PHADDSW, IX86_BUILTIN_PHSUBW, IX86_BUILTIN_PHSUBD,
IX86_BUILTIN_PHSUBSW, IX86_BUILTIN_PMADDUBSW,
IX86_BUILTIN_PMULHRSW, IX86_BUILTIN_PSHUFB,
IX86_BUILTIN_PSIGNB, IX86_BUILTIN_PSIGNW, IX86_BUILTIN_PSIGND,
IX86_BUILTIN_PALIGNR, IX86_BUILTIN_PABSB, IX86_BUILTIN_PABSW,
IX86_BUILTIN_PABSD, IX86_BUILTIN_PHADDW128,
IX86_BUILTIN_PHADDD128, IX86_BUILTIN_PHADDSW128,
IX86_BUILTIN_PHSUBW128, IX86_BUILTIN_PHSUBD128,
IX86_BUILTIN_PHSUBSW128, IX86_BUILTIN_PMADDUBSW128,
IX86_BUILTIN_PMULHRSW128, IX86_BUILTIN_PSHUFB128,
IX86_BUILTIN_PSIGNB128, IX86_BUILTIN_PSIGNW128,
IX86_BUILTIN_PSIGND128, IX86_BUILTIN_PALIGNR128,
IX86_BUILTIN_PABSB128, IX86_BUILTIN_PABSW128 and
IX86_BUILTIN_PABSD128.
(bdesc_2arg): Add SSSE3.
(bdesc_1arg): Likewise.
(ix86_init_mmx_sse_builtins): Support SSSE3.
(ix86_expand_builtin): Likewise.
* config/i386/i386.h (TARGET_CPU_CPP_BUILTINS): Likewise.
* config/i386/i386.md (UNSPEC_PSHUFB): New.
(UNSPEC_PSIGN): Likewise.
(UNSPEC_PALIGNR): Likewise.
Include mmx.md before sse.md.
* config/i386/i386.opt: Add -mssse3.
* config/i386/sse.md (ssse3_phaddwv8hi3): New pattern for SSSE3.
(ssse3_phaddwv4hi3): Likewise.
(ssse3_phadddv4si3): Likewise.
(ssse3_phadddv2si3): Likewise.
(ssse3_phaddswv8hi3): Likewise.
(ssse3_phaddswv4hi3): Likewise.
(ssse3_phsubwv8hi3): Likewise.
(ssse3_phsubwv4hi3): Likewise.
(ssse3_phsubdv4si3): Likewise.
(ssse3_phsubdv2si3): Likewise.
(ssse3_phsubswv8hi3): Likewise.
(ssse3_phsubswv4hi3): Likewise.
(ssse3_pmaddubswv8hi3): Likewise.
(ssse3_pmaddubswv4hi3): Likewise.
(ssse3_pmulhrswv8hi3): Likewise.
(ssse3_pmulhrswv4hi3): Likewise.
(ssse3_pshufbv16qi3): Likewise.
(ssse3_pshufbv8qi3): Likewise.
(ssse3_psign<mode>3): Likewise.
(ssse3_psign<mode>3): Likewise.
(ssse3_palignrti): Likewise.
(ssse3_palignrdi): Likewise.
(abs<mode>2): Likewise.
(abs<mode>2): Likewise.
* config/i386/tmmintrin.h: New file.
* doc/extend.texi: Document SSSE3 built-in functions.
* doc/invoke.texi: Document -mssse3/-mno-ssse3 switches.
Fix a typo in GCC affecting calculations with -ffast-math. The fix is similar to the one applied in GCC-4.3 in GCCSVN-r117929 under the GPLv2. Submitted by: Andrey Simonenko Reviewed by: mm Approved by: jhb (mentor) MFC after: 3 days
2012-04-05 15:16:51 +00:00
GCC: bring back experimental support for amdfam10/barcelona CPUs. Initial support for the AMD amdfam10 chipsets has been available in the gcc43 branch under GPLv2. AMD and some linux distributions (OpenSUSE) did a backport of the amdfam10 support and made it available. This is a revised subset of the support initially brought in in r236962 and later reverted. The collateral efects seem to have disappeared but it is still recommended to set the CPUTYPE with caution. Reviewed by: jkim (ages ago) MFC after: 3 weeks
2013-06-01 01:02:24 +00:00
2006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117959)
Update the gcc43 changelog. The issue solved in r250392 actually originated upstream and was fixed in upstream gcc43 branch in 2006/10/24 (under GPLv2). Register it in the appropriate ChangeLog for reference. MFC after: 3 days
2013-05-12 03:36:28 +00:00
* config/i386/tmmintrin.h: Remove the duplicated content.
Bring a couple of fixes for gcc optimizations. The GCC4.3 branch contains some optimization fixes that were not considered regressions and therefore were never backported. We are bringing a couple of them that are under GPLv2 since they were made before the license switch upstream. While here, add the GCC revision numbers in the log. Discussed with: jkim MFC after: 1 week
2012-06-21 16:49:20 +00:00
2006-10-21 Richard Guenther <rguenther@suse.de> (r117932)
PR tree-optimization/3511
* tree-ssa-pre.c (phi_translate): Fold CALL_EXPRs that
got new invariant arguments during PHI translation.
2006-10-21 Richard Guenther <rguenther@suse.de> (r117929)
Fix a typo in GCC affecting calculations with -ffast-math. The fix is similar to the one applied in GCC-4.3 in GCCSVN-r117929 under the GPLv2. Submitted by: Andrey Simonenko Reviewed by: mm Approved by: jhb (mentor) MFC after: 3 days
2012-04-05 15:16:51 +00:00
* builtins.c (fold_builtin_classify): Fix typo.
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