109 lines
4.8 KiB
Diff
109 lines
4.8 KiB
Diff
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Pull in r222587 from upstream llvm trunk (by Jörg Sonnenberger):
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Fix transformation of add with pc argument to adr for non-immediate
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arguments.
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This fixes an "Unimplemented" error when assembling certain ARM add
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instructions with pc-relative arguments.
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Reported by: sbruno
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PR: 196412, 196423
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Introduced here: http://svnweb.freebsd.org/changeset/base/276537
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Index: lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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===================================================================
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--- lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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+++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@@ -314,7 +314,7 @@ class ARMAsmParser : public MCTargetAsmParser {
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void cvtThumbBranches(MCInst &Inst, const OperandVector &);
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bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
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- bool processInstruction(MCInst &Inst, const OperandVector &Ops);
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+ bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
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bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
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bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
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@@ -6175,7 +6175,8 @@ static unsigned getRealVLDOpcode(unsigned Opc, uns
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}
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bool ARMAsmParser::processInstruction(MCInst &Inst,
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- const OperandVector &Operands) {
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+ const OperandVector &Operands,
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+ MCStreamer &Out) {
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switch (Inst.getOpcode()) {
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// Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
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case ARM::LDRT_POST:
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@@ -6216,12 +6217,31 @@ bool ARMAsmParser::processInstruction(MCInst &Inst
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// Alias for alternate form of 'ADR Rd, #imm' instruction.
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case ARM::ADDri: {
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if (Inst.getOperand(1).getReg() != ARM::PC ||
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- Inst.getOperand(5).getReg() != 0)
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+ Inst.getOperand(5).getReg() != 0 ||
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+ !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm()))
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return false;
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MCInst TmpInst;
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TmpInst.setOpcode(ARM::ADR);
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TmpInst.addOperand(Inst.getOperand(0));
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- TmpInst.addOperand(Inst.getOperand(2));
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+ if (Inst.getOperand(2).isImm()) {
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+ TmpInst.addOperand(Inst.getOperand(2));
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+ } else {
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+ // Turn PC-relative expression into absolute expression.
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+ // Reading PC provides the start of the current instruction + 8 and
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+ // the transform to adr is biased by that.
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+ MCSymbol *Dot = getContext().CreateTempSymbol();
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+ Out.EmitLabel(Dot);
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+ const MCExpr *OpExpr = Inst.getOperand(2).getExpr();
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+ const MCExpr *InstPC = MCSymbolRefExpr::Create(Dot,
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+ MCSymbolRefExpr::VK_None,
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+ getContext());
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+ const MCExpr *Const8 = MCConstantExpr::Create(8, getContext());
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+ const MCExpr *ReadPC = MCBinaryExpr::CreateAdd(InstPC, Const8,
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+ getContext());
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+ const MCExpr *FixupAddr = MCBinaryExpr::CreateAdd(ReadPC, OpExpr,
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+ getContext());
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+ TmpInst.addOperand(MCOperand::CreateExpr(FixupAddr));
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+ }
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TmpInst.addOperand(Inst.getOperand(3));
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TmpInst.addOperand(Inst.getOperand(4));
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Inst = TmpInst;
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@@ -8061,7 +8081,7 @@ bool ARMAsmParser::MatchAndEmitInstruction(SMLoc I
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// encoding is selected. Loop on it while changes happen so the
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// individual transformations can chain off each other. E.g.,
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// tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
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- while (processInstruction(Inst, Operands))
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+ while (processInstruction(Inst, Operands, Out))
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;
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// Only after the instruction is fully processed, we can validate it
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Index: test/MC/ARM/basic-arm-instructions.s
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===================================================================
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--- test/MC/ARM/basic-arm-instructions.s
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+++ test/MC/ARM/basic-arm-instructions.s
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@@ -191,8 +191,10 @@ Lforward:
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add r0, #-4
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add r4, r5, #-21
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- add r0, pc, #0xc0000000
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+ add r0, pc, #0xc0000000
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+ add r0, pc, #(Lback - .)
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+
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@ CHECK: add r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe2]
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@ CHECK: add r4, r5, r6 @ encoding: [0x06,0x40,0x85,0xe0]
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@ CHECK: add r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x85,0xe0]
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@@ -222,7 +224,11 @@ Lforward:
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@ CHECK: sub r0, r0, #4 @ encoding: [0x04,0x00,0x40,0xe2]
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@ CHECK: sub r4, r5, #21 @ encoding: [0x15,0x40,0x45,0xe2]
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-@ CHECK: adr r0, #-1073741824 @ encoding: [0x03,0x01,0x8f,0xe2]
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+@ CHECK: adr r0, #-1073741824 @ encoding: [0x03,0x01,0x8f,0xe2]
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+@ CHECK: Ltmp0:
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+@ CHECK-NEXT: Ltmp1:
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+@ CHECK-NEXT: adr r0, (Ltmp1+8)+(Lback-Ltmp0) @ encoding: [A,A,0x0f'A',0xe2'A']
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+@ CHECK-NEXT: @ fixup A - offset: 0, value: (Ltmp1+8)+(Lback-Ltmp0), kind: fixup_arm_adr_pcrel_12
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@ Test right shift by 32, which is encoded as 0
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add r3, r1, r2, lsr #32
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