freebsd-dev/sys/conf/options.riscv


RISCV				opt_global.h	# For cpu RISCV to work
INTRNG				opt_global.h
Welcome the RISC-V 64-bit kernel. This is the final step required allowing to compile and to run RISC-V kernel and userland from HEAD. RISC-V is a completely open ISA that is freely available to academia and industry. Thanks to all the people involved! Special thanks to Andrew Turner, David Chisnall, Ed Maste, Konstantin Belousov, John Baldwin and Arun Thomas for their help. Thanks to Robert Watson for organizing this project. This project sponsored by UK Higher Education Innovation Fund (HEIF5) and DARPA CTSRD project at the University of Cambridge Computer Laboratory. FreeBSD/RISC-V project home: https://wiki.freebsd.org/riscv Reviewed by: andrew, emaste, kib Relnotes: Yes Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D4982 2016-01-29 15:12:31 +00:00
conf: Document why we have ARM64 and RISCV options These are needed for the 'cpu ARM64' and 'cpu RISCV' options in these architecture's config files. cpu lines are non-optional in config(8), so we must define them here. There's no other use for them in the tree. Sponsored by: Netflix 2022-10-20 15:29:33 +00:00			`RISCV opt_global.h # For cpu RISCV to work`
o Add driver for PLIC (Platform-Level Interrupt Controller) device. o Convert interrupt machdep support to use INTRNG code. Sponsored by: DARPA, AFRL 2018-06-12 17:45:15 +00:00			`INTRNG opt_global.h`