2003-11-03 21:53:38 +00:00
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/*-
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* Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_isa.h"
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#include "opt_no_mixed_mode.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/apicreg.h>
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#include <machine/frame.h>
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#include <machine/intr_machdep.h>
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#include <machine/apicvar.h>
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#include <machine/segments.h>
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#if defined(DEV_ISA) && !defined(NO_MIXED_MODE)
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#define MIXED_MODE
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#endif
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#define IOAPIC_ISA_INTS 16
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#define IOAPIC_MEM_REGION 32
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#define IOAPIC_REDTBL_LO(i) (IOAPIC_REDTBL + (i) * 2)
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#define IOAPIC_REDTBL_HI(i) (IOAPIC_REDTBL_LO(i) + 1)
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#define VECTOR_EXTINT -1
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#define VECTOR_NMI -2
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#define VECTOR_SMI -3
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#define VECTOR_DISABLED -4
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#define DEST_NONE -1
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#define DEST_EXTINT -2
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#define TODO printf("%s: not implemented!\n", __func__)
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MALLOC_DEFINE(M_IOAPIC, "I/O APIC", "I/O APIC structures");
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/*
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* New interrupt support code..
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*
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* XXX: we really should have the interrupt cookie passed up from new-bus
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* just be a int pin, and not map 1:1 to interrupt vector number but should
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* use INTR_TYPE_FOO to set priority bands for device classes and do all the
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* magic remapping of intpin to vector in here. For now we just cheat as on
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* ia64 and map intpin X to vector NRSVIDT + X. Note that we assume that the
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* first IO APIC has ISA interrupts on pins 1-15. Not sure how you are
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* really supposed to figure out which IO APIC in a system with multiple IO
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* APIC's actually has the ISA interrupts routed to it. As far as interrupt
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* pin numbers, we use the ACPI System Interrupt number model where each
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* IO APIC has a contiguous chunk of the System Interrupt address space.
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*/
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/*
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* Direct the ExtINT pin on the first I/O APIC to a logical cluster of
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* CPUs rather than a physical destination of just the BSP.
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*
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* Note: This is disabled by default as test systems seem to croak with it
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* enabled.
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#define ENABLE_EXTINT_LOGICAL_DESTINATION
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*/
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struct ioapic_intsrc {
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struct intsrc io_intsrc;
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int io_intpin:8;
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int io_vector:8;
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int io_activehi:1;
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int io_edgetrigger:1;
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int io_masked:1;
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int io_dest:5;
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};
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struct ioapic {
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struct pic io_pic;
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u_int io_id:8; /* logical ID */
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u_int io_apic_id:4;
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u_int io_intbase:8; /* System Interrupt base */
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u_int io_numintr:8;
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volatile ioapic_t *io_addr; /* XXX: should use bus_space */
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STAILQ_ENTRY(ioapic) io_next;
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struct ioapic_intsrc io_pins[0];
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};
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static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list);
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static u_int next_id, program_logical_dest;
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static u_int ioapic_read(volatile ioapic_t *apic, int reg);
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static void ioapic_write(volatile ioapic_t *apic, int reg, u_int val);
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static void ioapic_enable_source(struct intsrc *isrc);
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static void ioapic_disable_source(struct intsrc *isrc);
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static void ioapic_eoi_source(struct intsrc *isrc);
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static void ioapic_enable_intr(struct intsrc *isrc);
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static int ioapic_vector(struct intsrc *isrc);
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static int ioapic_source_pending(struct intsrc *isrc);
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static void ioapic_suspend(struct intsrc *isrc);
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static void ioapic_resume(struct intsrc *isrc);
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static void ioapic_program_destination(struct ioapic_intsrc *intpin);
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#ifdef MIXED_MODE
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static void ioapic_setup_mixed_mode(struct ioapic_intsrc *intpin);
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#endif
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struct pic ioapic_template = { ioapic_enable_source, ioapic_disable_source,
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ioapic_eoi_source, ioapic_enable_intr,
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ioapic_vector, ioapic_source_pending,
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ioapic_suspend, ioapic_resume };
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static int next_ioapic_base, logical_clusters, current_cluster;
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static u_int
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ioapic_read(volatile ioapic_t *apic, int reg)
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{
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mtx_assert(&icu_lock, MA_OWNED);
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apic->ioregsel = reg;
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return (apic->iowin);
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}
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static void
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ioapic_write(volatile ioapic_t *apic, int reg, u_int val)
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{
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mtx_assert(&icu_lock, MA_OWNED);
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apic->ioregsel = reg;
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apic->iowin = val;
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}
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static void
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ioapic_enable_source(struct intsrc *isrc)
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{
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struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
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struct ioapic *io = (struct ioapic *)isrc->is_pic;
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uint32_t flags;
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mtx_lock_spin(&icu_lock);
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if (intpin->io_masked) {
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flags = ioapic_read(io->io_addr,
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IOAPIC_REDTBL_LO(intpin->io_intpin));
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flags &= ~(IOART_INTMASK);
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ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
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flags);
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intpin->io_masked = 0;
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}
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mtx_unlock_spin(&icu_lock);
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}
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static void
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ioapic_disable_source(struct intsrc *isrc)
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{
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struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
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struct ioapic *io = (struct ioapic *)isrc->is_pic;
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uint32_t flags;
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mtx_lock_spin(&icu_lock);
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if (!intpin->io_masked && !intpin->io_edgetrigger) {
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flags = ioapic_read(io->io_addr,
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IOAPIC_REDTBL_LO(intpin->io_intpin));
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flags |= IOART_INTMSET;
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ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
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flags);
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intpin->io_masked = 1;
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}
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mtx_unlock_spin(&icu_lock);
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}
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static void
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ioapic_eoi_source(struct intsrc *isrc)
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{
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TODO;
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/* lapic_eoi(); */
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}
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/*
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* Program an individual intpin's logical destination.
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*/
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static void
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ioapic_program_destination(struct ioapic_intsrc *intpin)
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{
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struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic;
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uint32_t value;
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KASSERT(intpin->io_dest != DEST_NONE,
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("intpin not assigned to a cluster"));
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KASSERT(intpin->io_dest != DEST_EXTINT,
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("intpin routed via ExtINT"));
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if (bootverbose) {
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printf("ioapic%u: routing intpin %u (", io->io_id,
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intpin->io_intpin);
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if (intpin->io_vector == VECTOR_EXTINT)
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printf("ExtINT");
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else
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printf("IRQ %u", intpin->io_vector);
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printf(") to cluster %u\n", intpin->io_dest);
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}
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mtx_lock_spin(&icu_lock);
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value = ioapic_read(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin));
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value &= ~IOART_DESTMOD;
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value |= IOART_DESTLOG;
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ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), value);
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value = ioapic_read(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin));
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value &= ~IOART_DEST;
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value |= (intpin->io_dest << APIC_ID_CLUSTER_SHIFT |
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APIC_ID_CLUSTER_ID) << APIC_ID_SHIFT;
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ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), value);
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mtx_unlock_spin(&icu_lock);
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}
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static void
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ioapic_assign_cluster(struct ioapic_intsrc *intpin)
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{
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/*
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* Assign this intpin to a logical APIC cluster in a
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* round-robin fashion. We don't actually use the logical
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* destination for this intpin until after all the CPU's
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* have been started so that we don't end up with interrupts
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* that don't go anywhere. Another alternative might be to
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* start up the CPU's earlier so that they can handle interrupts
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* sooner.
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*/
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intpin->io_dest = current_cluster;
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current_cluster++;
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if (current_cluster >= logical_clusters)
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current_cluster = 0;
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if (program_logical_dest)
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ioapic_program_destination(intpin);
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}
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static void
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ioapic_enable_intr(struct intsrc *isrc)
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{
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struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
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KASSERT(intpin->io_dest != DEST_EXTINT,
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("ExtINT pin trying to use ioapic enable_intr method"));
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if (intpin->io_dest == DEST_NONE) {
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ioapic_assign_cluster(intpin);
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lapic_enable_intr(intpin->io_vector);
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}
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}
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static int
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ioapic_vector(struct intsrc *isrc)
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{
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struct ioapic_intsrc *pin;
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pin = (struct ioapic_intsrc *)isrc;
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return (pin->io_vector);
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}
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static int
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ioapic_source_pending(struct intsrc *isrc)
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{
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struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
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return (lapic_intr_pending(intpin->io_vector));
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}
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static void
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ioapic_suspend(struct intsrc *isrc)
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{
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TODO;
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}
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static void
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ioapic_resume(struct intsrc *isrc)
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{
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TODO;
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}
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/*
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* Allocate and return a logical cluster ID. Note that the first time
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* this is called, it returns cluster 0. ioapic_enable_intr() treats
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* the two cases of logical_clusters == 0 and logical_clusters == 1 the
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* same: one cluster of ID 0 exists. The logical_clusters == 0 case is
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* for UP kernels, which should never call this function.
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*/
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int
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ioapic_next_logical_cluster(void)
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{
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if (logical_clusters >= APIC_MAX_CLUSTER)
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panic("WARNING: Local APIC cluster IDs exhausted!");
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return (logical_clusters++);
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}
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/*
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* Create a plain I/O APIC object.
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*/
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void *
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ioapic_create(uintptr_t addr, int32_t apic_id, int intbase)
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{
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struct ioapic *io;
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struct ioapic_intsrc *intpin;
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volatile ioapic_t *apic;
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u_int numintr, i;
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uint32_t value;
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apic = (ioapic_t *)pmap_mapdev(addr, IOAPIC_MEM_REGION);
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mtx_lock_spin(&icu_lock);
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numintr = ((ioapic_read(apic, IOAPIC_VER) & IOART_VER_MAXREDIR) >>
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MAXREDIRSHIFT) + 1;
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mtx_unlock_spin(&icu_lock);
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io = malloc(sizeof(struct ioapic) +
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numintr * sizeof(struct ioapic_intsrc), M_IOAPIC, M_WAITOK);
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io->io_pic = ioapic_template;
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mtx_lock_spin(&icu_lock);
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io->io_id = next_id++;
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io->io_apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT;
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if (apic_id != -1 && io->io_apic_id != apic_id) {
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ioapic_write(apic, IOAPIC_ID, apic_id << APIC_ID_SHIFT);
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mtx_unlock_spin(&icu_lock);
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|
io->io_apic_id = apic_id;
|
|
|
|
printf("ioapic%u: Changing APIC ID to %d\n", io->io_id,
|
|
|
|
apic_id);
|
|
|
|
} else
|
|
|
|
mtx_unlock_spin(&icu_lock);
|
|
|
|
if (intbase == -1) {
|
|
|
|
intbase = next_ioapic_base;
|
|
|
|
printf("ioapic%u: Assuming intbase of %d\n", io->io_id,
|
|
|
|
intbase);
|
|
|
|
} else if (intbase != next_ioapic_base)
|
|
|
|
printf("ioapic%u: WARNING: intbase %d != expected base %d\n",
|
|
|
|
io->io_id, intbase, next_ioapic_base);
|
|
|
|
io->io_intbase = intbase;
|
|
|
|
next_ioapic_base += numintr;
|
|
|
|
io->io_numintr = numintr;
|
|
|
|
io->io_addr = apic;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize pins. Start off with interrupts disabled. Default
|
|
|
|
* to active-hi and edge-triggered for ISA interrupts and active-lo
|
|
|
|
* and level-triggered for all others.
|
|
|
|
*/
|
|
|
|
bzero(io->io_pins, sizeof(struct ioapic_intsrc) * numintr);
|
|
|
|
mtx_lock_spin(&icu_lock);
|
|
|
|
for (i = 0, intpin = io->io_pins; i < numintr; i++, intpin++) {
|
|
|
|
intpin->io_intsrc.is_pic = (struct pic *)io;
|
|
|
|
intpin->io_intpin = i;
|
|
|
|
intpin->io_vector = intbase + i;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Assume that pin 0 on the first IO APIC is an ExtINT pin by
|
|
|
|
* default. Assume that intpins 1-15 are ISA interrupts and
|
|
|
|
* use suitable defaults for those. Assume that all other
|
|
|
|
* intpins are PCI interrupts. Enable the ExtINT pin by
|
|
|
|
* default but mask all other pins.
|
|
|
|
*/
|
|
|
|
if (intpin->io_vector == 0) {
|
|
|
|
intpin->io_activehi = 1;
|
|
|
|
intpin->io_edgetrigger = 1;
|
|
|
|
intpin->io_vector = VECTOR_EXTINT;
|
|
|
|
intpin->io_masked = 0;
|
|
|
|
} else if (intpin->io_vector < IOAPIC_ISA_INTS) {
|
|
|
|
intpin->io_activehi = 1;
|
|
|
|
intpin->io_edgetrigger = 1;
|
|
|
|
intpin->io_masked = 1;
|
|
|
|
} else {
|
|
|
|
intpin->io_activehi = 0;
|
|
|
|
intpin->io_edgetrigger = 0;
|
|
|
|
intpin->io_masked = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Start off without a logical cluster destination until
|
|
|
|
* the pin is enabled.
|
|
|
|
*/
|
|
|
|
intpin->io_dest = DEST_NONE;
|
|
|
|
if (bootverbose) {
|
|
|
|
printf("ioapic%u: intpin %d -> ", io->io_id, i);
|
|
|
|
if (intpin->io_vector == VECTOR_EXTINT)
|
|
|
|
printf("ExtINT\n");
|
|
|
|
else
|
|
|
|
printf("irq %d\n", intpin->io_vector);
|
|
|
|
}
|
|
|
|
value = ioapic_read(apic, IOAPIC_REDTBL_LO(i));
|
|
|
|
ioapic_write(apic, IOAPIC_REDTBL_LO(i), value | IOART_INTMSET);
|
|
|
|
}
|
|
|
|
mtx_unlock_spin(&icu_lock);
|
|
|
|
|
|
|
|
return (io);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ioapic_get_vector(void *cookie, u_int pin)
|
|
|
|
{
|
|
|
|
struct ioapic *io;
|
|
|
|
|
|
|
|
io = (struct ioapic *)cookie;
|
|
|
|
if (pin >= io->io_numintr)
|
|
|
|
return (-1);
|
|
|
|
return (io->io_pins[pin].io_vector);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ioapic_disable_pin(void *cookie, u_int pin)
|
|
|
|
{
|
|
|
|
struct ioapic *io;
|
|
|
|
|
|
|
|
io = (struct ioapic *)cookie;
|
|
|
|
if (pin >= io->io_numintr)
|
|
|
|
return (EINVAL);
|
|
|
|
if (io->io_pins[pin].io_vector == VECTOR_DISABLED)
|
|
|
|
return (EINVAL);
|
|
|
|
io->io_pins[pin].io_vector = VECTOR_DISABLED;
|
|
|
|
if (bootverbose)
|
|
|
|
printf("ioapic%u: intpin %d disabled\n", io->io_id, pin);
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ioapic_remap_vector(void *cookie, u_int pin, int vector)
|
|
|
|
{
|
|
|
|
struct ioapic *io;
|
|
|
|
|
|
|
|
io = (struct ioapic *)cookie;
|
|
|
|
if (pin >= io->io_numintr || vector < 0)
|
|
|
|
return (EINVAL);
|
|
|
|
if (io->io_pins[pin].io_vector < 0)
|
|
|
|
return (EINVAL);
|
|
|
|
io->io_pins[pin].io_vector = vector;
|
|
|
|
if (bootverbose)
|
|
|
|
printf("ioapic%u: Routing IRQ %d -> intpin %d\n", io->io_id,
|
|
|
|
vector, pin);
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ioapic_set_nmi(void *cookie, u_int pin)
|
|
|
|
{
|
|
|
|
struct ioapic *io;
|
|
|
|
|
|
|
|
io = (struct ioapic *)cookie;
|
|
|
|
if (pin >= io->io_numintr)
|
|
|
|
return (EINVAL);
|
|
|
|
if (io->io_pins[pin].io_vector < 0)
|
|
|
|
return (EINVAL);
|
|
|
|
io->io_pins[pin].io_vector = VECTOR_NMI;
|
|
|
|
io->io_pins[pin].io_masked = 0;
|
|
|
|
io->io_pins[pin].io_edgetrigger = 1;
|
|
|
|
io->io_pins[pin].io_activehi = 1;
|
|
|
|
if (bootverbose)
|
|
|
|
printf("ioapic%u: Routing NMI -> intpin %d\n",
|
|
|
|
io->io_id, pin);
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ioapic_set_smi(void *cookie, u_int pin)
|
|
|
|
{
|
|
|
|
struct ioapic *io;
|
|
|
|
|
|
|
|
io = (struct ioapic *)cookie;
|
|
|
|
if (pin >= io->io_numintr)
|
|
|
|
return (EINVAL);
|
|
|
|
if (io->io_pins[pin].io_vector < 0)
|
|
|
|
return (EINVAL);
|
|
|
|
io->io_pins[pin].io_vector = VECTOR_SMI;
|
|
|
|
io->io_pins[pin].io_masked = 0;
|
|
|
|
io->io_pins[pin].io_edgetrigger = 1;
|
|
|
|
io->io_pins[pin].io_activehi = 1;
|
|
|
|
if (bootverbose)
|
|
|
|
printf("ioapic%u: Routing SMI -> intpin %d\n",
|
|
|
|
io->io_id, pin);
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ioapic_set_extint(void *cookie, u_int pin)
|
|
|
|
{
|
|
|
|
struct ioapic *io;
|
|
|
|
|
|
|
|
io = (struct ioapic *)cookie;
|
|
|
|
if (pin >= io->io_numintr)
|
|
|
|
return (EINVAL);
|
|
|
|
if (io->io_pins[pin].io_vector < 0)
|
|
|
|
return (EINVAL);
|
|
|
|
io->io_pins[pin].io_vector = VECTOR_EXTINT;
|
|
|
|
io->io_pins[pin].io_masked = 0;
|
|
|
|
io->io_pins[pin].io_edgetrigger = 1;
|
|
|
|
io->io_pins[pin].io_activehi = 1;
|
|
|
|
if (bootverbose)
|
|
|
|
printf("ioapic%u: Routing external 8259A's -> intpin %d\n",
|
|
|
|
io->io_id, pin);
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ioapic_set_polarity(void *cookie, u_int pin, char activehi)
|
|
|
|
{
|
|
|
|
struct ioapic *io;
|
|
|
|
|
|
|
|
io = (struct ioapic *)cookie;
|
|
|
|
if (pin >= io->io_numintr)
|
|
|
|
return (EINVAL);
|
|
|
|
if (io->io_pins[pin].io_vector < 0)
|
|
|
|
return (EINVAL);
|
|
|
|
io->io_pins[pin].io_activehi = activehi;
|
|
|
|
if (bootverbose)
|
|
|
|
printf("ioapic%u: intpin %d polarity: %s\n", io->io_id, pin,
|
|
|
|
activehi ? "active-hi" : "active-lo");
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
ioapic_set_triggermode(void *cookie, u_int pin, char edgetrigger)
|
|
|
|
{
|
|
|
|
struct ioapic *io;
|
|
|
|
|
|
|
|
io = (struct ioapic *)cookie;
|
|
|
|
if (pin >= io->io_numintr)
|
|
|
|
return (EINVAL);
|
|
|
|
if (io->io_pins[pin].io_vector < 0)
|
|
|
|
return (EINVAL);
|
|
|
|
io->io_pins[pin].io_edgetrigger = edgetrigger;
|
|
|
|
if (bootverbose)
|
|
|
|
printf("ioapic%u: intpin %d trigger: %s\n", io->io_id, pin,
|
|
|
|
edgetrigger ? "edge" : "level");
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Register a complete I/O APIC object with the interrupt subsystem.
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
ioapic_register(void *cookie)
|
|
|
|
{
|
|
|
|
struct ioapic_intsrc *pin;
|
|
|
|
struct ioapic *io;
|
|
|
|
volatile ioapic_t *apic;
|
|
|
|
uint32_t flags;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
io = (struct ioapic *)cookie;
|
|
|
|
apic = io->io_addr;
|
|
|
|
mtx_lock_spin(&icu_lock);
|
|
|
|
flags = ioapic_read(apic, IOAPIC_VER) & IOART_VER_VERSION;
|
|
|
|
STAILQ_INSERT_TAIL(&ioapic_list, io, io_next);
|
|
|
|
mtx_unlock_spin(&icu_lock);
|
2003-11-04 19:22:20 +00:00
|
|
|
printf("ioapic%u <Version %u.%u> irqs %u-%u on motherboard\n",
|
|
|
|
io->io_id, flags >> 4, flags & 0xf, io->io_intbase,
|
|
|
|
io->io_intbase + io->io_numintr - 1);
|
2003-11-03 21:53:38 +00:00
|
|
|
for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++) {
|
|
|
|
/*
|
|
|
|
* Finish initializing the pins by programming the vectors
|
|
|
|
* and delivery mode.
|
|
|
|
*/
|
|
|
|
if (pin->io_vector == VECTOR_DISABLED)
|
|
|
|
continue;
|
|
|
|
flags = IOART_DESTPHY;
|
|
|
|
if (pin->io_edgetrigger)
|
|
|
|
flags |= IOART_TRGREDG;
|
|
|
|
else
|
|
|
|
flags |= IOART_TRGRLVL;
|
|
|
|
if (pin->io_activehi)
|
|
|
|
flags |= IOART_INTAHI;
|
|
|
|
else
|
|
|
|
flags |= IOART_INTALO;
|
|
|
|
if (pin->io_masked)
|
|
|
|
flags |= IOART_INTMSET;
|
|
|
|
switch (pin->io_vector) {
|
|
|
|
case VECTOR_EXTINT:
|
|
|
|
KASSERT(pin->io_edgetrigger,
|
|
|
|
("EXTINT not edge triggered"));
|
|
|
|
flags |= IOART_DELEXINT;
|
|
|
|
break;
|
|
|
|
case VECTOR_NMI:
|
|
|
|
KASSERT(pin->io_edgetrigger,
|
|
|
|
("NMI not edge triggered"));
|
|
|
|
flags |= IOART_DELNMI;
|
|
|
|
break;
|
|
|
|
case VECTOR_SMI:
|
|
|
|
KASSERT(pin->io_edgetrigger,
|
|
|
|
("SMI not edge triggered"));
|
|
|
|
flags |= IOART_DELSMI;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
flags |= IOART_DELLOPRI |
|
|
|
|
apic_irq_to_idt(pin->io_vector);
|
|
|
|
}
|
|
|
|
mtx_lock_spin(&icu_lock);
|
|
|
|
ioapic_write(apic, IOAPIC_REDTBL_LO(i), flags);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Route interrupts to the BSP by default using physical
|
|
|
|
* addressing. Vectored interrupts get readdressed using
|
|
|
|
* logical IDs to CPU clusters when they are enabled.
|
|
|
|
*/
|
|
|
|
flags = ioapic_read(apic, IOAPIC_REDTBL_HI(i));
|
|
|
|
flags &= ~IOART_DEST;
|
|
|
|
flags |= PCPU_GET(apic_id) << APIC_ID_SHIFT;
|
|
|
|
ioapic_write(apic, IOAPIC_REDTBL_HI(i), flags);
|
|
|
|
mtx_unlock_spin(&icu_lock);
|
|
|
|
if (pin->io_vector >= 0) {
|
|
|
|
#ifdef MIXED_MODE
|
|
|
|
/* Route IRQ0 via the 8259A using mixed mode. */
|
|
|
|
if (pin->io_vector == 0)
|
|
|
|
ioapic_setup_mixed_mode(pin);
|
|
|
|
else
|
|
|
|
#endif
|
|
|
|
intr_register_source(&pin->io_intsrc);
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Program all the intpins to use logical destinations once the AP's
|
|
|
|
* have been launched.
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
ioapic_set_logical_destinations(void *arg __unused)
|
|
|
|
{
|
|
|
|
struct ioapic *io;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
program_logical_dest = 1;
|
|
|
|
STAILQ_FOREACH(io, &ioapic_list, io_next)
|
|
|
|
for (i = 0; i < io->io_numintr; i++)
|
|
|
|
if (io->io_pins[i].io_dest != DEST_NONE &&
|
|
|
|
io->io_pins[i].io_dest != DEST_EXTINT)
|
|
|
|
ioapic_program_destination(&io->io_pins[i]);
|
|
|
|
}
|
|
|
|
SYSINIT(ioapic_destinations, SI_SUB_SMP, SI_ORDER_SECOND,
|
|
|
|
ioapic_set_logical_destinations, NULL)
|
|
|
|
|
|
|
|
#ifdef MIXED_MODE
|
|
|
|
/*
|
|
|
|
* Support for mixed-mode interrupt sources. These sources route an ISA
|
|
|
|
* IRQ through the 8259A's via the ExtINT on pin 0 of the I/O APIC that
|
|
|
|
* routes the ISA interrupts. We just ignore the intpins that use this
|
|
|
|
* mode and allow the atpic driver to register its interrupt source for
|
|
|
|
* that IRQ instead.
|
|
|
|
*/
|
|
|
|
|
|
|
|
void
|
|
|
|
ioapic_setup_mixed_mode(struct ioapic_intsrc *intpin)
|
|
|
|
{
|
|
|
|
struct ioapic_intsrc *extint;
|
|
|
|
struct ioapic *io;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Mark the associated I/O APIC intpin as being delivered via
|
|
|
|
* ExtINT and enable the ExtINT pin on the I/O APIC if needed.
|
|
|
|
*/
|
|
|
|
intpin->io_dest = DEST_EXTINT;
|
|
|
|
io = (struct ioapic *)intpin->io_intsrc.is_pic;
|
|
|
|
extint = &io->io_pins[0];
|
|
|
|
if (extint->io_vector != VECTOR_EXTINT)
|
|
|
|
panic("Can't find ExtINT pin to route through!");
|
|
|
|
#ifdef ENABLE_EXTINT_LOGICAL_DESTINATION
|
|
|
|
if (extint->io_dest == DEST_NONE)
|
|
|
|
ioapic_assign_cluster(extint);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* MIXED_MODE */
|