386 lines
14 KiB
C
386 lines
14 KiB
C
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/*-
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* Copyright (c) 2008 Stanislav Sedov <stas@FreeBSD.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Master configuration register
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*/
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#define AE_MASTER_REG 0x1400
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#define AE_MASTER_SOFT_RESET 0x1 /* Reset adapter. */
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#define AE_MASTER_MTIMER_EN 0x2 /* Unknown. */
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#define AE_MASTER_IMT_EN 0x4 /* Interrupt moderation timer enable. */
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#define AE_MASTER_MANUAL_INT 0x8 /* Software manual interrupt. */
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#define AE_MASTER_REVNUM_SHIFT 16 /* Chip revision number. */
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#define AE_MASTER_REVNUM_MASK 0xff
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#define AE_MASTER_DEVID_SHIFT 24 /* PCI device id. */
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#define AE_MASTER_DEVID_MASK 0xff
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/*
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* Interrupt status register
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*/
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#define AE_ISR_REG 0x1600
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#define AE_ISR_TIMER 0x00000001 /* Counter expired. */
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#define AE_ISR_MANUAL 0x00000002 /* Manual interrupt occuried. */
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#define AE_ISR_RXF_OVERFLOW 0x00000004 /* RxF overflow occuried. */
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#define AE_ISR_TXF_UNDERRUN 0x00000008 /* TxF underrun occuried. */
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#define AE_ISR_TXS_OVERFLOW 0x00000010 /* TxS overflow occuried. */
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#define AE_ISR_RXS_OVERFLOW 0x00000020 /* Internal RxS ring overflow. */
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#define AE_ISR_LINK_CHG 0x00000040 /* Link state changed. */
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#define AE_ISR_TXD_UNDERRUN 0x00000080 /* TxD underrun occuried. */
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#define AE_ISR_RXD_OVERFLOW 0x00000100 /* RxD overflow occuried. */
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#define AE_ISR_DMAR_TIMEOUT 0x00000200 /* DMA read timeout. */
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#define AE_ISR_DMAW_TIMEOUT 0x00000400 /* DMA write timeout. */
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#define AE_ISR_PHY 0x00000800 /* PHY interrupt. */
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#define AE_ISR_TXS_UPDATED 0x00010000 /* Tx status updated. */
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#define AE_ISR_RXD_UPDATED 0x00020000 /* Rx status updated. */
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#define AE_ISR_TX_EARLY 0x00040000 /* TxMAC started transmit. */
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#define AE_ISR_FIFO_UNDERRUN 0x01000000 /* FIFO underrun. */
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#define AE_ISR_FRAME_ERROR 0x02000000 /* Frame receive error. */
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#define AE_ISR_FRAME_SUCCESS 0x04000000 /* Frame receive success. */
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#define AE_ISR_CRC_ERROR 0x08000000 /* CRC error occuried. */
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#define AE_ISR_PHY_LINKDOWN 0x10000000 /* PHY link down. */
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#define AE_ISR_DISABLE 0x80000000 /* Disable interrupts. */
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#define AE_ISR_TX_EVENT (AE_ISR_TXF_UNDERRUN | AE_ISR_TXS_OVERFLOW | \
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AE_ISR_TXD_UNDERRUN | AE_ISR_TXS_UPDATED | \
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AE_ISR_TX_EARLY)
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#define AE_ISR_RX_EVENT (AE_ISR_RXF_OVERFLOW | AE_ISR_RXS_OVERFLOW | \
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AE_ISR_RXD_OVERFLOW | AE_ISR_RXD_UPDATED)
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/* Interrupt mask register. */
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#define AE_IMR_REG 0x1604
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#define AE_IMR_DEFAULT (AE_ISR_DMAR_TIMEOUT | AE_ISR_DMAW_TIMEOUT | \
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AE_ISR_PHY_LINKDOWN | \
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AE_ISR_TXS_UPDATED | AE_ISR_RXD_UPDATED )
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/*
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* Ethernet address register.
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*/
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#define AE_EADDR0_REG 0x1488 /* 5 - 2 bytes */
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#define AE_EADDR1_REG 0x148c /* 1 - 0 bytes */
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/*
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* Desriptor rings registers.
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* L2 supports 64-bit addressing but all rings base addresses
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* should have the same high 32 bits of address.
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*/
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#define AE_DESC_ADDR_HI_REG 0x1540 /* High 32 bits of ring base address. */
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#define AE_RXD_ADDR_LO_REG 0x1554 /* Low 32 bits of RxD ring address. */
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#define AE_TXD_ADDR_LO_REG 0x1544 /* Low 32 bits of TxD ring address. */
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#define AE_TXS_ADDR_LO_REG 0x154c /* Low 32 bits of TxS ring address. */
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#define AE_RXD_COUNT_REG 0x1558 /* Number of RxD descriptors in ring.
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Should be 120-byte aligned (i.e.
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the 'data' field of RxD should
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have 128-byte alignment). */
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#define AE_TXD_BUFSIZE_REG 0x1548 /* Size of TxD ring in 4-byte units.
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Should be 4-byte aligned. */
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#define AE_TXS_COUNT_REG 0x1550 /* Number of TxS descriptors in ring.
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4 byte alignment. */
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#define AE_RXD_COUNT_MIN 16
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#define AE_RXD_COUNT_MAX 512
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#define AE_RXD_COUNT_DEFAULT 64
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#define AE_TXD_BUFSIZE_MIN 4096
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#define AE_TXD_BUFSIZE_MAX 65536
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#define AE_TXD_BUFSIZE_DEFAULT 8192
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#define AE_TXS_COUNT_MIN 8 /* Not sure. */
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#define AE_TXS_COUNT_MAX 160
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#define AE_TXS_COUNT_DEFAULT 64 /* AE_TXD_BUFSIZE_DEFAULT / 128 */
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/*
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* Inter-frame gap configuration register.
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*/
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#define AE_IFG_REG 0x1484
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#define AE_IFG_TXIPG_DEFAULT 0x60 /* 96-bit IFG time. */
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#define AE_IFG_TXIPG_SHIFT 0
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#define AE_IFG_TXIPG_MASK 0x7f
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#define AE_IFG_RXIPG_DEFAULT 0x50 /* 80-bit IFG time. */
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#define AE_IFG_RXIPG_SHIFT 8
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#define AE_IFG_RXIPG_MASK 0xff00
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#define AE_IFG_IPGR1_DEFAULT 0x40 /* Carrier-sense window. */
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#define AE_IFG_IPGR1_SHIFT 16
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#define AE_IFG_IPGR1_MASK 0x7f0000
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#define AE_IFG_IPGR2_DEFAULT 0x60 /* IFG window. */
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#define AE_IFG_IPGR2_SHIFT 24
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#define AE_IFG_IPGR2_MASK 0x7f000000
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/*
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* Half-duplex mode configuration register.
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*/
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#define AE_HDPX_REG 0x1498
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/* Collision window. */
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#define AE_HDPX_LCOL_SHIFT 0
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#define AE_HDPX_LCOL_MASK 0x000003ff
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#define AE_HDPX_LCOL_DEFAULT 0x37
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/* Max retransmission time, after that the packet will be discarded. */
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#define AE_HDPX_RETRY_SHIFT 12
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#define AE_HDPX_RETRY_MASK 0x0000f000
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#define AE_HDPX_RETRY_DEFAULT 0x0f
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/* Alternative binary exponential back-off time. */
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#define AE_HDPX_ABEBT_SHIFT 20
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#define AE_HDPX_ABEBT_MASK 0x00f00000
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#define AE_HDPX_ABEBT_DEFAULT 0x0a
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/* IFG to start JAM for collision based flow control (8-bit time units).*/
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#define AE_HDPX_JAMIPG_SHIFT 24
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#define AE_HDPX_JAMIPG_MASK 0x0f000000
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#define AE_HDPX_JAMIPG_DEFAULT 0x07
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/* Allow the transmission of a packet which has been excessively deferred. */
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#define AE_HDPX_EXC_EN 0x00010000
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/* No back-off on collision, immediately start the retransmission. */
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#define AE_HDPX_NO_BACK_C 0x00020000
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/* No back-off on backpressure, immediately start the transmission. */
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#define AE_HDPX_NO_BACK_P 0x00040000
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/* Alternative binary exponential back-off enable. */
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#define AE_HDPX_ABEBE 0x00080000
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/*
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* Interrupt moderation timer configuration register.
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*/
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#define AE_IMT_REG 0x1408 /* Timer value in 2 us units. */
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#define AE_IMT_MAX 65000
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#define AE_IMT_MIN 50
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#define AE_IMT_DEFAULT 100 /* 200 microseconds. */
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/*
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* Interrupt clearing timer configuration register.
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*/
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#define AE_ICT_REG 0x140e /* Maximum time allowed to clear
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interrupt. In 2 us units. */
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#define AE_ICT_DEFAULT 50000 /* 100ms */
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/*
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* MTU configuration register.
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*/
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#define AE_MTU_REG 0x149c /* MTU size in bytes. */
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/*
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* Cut-through configuration register.
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*/
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#define AE_CUT_THRESH_REG 0x1590 /* Cut-through threshold in unknown units. */
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#define AE_CUT_THRESH_DEFAULT 0x177
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/*
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* Flow-control configuration registers.
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*/
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#define AE_FLOW_THRESH_HI_REG 0x15a8 /* High watermark of RxD
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overflow threshold. */
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#define AE_FLOW_THRESH_LO_REG 0x15aa /* Lower watermark of RxD
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overflow threshold */
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/*
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* Mailbox configuration registers.
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*/
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#define AE_MB_TXD_IDX_REG 0x15f0 /* TxD read index. */
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#define AE_MB_RXD_IDX_REG 0x15f4 /* RxD write index. */
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/*
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* DMA configuration registers.
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*/
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#define AE_DMAREAD_REG 0x1580 /* Read DMA configuration register. */
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#define AE_DMAREAD_EN 1
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#define AE_DMAWRITE_REG 0x15a0 /* Write DMA configuration register. */
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#define AE_DMAWRITE_EN 1
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/*
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* MAC configuration register.
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*/
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#define AE_MAC_REG 0x1480
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#define AE_MAC_TX_EN 0x00000001 /* Enable transmit. */
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#define AE_MAC_RX_EN 0x00000002 /* Enable receive. */
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#define AE_MAC_TX_FLOW_EN 0x00000004 /* Enable Tx flow control. */
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#define AE_MAC_RX_FLOW_EN 0x00000008 /* Enable Rx flow control. */
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#define AE_MAC_LOOPBACK 0x00000010 /* Loopback at MII. */
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#define AE_MAC_FULL_DUPLEX 0x00000020 /* Enable full-duplex. */
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#define AE_MAC_TX_CRC_EN 0x00000040 /* Enable CRC generation. */
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#define AE_MAC_TX_AUTOPAD 0x00000080 /* Pad short frames. */
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#define AE_MAC_PREAMBLE_MASK 0x00003c00 /* Preamble length. */
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#define AE_MAC_PREAMBLE_SHIFT 10
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#define AE_MAC_PREAMBLE_DEFAULT 0x07 /* By standard. */
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#define AE_MAC_RMVLAN_EN 0x00004000 /* Remove VLAN tags in
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incoming packets. */
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#define AE_MAC_PROMISC_EN 0x00008000 /* Enable promiscue mode. */
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#define AE_MAC_TX_MAXBACKOFF 0x00100000 /* Unknown. */
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#define AE_MAC_MCAST_EN 0x02000000 /* Pass all multicast frames. */
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#define AE_MAC_BCAST_EN 0x04000000 /* Pass all broadcast frames. */
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#define AE_MAC_CLK_PHY 0x08000000 /* If 1 uses loopback clock
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PHY, if 0 - system clock. */
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#define AE_HALFBUF_MASK 0xf0000000 /* Half-duplex retry buffer. */
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#define AE_HALFBUF_SHIFT 28
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#define AE_HALFBUF_DEFAULT 2 /* XXX: From Linux. */
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/*
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* MDIO control register.
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*/
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#define AE_MDIO_REG 0x1414
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#define AE_MDIO_DATA_MASK 0xffff
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#define AE_MDIO_DATA_SHIFT 0
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#define AE_MDIO_REGADDR_MASK 0x1f0000
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#define AE_MDIO_REGADDR_SHIFT 16
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#define AE_MDIO_READ 0x00200000 /* Read operation. */
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#define AE_MDIO_SUP_PREAMBLE 0x00400000 /* Suppress preamble. */
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#define AE_MDIO_START 0x00800000 /* Initiate MDIO transfer. */
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#define AE_MDIO_CLK_SHIFT 24 /* Clock selection. */
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#define AE_MDIO_CLK_MASK 0x07000000 /* Clock selection. */
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#define AE_MDIO_CLK_25_4 0 /* Dividers? */
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#define AE_MDIO_CLK_25_6 2
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#define AE_MDIO_CLK_25_8 3
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#define AE_MDIO_CLK_25_10 4
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#define AE_MDIO_CLK_25_14 5
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#define AE_MDIO_CLK_25_20 6
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#define AE_MDIO_CLK_25_28 7
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#define AE_MDIO_BUSY 0x08000000 /* MDIO is busy. */
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/*
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* Idle status register.
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*/
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#define AE_IDLE_REG 0x1410
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/*
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* Idle status bits.
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* If bit is set then the corresponding module is in non-idle state.
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*/
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#define AE_IDLE_RXMAC 1
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#define AE_IDLE_TXMAC 2
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#define AE_IDLE_DMAREAD 8
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#define AE_IDLE_DMAWRITE 4
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/*
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* Multicast hash tables registers.
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*/
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#define AE_REG_MHT0 0x1490
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#define AE_REG_MHT1 0x1494
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/*
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* Wake on lan (WOL).
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*/
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#define AE_WOL_REG 0x14a0
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#define AE_WOL_MAGIC 0x00000004
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#define AE_WOL_MAGIC_PME 0x00000008
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#define AE_WOL_LNKCHG 0x00000010
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#define AE_WOL_LNKCHG_PME 0x00000020
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/*
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* PCIE configuration registers. Descriptions unknown.
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*/
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#define AE_PCIE_LTSSM_TESTMODE_REG 0x12fc
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#define AE_PCIE_LTSSM_TESTMODE_DEFAULT 0x6500
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#define AE_PCIE_DLL_TX_CTRL_REG 0x1104
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#define AE_PCIE_DLL_TX_CTRL_SEL_NOR_CLK 0x0400
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#define AE_PCIE_DLL_TX_CTRL_DEFAULT 0x0568
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#define AE_PCIE_PHYMISC_REG 0x1000
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#define AE_PCIE_PHYMISC_FORCE_RCV_DET 0x4
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/*
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* PHY enable register.
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*/
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#define AE_PHY_ENABLE_REG 0x140c
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#define AE_PHY_ENABLE 1
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/*
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* VPD registers.
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*/
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#define AE_VPD_CAP_REG 0x6c /* Command register. */
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#define AE_VPD_CAP_ID_MASK 0xff
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#define AE_VPD_CAP_ID_SHIFT 0
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#define AE_VPD_CAP_NEXT_MASK 0xff00
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#define AE_VPD_CAP_NEXT_SHIFT 8
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||
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#define AE_VPD_CAP_ADDR_MASK 0x7fff0000
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||
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#define AE_VPD_CAP_ADDR_SHIFT 16
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||
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#define AE_VPD_CAP_DONE 0x80000000
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||
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||
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#define AE_VPD_DATA_REG 0x70 /* Data register. */
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||
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||
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#define AE_VPD_NREGS 64 /* Maximum number of VPD regs. */
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||
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#define AE_VPD_SIG_MASK 0xff
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||
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#define AE_VPD_SIG 0x5a /* VPD block signature. */
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||
|
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#define AE_VPD_REG_SHIFT 16 /* Register id offset. */
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||
|
|
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||
|
|
/*
|
||
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|
* SPI registers.
|
||
|
|
*/
|
||
|
|
#define AE_SPICTL_REG 0x200
|
||
|
|
#define AE_SPICTL_VPD_EN 0x2000 /* Enable VPD. */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* PHY-specific registers constants.
|
||
|
|
*/
|
||
|
|
#define AE_PHY_DBG_ADDR 0x1d
|
||
|
|
#define AE_PHY_DBG_DATA 0x1e
|
||
|
|
#define AE_PHY_DBG_POWERSAVE 0x1000
|
||
|
|
|
||
|
|
/*
|
||
|
|
* TxD flags.
|
||
|
|
*/
|
||
|
|
#define AE_TXD_INSERT_VTAG 0x8000 /* Insert VLAN tag on transfer. */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* TxS flags.
|
||
|
|
*/
|
||
|
|
#define AE_TXS_SUCCESS 0x0001 /* Packed transmitted successfully. */
|
||
|
|
#define AE_TXS_BCAST 0x0002 /* Transmitted broadcast frame. */
|
||
|
|
#define AE_TXS_MCAST 0x0004 /* Transmitted multicast frame. */
|
||
|
|
#define AE_TXS_PAUSE 0x0008 /* Transmitted pause frame. */
|
||
|
|
#define AE_TXS_CTRL 0x0010 /* Transmitted control frame. */
|
||
|
|
#define AE_TXS_DEFER 0x0020 /* Frame transmitted with defer. */
|
||
|
|
#define AE_TXS_EXCDEFER 0x0040 /* Excessive collision. */
|
||
|
|
#define AE_TXS_SINGLECOL 0x0080 /* Single collision occuried. */
|
||
|
|
#define AE_TXS_MULTICOL 0x0100 /* Multiple collisions occuried. */
|
||
|
|
#define AE_TXS_LATECOL 0x0200 /* Late collision occuried. */
|
||
|
|
#define AE_TXS_ABORTCOL 0x0400 /* Frame abort due to collisions. */
|
||
|
|
#define AE_TXS_UNDERRUN 0x0800 /* Tx SRAM underrun occuried. */
|
||
|
|
#define AE_TXS_UPDATE 0x8000
|
||
|
|
|
||
|
|
/*
|
||
|
|
* RxD flags.
|
||
|
|
*/
|
||
|
|
#define AE_RXD_SUCCESS 0x0001
|
||
|
|
#define AE_RXD_BCAST 0x0002 /* Broadcast frame received. */
|
||
|
|
#define AE_RXD_MCAST 0x0004 /* Multicast frame received. */
|
||
|
|
#define AE_RXD_PAUSE 0x0008 /* Pause frame received. */
|
||
|
|
#define AE_RXD_CTRL 0x0010 /* Control frame received. */
|
||
|
|
#define AE_RXD_CRCERR 0x0020 /* Invalid frame CRC. */
|
||
|
|
#define AE_RXD_CODEERR 0x0040 /* Invalid frame opcode. */
|
||
|
|
#define AE_RXD_RUNT 0x0080 /* Runt frame received. */
|
||
|
|
#define AE_RXD_FRAG 0x0100 /* Collision fragment received. */
|
||
|
|
#define AE_RXD_TRUNC 0x0200 /* The frame was truncated due
|
||
|
|
to Rx SRAM underrun. */
|
||
|
|
#define AE_RXD_ALIGN 0x0400 /* Frame alignment error. */
|
||
|
|
#define AE_RXD_HAS_VLAN 0x0800 /* VLAN tag present. */
|
||
|
|
#define AE_RXD_UPDATE 0x8000
|