253 lines
9.6 KiB
Markdown
253 lines
9.6 KiB
Markdown
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;; Scheduling description for UltraSPARC-I/II.
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;; Copyright (C) 2002 Free Software Foundation, Inc.
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;;
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;; This file is part of GNU CC.
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;;
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;; GNU CC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 2, or (at your option)
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;; any later version.
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;;
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;; GNU CC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GNU CC; see the file COPYING. If not, write to
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;; the Free Software Foundation, 59 Temple Place - Suite 330,
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;; Boston, MA 02111-1307, USA.
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;; UltraSPARC-I and II are quad-issue processors. Interesting features
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;; to note:
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;;
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;; - Buffered loads, they can queue waiting for the actual data until
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;; an instruction actually tries to reference the destination register
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;; as an input
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;; - Two integer units. Only one of them can do shifts, and the other
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;; is the only one which may do condition code setting instructions.
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;; Complicating things further, a shift may go only into the first
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;; slot in a dispatched group. And if you have a non-condition code
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;; setting instruction and one that does set the condition codes. The
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;; former must be issued first in order for both of them to issue.
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;; - Stores can issue before the value being stored is available. As long
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;; as the input data becomes ready before the store is to move out of the
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;; store buffer, it will not cause a stall.
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;; - Branches may issue in the same cycle as an instruction setting the
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;; condition codes being tested by that branch. This does not apply
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;; to floating point, only integer.
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(define_automaton "ultrasparc_0,ultrasparc_1")
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(define_cpu_unit "us1_fdivider,us1_fpm" "ultrasparc_0");
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(define_cpu_unit "us1_fpa,us1_load_writeback" "ultrasparc_1")
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(define_cpu_unit "us1_fps_0,us1_fps_1,us1_fpd_0,us1_fpd_1" "ultrasparc_1")
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(define_cpu_unit "us1_slot0,us1_slot1,us1_slot2,us1_slot3" "ultrasparc_1")
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(define_cpu_unit "us1_ieu0,us1_ieu1,us1_cti,us1_lsu" "ultrasparc_1")
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(define_reservation "us1_slot012" "(us1_slot0 | us1_slot1 | us1_slot2)")
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(define_reservation "us1_slotany" "(us1_slot0 | us1_slot1 | us1_slot2 | us1_slot3)")
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(define_reservation "us1_single_issue" "us1_slot0 + us1_slot1 + us1_slot2 + us1_slot3")
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(define_reservation "us1_fp_single" "(us1_fps_0 | us1_fps_1)")
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(define_reservation "us1_fp_double" "(us1_fpd_0 | us1_fpd_1)")
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;; This is a simplified representation of the issue at hand.
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;; For most cases, going from one FP precision type insn to another
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;; just breaks up the insn group. However for some cases, such
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;; a situation causes the second insn to stall 2 more cycles.
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(exclusion_set "us1_fps_0,us1_fps_1" "us1_fpd_0,us1_fpd_1")
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;; If we have to schedule an ieu1 specific instruction and we want
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;; to reserve the ieu0 unit as well, we must reserve it first. So for
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;; example we could not schedule this sequence:
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;; COMPARE IEU1
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;; IALU IEU0
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;; but we could schedule them together like this:
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;; IALU IEU0
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;; COMPARE IEU1
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;; This basically requires that ieu0 is reserved before ieu1 when
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;; it is required that both be reserved.
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(absence_set "us1_ieu0" "us1_ieu1")
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;; This defines the slotting order. Most IEU instructions can only
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;; execute in the first three slots, FPU and branches can go into
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;; any slot. We represent instructions which "break the group"
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;; as requiring reservation of us1_slot0.
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(absence_set "us1_slot0" "us1_slot1,us1_slot2,us1_slot3")
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(absence_set "us1_slot1" "us1_slot2,us1_slot3")
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(absence_set "us1_slot2" "us1_slot3")
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(define_insn_reservation "us1_single" 1
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(and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "multi,flushw,iflush,trap"))
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"us1_single_issue")
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(define_insn_reservation "us1_simple_ieuN" 1
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(and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "ialu"))
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"(us1_ieu0 | us1_ieu1) + us1_slot012")
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(define_insn_reservation "us1_simple_ieu0" 1
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(and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "shift"))
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"us1_ieu0 + us1_slot012")
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(define_insn_reservation "us1_simple_ieu1" 1
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(and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "compare"))
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"us1_ieu1 + us1_slot012")
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(define_insn_reservation "us1_ialuX" 1
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(and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "ialuX"))
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"us1_single_issue")
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(define_insn_reservation "us1_cmove" 2
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(and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "cmove"))
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"us1_single_issue, nothing")
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(define_insn_reservation "us1_imul" 1
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(and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "imul"))
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"us1_single_issue")
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(define_insn_reservation "us1_idiv" 1
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(and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "idiv"))
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"us1_single_issue")
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;; For loads, the "delayed return mode" behavior of the chip
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;; is represented using the us1_load_writeback resource.
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(define_insn_reservation "us1_load" 2
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(and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "load,fpload"))
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"us1_lsu + us1_slot012, us1_load_writeback")
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(define_insn_reservation "us1_load_signed" 3
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(and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "sload"))
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"us1_lsu + us1_slot012, nothing, us1_load_writeback")
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(define_insn_reservation "us1_store" 1
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(and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "store,fpstore"))
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"us1_lsu + us1_slot012")
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(define_insn_reservation "us1_branch" 1
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(and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "branch"))
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"us1_cti + us1_slotany")
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(define_insn_reservation "us1_call_jmpl" 1
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(and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch"))
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"us1_cti + us1_ieu1 + us1_slot0")
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(define_insn_reservation "us1_fmov_single" 1
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(and (and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "fpmove"))
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(eq_attr "fptype" "single"))
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"us1_fpa + us1_fp_single + us1_slotany")
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(define_insn_reservation "us1_fmov_double" 1
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(and (and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "fpmove"))
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(eq_attr "fptype" "double"))
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"us1_fpa + us1_fp_double + us1_slotany")
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(define_insn_reservation "us1_fcmov_single" 2
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(and (and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "fpcmove,fpcrmove"))
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(eq_attr "fptype" "single"))
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"us1_fpa + us1_fp_single + us1_slotany, nothing")
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(define_insn_reservation "us1_fcmov_double" 2
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(and (and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "fpcmove,fpcrmove"))
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(eq_attr "fptype" "double"))
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"us1_fpa + us1_fp_double + us1_slotany, nothing")
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(define_insn_reservation "us1_faddsub_single" 4
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(and (and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "fp"))
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(eq_attr "fptype" "single"))
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"us1_fpa + us1_fp_single + us1_slotany, nothing*3")
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(define_insn_reservation "us1_faddsub_double" 4
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(and (and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "fp"))
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(eq_attr "fptype" "double"))
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"us1_fpa + us1_fp_double + us1_slotany, nothing*3")
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(define_insn_reservation "us1_fpcmp_single" 1
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(and (and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "fpcmp"))
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(eq_attr "fptype" "single"))
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"us1_fpa + us1_fp_single + us1_slotany")
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(define_insn_reservation "us1_fpcmp_double" 1
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(and (and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "fpcmp"))
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(eq_attr "fptype" "double"))
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"us1_fpa + us1_fp_double + us1_slotany")
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(define_insn_reservation "us1_fmult_single" 4
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(and (and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "fpmul"))
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(eq_attr "fptype" "single"))
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"us1_fpm + us1_fp_single + us1_slotany, nothing*3")
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(define_insn_reservation "us1_fmult_double" 4
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(and (and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "fpmul"))
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(eq_attr "fptype" "double"))
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"us1_fpm + us1_fp_double + us1_slotany, nothing*3")
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;; This is actually in theory dangerous, because it is possible
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;; for the chip to prematurely dispatch the dependent instruction
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;; in the G stage, resulting in a 9 cycle stall. However I have never
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;; been able to trigger this case myself even with hand written code,
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;; so it must require some rare complicated pipeline state.
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(define_bypass 3
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"us1_faddsub_single,us1_faddsub_double,us1_fmult_single,us1_fmult_double"
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"us1_faddsub_single,us1_faddsub_double,us1_fmult_single,us1_fmult_double")
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;; Floating point divide and square root use the multiplier unit
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;; for final rounding 3 cycles before the divide/sqrt is complete.
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(define_insn_reservation "us1_fdivs"
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13
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(and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "fpdivs,fpsqrts"))
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"(us1_fpm + us1_fdivider + us1_slot0), us1_fdivider*8, (us1_fpm + us1_fdivider), us1_fdivider*2"
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)
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(define_bypass
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"us1_fdivs"
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"us1_faddsub_single,us1_faddsub_double,us1_fmult_single,us1_fmult_double")
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(define_insn_reservation "us1_fdivd"
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23
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(and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "fpdivd,fpsqrtd"))
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"(us1_fpm + us1_fdivider + us1_slot0), us1_fdivider*18, (us1_fpm + us1_fdivider), us1_fdivider*2"
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)
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(define_bypass
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22
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"us1_fdivd"
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"us1_faddsub_single,us1_faddsub_double,us1_fmult_single,us1_fmult_double")
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;; Any store may multi issue with the insn creating the source
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;; data as long as that creating insn is not an FPU div/sqrt.
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;; We need a special guard function because this bypass does
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;; not apply to the address inputs of the store.
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(define_bypass 0 "us1_simple_ieuN,us1_simple_ieu1,us1_simple_ieu0,us1_faddsub_single,us1_faddsub_double,us1_fmov_single,us1_fmov_double,us1_fcmov_single,us1_fcmov_double,us1_fmult_single,us1_fmult_double" "us1_store"
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"store_data_bypass_p")
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;; An integer branch may execute in the same cycle as the compare
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;; creating the condition codes.
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(define_bypass 0 "us1_simple_ieu1" "us1_branch")
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