120 lines
4.0 KiB
C
120 lines
4.0 KiB
C
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/* $NetBSD: gtreg.h,v 1.2 2005/12/24 20:07:03 perry Exp $ */
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/*-
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* Copyright (c) 1997, 1998, 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define GT_REGVAL(x) *((volatile u_int32_t *) \
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(MIPS_PHYS_TO_KSEG1(MALTA_CORECTRL_BASE + (x))))
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/* CPU Configuration Register Map */
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#define GT_CPU_INT 0x000
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#define GT_MULTIGT 0x120
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/* CPU Address Decode Register Map */
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/* CPU Error Report Register Map */
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/* CPU Sync Barrier Register Map */
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/* SDRAM and Device Address Decode Register Map */
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/* SDRAM Configuration Register Map */
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/* SDRAM Parameters Register Map */
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/* ECC Register Map */
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/* Device Parameters Register Map */
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/* DMA Record Register Map */
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/* DMA Arbiter Register Map */
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/* Timer/Counter Register Map */
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//#define GT_TC_0 0x850
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//#define GT_TC_1 0x854
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//#define GT_TC_2 0x858
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//#define GT_TC_3 0x85c
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//#define GT_TC_CONTROL 0x864
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/* PCI Internal Register Map */
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#define GT_PCI0_CFG_ADDR 0xcf8
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#define GT_PCI0_CFG_DATA 0xcfc
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#define GT_PCI0_INTR_ACK 0xc34
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/* Interrupts Register Map */
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#define GT_INTR_CAUSE 0xc18
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#define GTIC_INTSUM 0x00000001
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#define GTIC_MEMOUT 0x00000002
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#define GTIC_DMAOUT 0x00000004
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#define GTIC_CPUOUT 0x00000008
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#define GTIC_DMA0COMP 0x00000010
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#define GTIC_DMA1COMP 0x00000020
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#define GTIC_DMA2COMP 0x00000040
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#define GTIC_DMA3COMP 0x00000080
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#define GTIC_T0EXP 0x00000100
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#define GTIC_T1EXP 0x00000200
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#define GTIC_T2EXP 0x00000400
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#define GTIC_T3EXP 0x00000800
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#define GTIC_MASRDERR0 0x00001000
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#define GTIC_SLVWRERR0 0x00002000
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#define GTIC_MASWRERR0 0x00004000
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#define GTIC_SLVRDERR0 0x00008000
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#define GTIC_ADDRERR0 0x00010000
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#define GTIC_MEMERR 0x00020000
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#define GTIC_MASABORT0 0x00040000
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#define GTIC_TARABORT0 0x00080000
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#define GTIC_RETRYCNT0 0x00100000
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#define GTIC_PMCINT_0 0x00200000
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#define GTIC_CPUINT 0x0c300000
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#define GTIC_PCINT 0xc3000000
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#define GTIC_CPUINTSUM 0x40000000
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#define GTIC_PCIINTSUM 0x80000000
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/* PCI Configuration Register Map */
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//#define GT_PCICONFIGBASE 0
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//#define GT_PCIDID BONITO(GT_PCICONFIGBASE + 0x00)
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//#define GT_PCICMD BONITO(GT_PCICONFIGBASE + 0x04)
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//#define GT_PCICLASS BONITO(GT_PCICONFIGBASE + 0x08)
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//#define GT_PCILTIMER BONITO(GT_PCICONFIGBASE + 0x0c)
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//#define GT_PCIBASE0 BONITO(GT_PCICONFIGBASE + 0x10)
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//#define GT_PCIBASE1 BONITO(GT_PCICONFIGBASE + 0x14)
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//#define GT_PCIBASE2 BONITO(GT_PCICONFIGBASE + 0x18)
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//#define GT_PCIEXPRBASE BONITO(GT_PCICONFIGBASE + 0x30)
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//#define GT_PCIINT BONITO(GT_PCICONFIGBASE + 0x3c)
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/* PCI Configuration, Function 1, Register Map */
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/* I2O Support Register Map */
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