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freebsd-dev/sys/mips/nlm/board.h

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Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
/*-
* Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
* reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
Support for EEPROM and CPLD on XLP EVP boards. On XLP evaluation platform, the board information is stored in an I2C eeprom and the network block configuration is available from a CPLD connected to the GBU (NOR flash bus). Add support for both of these.
2012-03-27 12:25:47 +00:00
*
Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
* NETLOGIC_BSD
Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
* $FreeBSD$
MIPS XLP platform code update. * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett
2011-09-05 10:45:29 +00:00
*/
Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
#ifndef __NLM_BOARD_H__
#define __NLM_BOARD_H__
xlpge : driver for XLP network accelerator Features: - network driver for the four 10G interfaces and two management ports on XLP 8xx. - Support 4xx and 3xx variants of the processor. - Source code and firmware building for the 16 mips32r2 micro-code engines in the Network Accelerator. - Basic initialization code for Packet ordering Engine. Submitted by: Prabhath Raman (prabhath at netlogicmicro com) [refactored and fixed up for style by jchandra]
2012-03-27 14:05:12 +00:00
#define XLP_NAE_NBLOCKS 5
#define XLP_NAE_NPORTS 4
Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
Support for EEPROM and CPLD on XLP EVP boards. On XLP evaluation platform, the board information is stored in an I2C eeprom and the network block configuration is available from a CPLD connected to the GBU (NOR flash bus). Add support for both of these.
2012-03-27 12:25:47 +00:00
/*
* EVP board EEPROM info
*/
#define EEPROM_I2CBUS 1
#define EEPROM_I2CADDR 0xAE
#define EEPROM_SIZE 48
#define EEPROM_MACADDR_OFFSET 2
XLP UART code udpate. Move XLP PCI UART device to sys/mips/nlm/dev/ directory. Other drivers for the XLP SoC devices will be added here as well. Update uart_cpu_xlp.c and uart_pci_xlp.c use macros for uart port, speed and IO frequency.
2012-03-27 14:48:40 +00:00
/* used if there is no FDT */
#define BOARD_CONSOLE_SPEED 115200
#define BOARD_CONSOLE_UART 0
xlpge : driver for XLP network accelerator Features: - network driver for the four 10G interfaces and two management ports on XLP 8xx. - Support 4xx and 3xx variants of the processor. - Source code and firmware building for the 16 mips32r2 micro-code engines in the Network Accelerator. - Basic initialization code for Packet ordering Engine. Submitted by: Prabhath Raman (prabhath at netlogicmicro com) [refactored and fixed up for style by jchandra]
2012-03-27 14:05:12 +00:00
/*
* EVP board CPLD chip select and daughter card info field
*/
#define XLP_EVB_CPLD_CHIPSELECT 2
#define DCARD_ILAKEN 0x0
#define DCARD_SGMII 0x1
#define DCARD_XAUI 0x2
#define DCARD_NOT_PRSNT 0x3
Support for EEPROM and CPLD on XLP EVP boards. On XLP evaluation platform, the board information is stored in an I2C eeprom and the network block configuration is available from a CPLD connected to the GBU (NOR flash bus). Add support for both of these.
2012-03-27 12:25:47 +00:00
#if !defined(LOCORE) && !defined(__ASSEMBLY__)
xlpge : driver for XLP network accelerator Features: - network driver for the four 10G interfaces and two management ports on XLP 8xx. - Support 4xx and 3xx variants of the processor. - Source code and firmware building for the 16 mips32r2 micro-code engines in the Network Accelerator. - Basic initialization code for Packet ordering Engine. Submitted by: Prabhath Raman (prabhath at netlogicmicro com) [refactored and fixed up for style by jchandra]
2012-03-27 14:05:12 +00:00
/*
* NAE configuration
*/
Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
struct xlp_port_ivars {
int port;
int block;
xlpge : driver for XLP network accelerator Features: - network driver for the four 10G interfaces and two management ports on XLP 8xx. - Support 4xx and 3xx variants of the processor. - Source code and firmware building for the 16 mips32r2 micro-code engines in the Network Accelerator. - Basic initialization code for Packet ordering Engine. Submitted by: Prabhath Raman (prabhath at netlogicmicro com) [refactored and fixed up for style by jchandra]
2012-03-27 14:05:12 +00:00
int node;
Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
int type;
int phy_addr;
xlpge : driver for XLP network accelerator Features: - network driver for the four 10G interfaces and two management ports on XLP 8xx. - Support 4xx and 3xx variants of the processor. - Source code and firmware building for the 16 mips32r2 micro-code engines in the Network Accelerator. - Basic initialization code for Packet ordering Engine. Submitted by: Prabhath Raman (prabhath at netlogicmicro com) [refactored and fixed up for style by jchandra]
2012-03-27 14:05:12 +00:00
int mdio_bus;
int loopback_mode;
int num_channels;
int free_desc_sizes;
int num_free_descs;
int pseq_fifo_size;
int iface_fifo_size;
int rxbuf_size;
int rx_slots_reqd;
int tx_slots_reqd;
int vlan_pri_en;
int stg2_fifo_size;
int eh_fifo_size;
int frout_fifo_size;
int ms_fifo_size;
int pkt_fifo_size;
int pktlen_fifo_size;
int max_stg2_offset;
int max_eh_offset;
int max_frout_offset;
int max_ms_offset;
int max_pmem_offset;
int stg1_2_credit;
int stg2_eh_credit;
int stg2_frout_credit;
int stg2_ms_credit;
int hw_parser_en;
u_int ieee1588_inc_intg;
u_int ieee1588_inc_den;
u_int ieee1588_inc_num;
uint64_t ieee1588_userval;
uint64_t ieee1588_ptpoff;
uint64_t ieee1588_tmr1;
uint64_t ieee1588_tmr2;
uint64_t ieee1588_tmr3;
Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
};
struct xlp_block_ivars {
int block;
int type;
u_int portmask;
struct xlp_port_ivars port_ivars[XLP_NAE_NPORTS];
};
struct xlp_nae_ivars {
int node;
xlpge : driver for XLP network accelerator Features: - network driver for the four 10G interfaces and two management ports on XLP 8xx. - Support 4xx and 3xx variants of the processor. - Source code and firmware building for the 16 mips32r2 micro-code engines in the Network Accelerator. - Basic initialization code for Packet ordering Engine. Submitted by: Prabhath Raman (prabhath at netlogicmicro com) [refactored and fixed up for style by jchandra]
2012-03-27 14:05:12 +00:00
int nblocks;
Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
u_int blockmask;
xlpge : driver for XLP network accelerator Features: - network driver for the four 10G interfaces and two management ports on XLP 8xx. - Support 4xx and 3xx variants of the processor. - Source code and firmware building for the 16 mips32r2 micro-code engines in the Network Accelerator. - Basic initialization code for Packet ordering Engine. Submitted by: Prabhath Raman (prabhath at netlogicmicro com) [refactored and fixed up for style by jchandra]
2012-03-27 14:05:12 +00:00
u_int xauimask;
u_int sgmiimask;
int freq;
u_int flow_crc_poly;
u_int hw_parser_en;
u_int prepad_en;
u_int prepad_size; /* size in 16 byte units */
u_int ieee_1588_en;
Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
struct xlp_block_ivars block_ivars[XLP_NAE_NBLOCKS];
};
struct xlp_board_info {
u_int nodemask;
struct xlp_node_info {
struct xlp_nae_ivars nae_ivars;
} nodes[XLP_MAX_NODES];
};
xlpge : driver for XLP network accelerator Features: - network driver for the four 10G interfaces and two management ports on XLP 8xx. - Support 4xx and 3xx variants of the processor. - Source code and firmware building for the 16 mips32r2 micro-code engines in the Network Accelerator. - Basic initialization code for Packet ordering Engine. Submitted by: Prabhath Raman (prabhath at netlogicmicro com) [refactored and fixed up for style by jchandra]
2012-03-27 14:05:12 +00:00
extern struct xlp_board_info xlp_board_info;
/* Network configuration */
int nlm_get_vfbid_mapping(int);
int nlm_get_poe_distvec(int vec, uint32_t *distvec);
void xlpge_get_macaddr(uint8_t *macaddr);
Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
int nlm_board_info_setup(void);
xlpge : driver for XLP network accelerator Features: - network driver for the four 10G interfaces and two management ports on XLP 8xx. - Support 4xx and 3xx variants of the processor. - Source code and firmware building for the 16 mips32r2 micro-code engines in the Network Accelerator. - Basic initialization code for Packet ordering Engine. Submitted by: Prabhath Raman (prabhath at netlogicmicro com) [refactored and fixed up for style by jchandra]
2012-03-27 14:05:12 +00:00
/* EEPROM & CPLD */
Support for EEPROM and CPLD on XLP EVP boards. On XLP evaluation platform, the board information is stored in an I2C eeprom and the network block configuration is available from a CPLD connected to the GBU (NOR flash bus). Add support for both of these.
2012-03-27 12:25:47 +00:00
int nlm_board_eeprom_read(int node, int i2cbus, int addr, int offs,
uint8_t *buf,int sz);
uint64_t nlm_board_cpld_base(int node, int chipselect);
int nlm_board_cpld_majorversion(uint64_t cpldbase);
int nlm_board_cpld_minorversion(uint64_t cpldbase);
void nlm_board_cpld_reset(uint64_t cpldbase);
int nlm_board_cpld_dboard_type(uint64_t cpldbase, int slot);
Add MIPS platform files for Netlogic XLP SoC. Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)
2011-07-16 19:35:44 +00:00
#endif
xlpge : driver for XLP network accelerator Features: - network driver for the four 10G interfaces and two management ports on XLP 8xx. - Support 4xx and 3xx variants of the processor. - Source code and firmware building for the 16 mips32r2 micro-code engines in the Network Accelerator. - Basic initialization code for Packet ordering Engine. Submitted by: Prabhath Raman (prabhath at netlogicmicro com) [refactored and fixed up for style by jchandra]
2012-03-27 14:05:12 +00:00
#endif
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