534 lines
13 KiB
Plaintext
534 lines
13 KiB
Plaintext
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/*
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* Copyright (C) 2013 STMicroelectronics (R&D) Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <dt-bindings/clock/stih415-clks.h>
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/ {
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/*
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* Fixed 30MHz oscillator input to SoC
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*/
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clk_sysin: clk-sysin {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <30000000>;
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};
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/*
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* ClockGenAs on SASG1
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*/
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clockgen-a@fee62000 {
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reg = <0xfee62000 0xb48>;
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clk_s_a0_pll: clk-s-a0-pll {
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#clock-cells = <1>;
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compatible = "st,clkgena-plls-c65";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-a0-pll0-hs",
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"clk-s-a0-pll0-ls",
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"clk-s-a0-pll1";
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};
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clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
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#clock-cells = <0>;
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compatible = "st,clkgena-prediv-c65",
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"st,clkgena-prediv";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-a0-osc-prediv";
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};
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clk_s_a0_hs: clk-s-a0-hs {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c65-hs",
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"st,clkgena-divmux";
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clocks = <&clk_s_a0_osc_prediv>,
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<&clk_s_a0_pll 0>, /* PLL0 HS */
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<&clk_s_a0_pll 2>; /* PLL1 */
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clock-output-names = "clk-s-fdma-0",
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"clk-s-fdma-1",
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""; /* clk-s-jit-sense */
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/* Fourth output unused */
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};
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clk_s_a0_ls: clk-s-a0-ls {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c65-ls",
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"st,clkgena-divmux";
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clocks = <&clk_s_a0_osc_prediv>,
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<&clk_s_a0_pll 1>, /* PLL0 LS */
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<&clk_s_a0_pll 2>; /* PLL1 */
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clock-output-names = "clk-s-icn-reg-0",
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"clk-s-icn-if-0",
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"clk-s-icn-reg-lp-0",
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"clk-s-emiss",
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"clk-s-eth1-phy",
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"clk-s-mii-ref-out";
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/* Remaining outputs unused */
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};
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};
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clockgen-a@fee81000 {
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reg = <0xfee81000 0xb48>;
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clk_s_a1_pll: clk-s-a1-pll {
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#clock-cells = <1>;
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compatible = "st,clkgena-plls-c65";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-a1-pll0-hs",
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"clk-s-a1-pll0-ls",
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"clk-s-a1-pll1";
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};
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clk_s_a1_osc_prediv: clk-s-a1-osc-prediv {
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#clock-cells = <0>;
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compatible = "st,clkgena-prediv-c65",
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"st,clkgena-prediv";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-a1-osc-prediv";
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};
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clk_s_a1_hs: clk-s-a1-hs {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c65-hs",
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"st,clkgena-divmux";
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clocks = <&clk_s_a1_osc_prediv>,
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<&clk_s_a1_pll 0>, /* PLL0 HS */
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<&clk_s_a1_pll 2>; /* PLL1 */
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clock-output-names = "", /* Reserved */
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"", /* Reserved */
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"clk-s-stac-phy",
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"clk-s-vtac-tx-phy";
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};
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clk_s_a1_ls: clk-s-a1-ls {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c65-ls",
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"st,clkgena-divmux";
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clocks = <&clk_s_a1_osc_prediv>,
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<&clk_s_a1_pll 1>, /* PLL0 LS */
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<&clk_s_a1_pll 2>; /* PLL1 */
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clock-output-names = "clk-s-icn-if-2",
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"clk-s-card-mmc",
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"clk-s-icn-if-1",
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"clk-s-gmac0-phy",
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"clk-s-nand-ctrl",
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"", /* Reserved */
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"clk-s-mii0-ref-out",
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""; /* clk-s-stac-sys */
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/* Remaining outputs unused */
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};
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};
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/*
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* ClockGenAs on MPE41
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*/
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clockgen-a@fde12000 {
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reg = <0xfde12000 0xb50>;
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clk_m_a0_pll0: clk-m-a0-pll0 {
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#clock-cells = <1>;
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compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-m-a0-pll0-phi0",
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"clk-m-a0-pll0-phi1",
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"clk-m-a0-pll0-phi2",
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"clk-m-a0-pll0-phi3";
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};
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clk_m_a0_pll1: clk-m-a0-pll1 {
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#clock-cells = <1>;
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compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-m-a0-pll1-phi0",
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"clk-m-a0-pll1-phi1",
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"clk-m-a0-pll1-phi2",
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"clk-m-a0-pll1-phi3";
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};
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clk_m_a0_osc_prediv: clk-m-a0-osc-prediv {
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#clock-cells = <0>;
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compatible = "st,clkgena-prediv-c32",
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"st,clkgena-prediv";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-m-a0-osc-prediv";
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};
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clk_m_a0_div0: clk-m-a0-div0 {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c32-odf0",
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"st,clkgena-divmux";
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clocks = <&clk_m_a0_osc_prediv>,
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<&clk_m_a0_pll0 0>, /* PLL0 PHI0 */
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<&clk_m_a0_pll1 0>; /* PLL1 PHI0 */
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clock-output-names = "clk-m-apb-pm", /* Unused */
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"", /* Unused */
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"", /* Unused */
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"", /* Unused */
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"clk-m-pp-dmu-0",
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"clk-m-pp-dmu-1",
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"clk-m-icm-disp",
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""; /* Unused */
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};
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clk_m_a0_div1: clk-m-a0-div1 {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c32-odf1",
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"st,clkgena-divmux";
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clocks = <&clk_m_a0_osc_prediv>,
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<&clk_m_a0_pll0 1>, /* PLL0 PHI1 */
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<&clk_m_a0_pll1 1>; /* PLL1 PHI1 */
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clock-output-names = "", /* Unused */
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"", /* Unused */
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"clk-m-a9-ext2f",
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"clk-m-st40rt",
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"clk-m-st231-dmu-0",
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"clk-m-st231-dmu-1",
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"clk-m-st231-aud",
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"clk-m-st231-gp-0";
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};
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clk_m_a0_div2: clk-m-a0-div2 {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c32-odf2",
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"st,clkgena-divmux";
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clocks = <&clk_m_a0_osc_prediv>,
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<&clk_m_a0_pll0 2>, /* PLL0 PHI2 */
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<&clk_m_a0_pll1 2>; /* PLL1 PHI2 */
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clock-output-names = "clk-m-st231-gp-1",
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"clk-m-icn-cpu",
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"clk-m-icn-stac",
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"clk-m-icn-dmu-0",
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"clk-m-icn-dmu-1",
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"", /* Unused */
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"", /* Unused */
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""; /* Unused */
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};
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clk_m_a0_div3: clk-m-a0-div3 {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c32-odf3",
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"st,clkgena-divmux";
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clocks = <&clk_m_a0_osc_prediv>,
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<&clk_m_a0_pll0 3>, /* PLL0 PHI3 */
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<&clk_m_a0_pll1 3>; /* PLL1 PHI3 */
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clock-output-names = "", /* Unused */
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"", /* Unused */
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"", /* Unused */
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"", /* Unused */
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"", /* Unused */
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"", /* Unused */
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"clk-m-icn-eram",
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"clk-m-a9-trace";
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};
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};
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clockgen-a@fd6db000 {
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reg = <0xfd6db000 0xb50>;
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clk_m_a1_pll0: clk-m-a1-pll0 {
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#clock-cells = <1>;
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compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-m-a1-pll0-phi0",
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"clk-m-a1-pll0-phi1",
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"clk-m-a1-pll0-phi2",
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"clk-m-a1-pll0-phi3";
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};
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clk_m_a1_pll1: clk-m-a1-pll1 {
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#clock-cells = <1>;
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compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-m-a1-pll1-phi0",
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"clk-m-a1-pll1-phi1",
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"clk-m-a1-pll1-phi2",
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"clk-m-a1-pll1-phi3";
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};
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clk_m_a1_osc_prediv: clk-m-a1-osc-prediv {
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#clock-cells = <0>;
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compatible = "st,clkgena-prediv-c32",
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"st,clkgena-prediv";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-m-a1-osc-prediv";
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};
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clk_m_a1_div0: clk-m-a1-div0 {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c32-odf0",
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"st,clkgena-divmux";
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clocks = <&clk_m_a1_osc_prediv>,
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<&clk_m_a1_pll0 0>, /* PLL0 PHI0 */
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<&clk_m_a1_pll1 0>; /* PLL1 PHI0 */
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clock-output-names = "clk-m-fdma-12",
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"clk-m-fdma-10",
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"clk-m-fdma-11",
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"clk-m-hva-lmi",
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"clk-m-proc-sc",
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"clk-m-tp",
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"clk-m-icn-gpu",
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"clk-m-icn-vdp-0";
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};
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clk_m_a1_div1: clk-m-a1-div1 {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c32-odf1",
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"st,clkgena-divmux";
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clocks = <&clk_m_a1_osc_prediv>,
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<&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
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<&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
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clock-output-names = "clk-m-icn-vdp-1",
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"clk-m-icn-vdp-2",
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"clk-m-icn-vdp-3",
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"clk-m-prv-t1-bus",
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"clk-m-icn-vdp-4",
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"clk-m-icn-reg-10",
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"", /* Unused */
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""; /* clk-m-icn-st231 */
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};
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clk_m_a1_div2: clk-m-a1-div2 {
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#clock-cells = <1>;
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compatible = "st,clkgena-divmux-c32-odf2",
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"st,clkgena-divmux";
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clocks = <&clk_m_a1_osc_prediv>,
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<&clk_m_a1_pll0 2>, /* PLL0 PHI2 */
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<&clk_m_a1_pll1 2>; /* PLL1 PHI2 */
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clock-output-names = "clk-m-fvdp-proc-alt",
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"", /* Unused */
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"", /* Unused */
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"", /* Unused */
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"", /* Unused */
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"", /* Unused */
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"", /* Unused */
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""; /* Unused */
|
||
|
|
};
|
||
|
|
|
||
|
|
clk_m_a1_div3: clk-m-a1-div3 {
|
||
|
|
#clock-cells = <1>;
|
||
|
|
compatible = "st,clkgena-divmux-c32-odf3",
|
||
|
|
"st,clkgena-divmux";
|
||
|
|
|
||
|
|
clocks = <&clk_m_a1_osc_prediv>,
|
||
|
|
<&clk_m_a1_pll0 3>, /* PLL0 PHI3 */
|
||
|
|
<&clk_m_a1_pll1 3>; /* PLL1 PHI3 */
|
||
|
|
|
||
|
|
clock-output-names = "", /* Unused */
|
||
|
|
"", /* Unused */
|
||
|
|
"", /* Unused */
|
||
|
|
"", /* Unused */
|
||
|
|
"", /* Unused */
|
||
|
|
"", /* Unused */
|
||
|
|
"", /* Unused */
|
||
|
|
""; /* Unused */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "fixed-factor-clock";
|
||
|
|
clocks = <&clk_m_a0_div1 2>;
|
||
|
|
clock-div = <2>;
|
||
|
|
clock-mult = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
clockgen-a@fd345000 {
|
||
|
|
reg = <0xfd345000 0xb50>;
|
||
|
|
|
||
|
|
clk_m_a2_pll0: clk-m-a2-pll0 {
|
||
|
|
#clock-cells = <1>;
|
||
|
|
compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
|
||
|
|
|
||
|
|
clocks = <&clk_sysin>;
|
||
|
|
|
||
|
|
clock-output-names = "clk-m-a2-pll0-phi0",
|
||
|
|
"clk-m-a2-pll0-phi1",
|
||
|
|
"clk-m-a2-pll0-phi2",
|
||
|
|
"clk-m-a2-pll0-phi3";
|
||
|
|
};
|
||
|
|
|
||
|
|
clk_m_a2_pll1: clk-m-a2-pll1 {
|
||
|
|
#clock-cells = <1>;
|
||
|
|
compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
|
||
|
|
|
||
|
|
clocks = <&clk_sysin>;
|
||
|
|
|
||
|
|
clock-output-names = "clk-m-a2-pll1-phi0",
|
||
|
|
"clk-m-a2-pll1-phi1",
|
||
|
|
"clk-m-a2-pll1-phi2",
|
||
|
|
"clk-m-a2-pll1-phi3";
|
||
|
|
};
|
||
|
|
|
||
|
|
clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "st,clkgena-prediv-c32",
|
||
|
|
"st,clkgena-prediv";
|
||
|
|
|
||
|
|
clocks = <&clk_sysin>;
|
||
|
|
|
||
|
|
clock-output-names = "clk-m-a2-osc-prediv";
|
||
|
|
};
|
||
|
|
|
||
|
|
clk_m_a2_div0: clk-m-a2-div0 {
|
||
|
|
#clock-cells = <1>;
|
||
|
|
compatible = "st,clkgena-divmux-c32-odf0",
|
||
|
|
"st,clkgena-divmux";
|
||
|
|
|
||
|
|
clocks = <&clk_m_a2_osc_prediv>,
|
||
|
|
<&clk_m_a2_pll0 0>, /* PLL0 PHI0 */
|
||
|
|
<&clk_m_a2_pll1 0>; /* PLL1 PHI0 */
|
||
|
|
|
||
|
|
clock-output-names = "clk-m-vtac-main-phy",
|
||
|
|
"clk-m-vtac-aux-phy",
|
||
|
|
"clk-m-stac-phy",
|
||
|
|
"clk-m-stac-sys",
|
||
|
|
"", /* clk-m-mpestac-pg */
|
||
|
|
"", /* clk-m-mpestac-wc */
|
||
|
|
"", /* clk-m-mpevtacaux-pg*/
|
||
|
|
""; /* clk-m-mpevtacmain-pg*/
|
||
|
|
};
|
||
|
|
|
||
|
|
clk_m_a2_div1: clk-m-a2-div1 {
|
||
|
|
#clock-cells = <1>;
|
||
|
|
compatible = "st,clkgena-divmux-c32-odf1",
|
||
|
|
"st,clkgena-divmux";
|
||
|
|
|
||
|
|
clocks = <&clk_m_a2_osc_prediv>,
|
||
|
|
<&clk_m_a2_pll0 1>, /* PLL0 PHI1 */
|
||
|
|
<&clk_m_a2_pll1 1>; /* PLL1 PHI1 */
|
||
|
|
|
||
|
|
clock-output-names = "", /* clk-m-mpevtacrx0-wc */
|
||
|
|
"", /* clk-m-mpevtacrx1-wc */
|
||
|
|
"clk-m-compo-main",
|
||
|
|
"clk-m-compo-aux",
|
||
|
|
"clk-m-bdisp-0",
|
||
|
|
"clk-m-bdisp-1",
|
||
|
|
"clk-m-icn-bdisp-0",
|
||
|
|
"clk-m-icn-bdisp-1";
|
||
|
|
};
|
||
|
|
|
||
|
|
clk_m_a2_div2: clk-m-a2-div2 {
|
||
|
|
#clock-cells = <1>;
|
||
|
|
compatible = "st,clkgena-divmux-c32-odf2",
|
||
|
|
"st,clkgena-divmux";
|
||
|
|
|
||
|
|
clocks = <&clk_m_a2_osc_prediv>,
|
||
|
|
<&clk_m_a2_pll0 2>, /* PLL0 PHI2 */
|
||
|
|
<&clk_m_a2_pll1 2>; /* PLL1 PHI2 */
|
||
|
|
|
||
|
|
clock-output-names = "", /* clk-m-icn-hqvdp0 */
|
||
|
|
"", /* clk-m-icn-hqvdp1 */
|
||
|
|
"clk-m-icn-compo",
|
||
|
|
"", /* clk-m-icn-vdpaux */
|
||
|
|
"clk-m-icn-ts",
|
||
|
|
"clk-m-icn-reg-lp-10",
|
||
|
|
"clk-m-dcephy-impctrl",
|
||
|
|
""; /* Unused */
|
||
|
|
};
|
||
|
|
|
||
|
|
clk_m_a2_div3: clk-m-a2-div3 {
|
||
|
|
#clock-cells = <1>;
|
||
|
|
compatible = "st,clkgena-divmux-c32-odf3",
|
||
|
|
"st,clkgena-divmux";
|
||
|
|
|
||
|
|
clocks = <&clk_m_a2_osc_prediv>,
|
||
|
|
<&clk_m_a2_pll0 3>, /* PLL0 PHI3 */
|
||
|
|
<&clk_m_a2_pll1 3>; /* PLL1 PHI3 */
|
||
|
|
|
||
|
|
clock-output-names = ""; /* Unused */
|
||
|
|
/* Remaining outputs unused */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* A9 PLL
|
||
|
|
*/
|
||
|
|
clockgen-a9@fdde00d8 {
|
||
|
|
reg = <0xfdde00d8 0x70>;
|
||
|
|
|
||
|
|
clockgen_a9_pll: clockgen-a9-pll {
|
||
|
|
#clock-cells = <1>;
|
||
|
|
compatible = "st,stih415-plls-c32-a9", "st,clkgen-plls-c32";
|
||
|
|
|
||
|
|
clocks = <&clk_sysin>;
|
||
|
|
clock-output-names = "clockgen-a9-pll-odf";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* ARM CPU related clocks
|
||
|
|
*/
|
||
|
|
clk_m_a9: clk-m-a9@fdde00d8 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "st,stih415-clkgen-a9-mux", "st,clkgen-mux";
|
||
|
|
reg = <0xfdde00d8 0x4>;
|
||
|
|
clocks = <&clockgen_a9_pll 0>,
|
||
|
|
<&clockgen_a9_pll 0>,
|
||
|
|
<&clk_m_a0_div1 2>,
|
||
|
|
<&clk_m_a9_ext2f_div2>;
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* ARM Peripheral clock for timers
|
||
|
|
*/
|
||
|
|
arm_periph_clk: clk-m-a9-periphs {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "fixed-factor-clock";
|
||
|
|
clocks = <&clk_m_a9>;
|
||
|
|
clock-div = <2>;
|
||
|
|
clock-mult = <1>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|