546 lines
14 KiB
Plaintext
546 lines
14 KiB
Plaintext
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/*
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* Copyright (C) 2013 STMicroelectronics (R&D) Limited.
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* Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* publishhed by the Free Software Foundation.
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*/
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#include "st-pincfg.h"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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aliases {
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gpio0 = &pio0;
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gpio1 = &pio1;
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gpio2 = &pio2;
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gpio3 = &pio3;
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gpio4 = &pio4;
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gpio5 = &pio5;
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gpio6 = &pio6;
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gpio7 = &pio7;
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gpio8 = &pio8;
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gpio9 = &pio9;
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gpio10 = &pio10;
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gpio11 = &pio11;
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gpio12 = &pio12;
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gpio13 = &pio13;
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gpio14 = &pio14;
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gpio15 = &pio15;
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gpio16 = &pio16;
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gpio17 = &pio17;
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gpio18 = &pio18;
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gpio19 = &pio100;
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gpio20 = &pio101;
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gpio21 = &pio102;
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gpio22 = &pio103;
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gpio23 = &pio104;
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gpio24 = &pio105;
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gpio25 = &pio106;
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gpio26 = &pio107;
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};
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soc {
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pin-controller-sbc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stih415-sbc-pinctrl";
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st,syscfg = <&syscfg_sbc>;
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reg = <0xfe61f080 0x4>;
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reg-names = "irqmux";
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interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "irqmux";
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ranges = <0 0xfe610000 0x5000>;
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pio0: gpio@fe610000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0 0x100>;
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st,bank-name = "PIO0";
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};
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pio1: gpio@fe611000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1000 0x100>;
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st,bank-name = "PIO1";
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};
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pio2: gpio@fe612000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2000 0x100>;
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st,bank-name = "PIO2";
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};
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pio3: gpio@fe613000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x3000 0x100>;
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st,bank-name = "PIO3";
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};
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pio4: gpio@fe614000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x4000 0x100>;
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st,bank-name = "PIO4";
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};
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sbc_serial1 {
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pinctrl_sbc_serial1:sbc_serial1 {
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st,pins {
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tx = <&pio2 6 ALT3 OUT>;
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rx = <&pio2 7 ALT3 IN>;
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};
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};
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};
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keyscan {
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pinctrl_keyscan: keyscan {
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st,pins {
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keyin0 = <&pio0 2 ALT2 IN>;
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keyin1 = <&pio0 3 ALT2 IN>;
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keyin2 = <&pio0 4 ALT2 IN>;
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keyin3 = <&pio2 6 ALT2 IN>;
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keyout0 = <&pio1 6 ALT2 OUT>;
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keyout1 = <&pio1 7 ALT2 OUT>;
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keyout2 = <&pio0 6 ALT2 OUT>;
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keyout3 = <&pio2 7 ALT2 OUT>;
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};
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};
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};
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sbc_i2c0 {
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pinctrl_sbc_i2c0_default: sbc_i2c0-default {
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st,pins {
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sda = <&pio4 6 ALT1 BIDIR>;
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scl = <&pio4 5 ALT1 BIDIR>;
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};
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};
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};
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sbc_i2c1 {
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pinctrl_sbc_i2c1_default: sbc_i2c1-default {
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st,pins {
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sda = <&pio3 2 ALT2 BIDIR>;
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scl = <&pio3 1 ALT2 BIDIR>;
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};
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};
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};
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rc{
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pinctrl_ir: ir0 {
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st,pins {
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ir = <&pio4 0 ALT2 IN>;
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};
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};
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};
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gmac1 {
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pinctrl_mii1: mii1 {
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st,pins {
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txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
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txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
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txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
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txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
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txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
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txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
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txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
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col = <&pio0 7 ALT1 IN BYPASS 1000>;
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mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
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mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
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crs = <&pio1 2 ALT1 IN BYPASS 1000>;
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mdint = <&pio1 3 ALT1 IN BYPASS 0>;
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rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
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rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
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rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
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rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
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rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
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rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
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rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
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phyclk = <&pio2 3 ALT1 IN NICLK 1000 CLK_A>;
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};
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};
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pinctrl_rgmii1: rgmii1-0 {
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st,pins {
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txd0 = <&pio0 0 ALT1 OUT DE_IO 1000 CLK_A>;
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txd1 = <&pio0 1 ALT1 OUT DE_IO 1000 CLK_A>;
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txd2 = <&pio0 2 ALT1 OUT DE_IO 1000 CLK_A>;
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txd3 = <&pio0 3 ALT1 OUT DE_IO 1000 CLK_A>;
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txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
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txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
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mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
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mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
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rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>;
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rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>;
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rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>;
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rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>;
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rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>;
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rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
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phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>;
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clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
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};
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};
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};
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};
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pin-controller-front {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stih415-front-pinctrl";
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st,syscfg = <&syscfg_front>;
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reg = <0xfee0f080 0x4>;
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reg-names = "irqmux";
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interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "irqmux";
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ranges = <0 0xfee00000 0x8000>;
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pio5: gpio@fee00000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0 0x100>;
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st,bank-name = "PIO5";
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};
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pio6: gpio@fee01000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1000 0x100>;
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st,bank-name = "PIO6";
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};
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pio7: gpio@fee02000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2000 0x100>;
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st,bank-name = "PIO7";
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};
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pio8: gpio@fee03000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x3000 0x100>;
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st,bank-name = "PIO8";
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};
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pio9: gpio@fee04000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x4000 0x100>;
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st,bank-name = "PIO9";
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};
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pio10: gpio@fee05000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x5000 0x100>;
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st,bank-name = "PIO10";
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};
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pio11: gpio@fee06000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x6000 0x100>;
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st,bank-name = "PIO11";
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};
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pio12: gpio@fee07000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x7000 0x100>;
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st,bank-name = "PIO12";
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};
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i2c0 {
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pinctrl_i2c0_default: i2c0-default {
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st,pins {
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sda = <&pio9 3 ALT1 BIDIR>;
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scl = <&pio9 2 ALT1 BIDIR>;
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};
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};
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};
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i2c1 {
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pinctrl_i2c1_default: i2c1-default {
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st,pins {
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sda = <&pio12 1 ALT1 BIDIR>;
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scl = <&pio12 0 ALT1 BIDIR>;
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};
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};
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};
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};
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pin-controller-rear {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stih415-rear-pinctrl";
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st,syscfg = <&syscfg_rear>;
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reg = <0xfe82f080 0x4>;
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reg-names = "irqmux";
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interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "irqmux";
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ranges = <0 0xfe820000 0x8000>;
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pio13: gpio@fe820000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0 0x100>;
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st,bank-name = "PIO13";
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};
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pio14: gpio@fe821000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x1000 0x100>;
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st,bank-name = "PIO14";
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};
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pio15: gpio@fe822000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2000 0x100>;
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st,bank-name = "PIO15";
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};
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pio16: gpio@fe823000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x3000 0x100>;
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st,bank-name = "PIO16";
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};
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pio17: gpio@fe824000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x4000 0x100>;
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st,bank-name = "PIO17";
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};
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pio18: gpio@fe825000 {
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gpio-controller;
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#gpio-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x5000 0x100>;
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st,bank-name = "PIO18";
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};
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serial2 {
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pinctrl_serial2: serial2-0 {
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st,pins {
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tx = <&pio17 4 ALT2 OUT>;
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rx = <&pio17 5 ALT2 IN>;
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};
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};
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};
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gmac0{
|
||
|
|
pinctrl_mii0: mii0 {
|
||
|
|
st,pins {
|
||
|
|
mdint = <&pio13 6 ALT2 IN BYPASS 0>;
|
||
|
|
txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
|
||
|
|
|
||
|
|
txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
|
||
|
|
txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
|
||
|
|
txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
|
||
|
|
txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
|
||
|
|
|
||
|
|
txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
|
||
|
|
txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
|
||
|
|
crs = <&pio15 2 ALT2 IN BYPASS 1000>;
|
||
|
|
col = <&pio15 3 ALT2 IN BYPASS 1000>;
|
||
|
|
mdio = <&pio15 4 ALT2 OUT BYPASS 3000>;
|
||
|
|
mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
|
||
|
|
|
||
|
|
rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
||
|
|
rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
||
|
|
rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
||
|
|
rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
||
|
|
rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
||
|
|
rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
||
|
|
rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>;
|
||
|
|
phyclk = <&pio13 5 ALT2 OUT NICLK 1000 CLK_A>;
|
||
|
|
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pinctrl_gmii0: gmii0 {
|
||
|
|
st,pins {
|
||
|
|
mdint = <&pio13 6 ALT2 IN BYPASS 0>;
|
||
|
|
mdio = <&pio15 4 ALT2 OUT BYPASS 3000>;
|
||
|
|
mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
|
||
|
|
txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
|
||
|
|
|
||
|
|
txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
|
||
|
|
txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
|
||
|
|
txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
|
||
|
|
txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
|
||
|
|
txd4 = <&pio14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
|
||
|
|
txd5 = <&pio14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
|
||
|
|
txd6 = <&pio14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
|
||
|
|
txd7 = <&pio14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
|
||
|
|
|
||
|
|
txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
|
||
|
|
txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
|
||
|
|
crs = <&pio15 2 ALT2 IN BYPASS 1000>;
|
||
|
|
col = <&pio15 3 ALT2 IN BYPASS 1000>;
|
||
|
|
rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
||
|
|
rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
||
|
|
|
||
|
|
rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
||
|
|
rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
||
|
|
rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
||
|
|
rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
||
|
|
rxd4 = <&pio16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
||
|
|
rxd5 = <&pio16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
||
|
|
rxd6 = <&pio16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
||
|
|
rxd7 = <&pio16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
||
|
|
|
||
|
|
rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>;
|
||
|
|
clk125 = <&pio17 6 ALT1 IN NICLK 0 CLK_A>;
|
||
|
|
phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>;
|
||
|
|
|
||
|
|
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
mmc0 {
|
||
|
|
pinctrl_mmc0: mmc0 {
|
||
|
|
st,pins {
|
||
|
|
mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>;
|
||
|
|
data0 = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>;
|
||
|
|
data1 = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>;
|
||
|
|
data2 = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>;
|
||
|
|
data3 = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>;
|
||
|
|
cmd = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>;
|
||
|
|
wp = <&pio15 3 ALT4 IN>;
|
||
|
|
data4 = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>;
|
||
|
|
data5 = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>;
|
||
|
|
data6 = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>;
|
||
|
|
data7 = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>;
|
||
|
|
pwr = <&pio17 1 ALT4 OUT>;
|
||
|
|
cd = <&pio17 2 ALT4 IN>;
|
||
|
|
led = <&pio17 3 ALT4 OUT>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pin-controller-left {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
compatible = "st,stih415-left-pinctrl";
|
||
|
|
st,syscfg = <&syscfg_left>;
|
||
|
|
reg = <0xfd6bf080 0x4>;
|
||
|
|
reg-names = "irqmux";
|
||
|
|
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
interrupt-names = "irqmux";
|
||
|
|
ranges = <0 0xfd6b0000 0x3000>;
|
||
|
|
|
||
|
|
pio100: gpio@fd6b0000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <1>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0 0x100>;
|
||
|
|
st,bank-name = "PIO100";
|
||
|
|
};
|
||
|
|
pio101: gpio@fd6b1000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <1>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x1000 0x100>;
|
||
|
|
st,bank-name = "PIO101";
|
||
|
|
};
|
||
|
|
pio102: gpio@fd6b2000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <1>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x2000 0x100>;
|
||
|
|
st,bank-name = "PIO102";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pin-controller-right {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
compatible = "st,stih415-right-pinctrl";
|
||
|
|
st,syscfg = <&syscfg_right>;
|
||
|
|
reg = <0xfd33f080 0x4>;
|
||
|
|
reg-names = "irqmux";
|
||
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
interrupt-names = "irqmux";
|
||
|
|
ranges = <0 0xfd330000 0x5000>;
|
||
|
|
|
||
|
|
pio103: gpio@fd330000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <1>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0 0x100>;
|
||
|
|
st,bank-name = "PIO103";
|
||
|
|
};
|
||
|
|
pio104: gpio@fd331000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <1>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x1000 0x100>;
|
||
|
|
st,bank-name = "PIO104";
|
||
|
|
};
|
||
|
|
pio105: gpio@fd332000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <1>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x2000 0x100>;
|
||
|
|
st,bank-name = "PIO105";
|
||
|
|
};
|
||
|
|
pio106: gpio@fd333000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <1>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x3000 0x100>;
|
||
|
|
st,bank-name = "PIO106";
|
||
|
|
};
|
||
|
|
pio107: gpio@fd334000 {
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <1>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x4000 0x100>;
|
||
|
|
st,bank-name = "PIO107";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|