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Fix the half/quater rate PLL setup for AR5416, AR9160 and

Browse Source 
(beta?) AR9280 chips.

Note: This doesn't "fix" half/quarter rate support for these
chips; it merely fixes an oversight.

Obtained from:	Atheros
This commit is contained in:
Adrian Chadd 2011-05-12 03:25:24 +00:00
parent 8a90965b83
commit 003df2a90f
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=221801
1 changed files with 7 additions and 3 deletions
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10
sys/dev/ath/ath_hal/ar5416/ar5416_reset.c
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@ -1389,10 +1389,12 @@ ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan)
pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
else if (IEEE80211_IS_CHAN_QUARTER(chan))
pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
else if (IEEE80211_IS_CHAN_5GHZ(chan))
if (IEEE80211_IS_CHAN_5GHZ(chan))
pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV);
else
pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV);
} else
pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV);
} else if (AR_SREV_SOWL_10_OR_LATER(ah)) {
@ -1402,7 +1404,8 @@ ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan)
pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL);
else if (IEEE80211_IS_CHAN_QUARTER(chan))
pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL);
else if (IEEE80211_IS_CHAN_5GHZ(chan))
if (IEEE80211_IS_CHAN_5GHZ(chan))
pll |= SM(0x50, AR_RTC_SOWL_PLL_DIV);
else
pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV);
@ -1415,7 +1418,8 @@ ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan)
pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
else if (IEEE80211_IS_CHAN_QUARTER(chan))
pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
else if (IEEE80211_IS_CHAN_5GHZ(chan))
if (IEEE80211_IS_CHAN_5GHZ(chan))
pll |= SM(0xa, AR_RTC_PLL_DIV);
else
pll |= SM(0xb, AR_RTC_PLL_DIV);