powerpc/powerpc64: Enforce natural alignment in memcpy
Summary: POWER architecture CPUs (Book-S) require natural alignment for cache-inhibited storage accesses. Since we can't know the caching model for a page ahead of time, always enforce natural alignment in memcpy. This fixes a SIGBUS in X with acceleration enabled on POWER9. As part of this, revert r358672, it's no longer necessary with this fix. Regression tested by alfredo. Reviewed by: alfredo Differential Revision: https://reviews.freebsd.org/D23969
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=358688
@ -66,7 +66,7 @@ DEFINE_UIFUNC(, FN_RET, FN_NAME, FN_PARAMS)
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* Since POWER ISA 2.07B this is solved transparently
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* by the hardware
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*/
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if (cpu_features2 & PPC_FEATURE2_ARCH_2_07)
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if (cpu_features2 & PPC_FEATURE_HAS_VSX)
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return (FN_NAME_VSX);
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else
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return (FN_NAME_NOVSX);
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@ -39,6 +39,11 @@ WEAK_REFERENCE(__memcpy, memcpy);
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#define BLOCK_BYTES (1 << BLOCK_BITS)
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#define BLOCK_MASK (BLOCK_BYTES - 1)
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/* Minimum 8 byte alignment, to avoid cache-inhibited alignment faults. */
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#ifndef ALIGN_MASK
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#define ALIGN_MASK 0x7
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#endif
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/*
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* r3: dst
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* r4: src
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@ -48,6 +53,12 @@ ENTRY(FN_NAME)
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cmpdi %r5, 0 /* len == 0? nothing to do */
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beqlr-
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/* If src and dst are relatively misaligned, do byte copies. */
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andi. %r8, %r3, ALIGN_MASK
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andi. %r7, %r4, ALIGN_MASK
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cmpd %r8, %r7
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mr %r7, %r5
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bne+ .Lcopy_remaining_fix_index_byte
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mr %r8, %r3 /* save dst */
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/* align src */
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@ -30,6 +30,7 @@
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#define FN_NAME __memcpy_vsx
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#define BLOCK_BITS 6
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#define ALIGN_MASK 0xf
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/*
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* r5: bytes to copy (multiple of BLOCK_BYTES)
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