Add MIPS32/64 Rev2 CP0 intctl register definitions.
Approved by: adrian (mentor) Differential Revision: https://reviews.freebsd.org/D12300
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=323621
@ -279,6 +279,15 @@ MIPS_RW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
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MIPS_RW32_COP0(prid, MIPS_COP_0_PRID);
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/* XXX 64-bit? */
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MIPS_RW32_COP0_SEL(ebase, MIPS_COP_0_PRID, 1);
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#if defined(CPU_MIPS24K) || defined(CPU_MIPS34K) || \
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defined(CPU_MIPS74K) || defined(CPU_MIPS1004K) || \
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defined(CPU_MIPS1074K) || defined(CPU_INTERAPTIV) || \
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defined(CPU_PROAPTIV)
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/* MIPS32/64 r2 intctl */
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MIPS_RW32_COP0_SEL(intctl, MIPS_COP_0_INTCTL, 1);
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#endif
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#ifdef CPU_XBURST
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MIPS_RW32_COP0_SEL(xburst_mbox0, MIPS_COP_0_XBURST_MBOX, 0);
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MIPS_RW32_COP0_SEL(xburst_mbox1, MIPS_COP_0_XBURST_MBOX, 1);
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@ -468,6 +468,7 @@
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* 10 MIPS_COP_0_TLB_HI 3636 TLB entry high.
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* 11 MIPS_COP_0_COMPARE .333 Compare (against Count).
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* 12 MIPS_COP_0_STATUS 3333 Status register.
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* 12/1 MIPS_COP_0_INTCTL ..33 Interrupt setup (MIPS32/64 r2).
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* 13 MIPS_COP_0_CAUSE 3333 Exception cause register.
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* 14 MIPS_COP_0_EXC_PC 3636 Exception PC.
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* 15 MIPS_COP_0_PRID 3333 Processor revision identifier.
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@ -548,6 +549,7 @@
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/* MIPS32/64 */
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#define MIPS_COP_0_USERLOCAL _(4) /* sel 2 is userlevel register */
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#define MIPS_COP_0_HWRENA _(7)
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#define MIPS_COP_0_INTCTL _(12)
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#define MIPS_COP_0_DEBUG _(23)
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#define MIPS_COP_0_DEPC _(24)
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#define MIPS_COP_0_PERFCNT _(25)
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@ -561,6 +563,16 @@
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#define MIPS_MMU_BAT 0x02 /* Standard BAT */
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#define MIPS_MMU_FIXED 0x03 /* Standard fixed mapping */
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/*
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* IntCtl Register Fields
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*/
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#define MIPS_INTCTL_IPTI_MASK 0xE0000000 /* bits 31..29 timer intr # */
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#define MIPS_INTCTL_IPTI_SHIFT 29
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#define MIPS_INTCTL_IPPCI_MASK 0x1C000000 /* bits 26..29 perf counter intr # */
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#define MIPS_INTCTL_IPPCI_SHIFT 26
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#define MIPS_INTCTL_VS_MASK 0x000001F0 /* bits 5..9 vector spacing */
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#define MIPS_INTCTL_VS_SHIFT 4
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/*
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* Config Register Fields
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* (See "MIPS Architecture for Programmers Volume III", MD00091, Table 9.39)
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