-mdoc tweaks.
This commit is contained in:
parent
76dcf5720c
commit
0206ebd3c8
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=183537
@ -118,38 +118,38 @@ The number of matches on the DR2 breakpoint register.
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.Pq Event 26H
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The number of matches on the DR3 breakpoint register.
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.It Li p5-btb-false-entries
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.Pq Event 3AH, Tn Pentium MMX
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.Pq Event 3AH , Tn Pentium MMX
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The number of false entries in the BTB.
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This event is only allocated on counter 0.
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.It Li p5-btb-hits
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.Pq Event 13H
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The number of branches executed that hit in the branch table buffer.
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.It Li p5-btb-miss-prediction-on-not-taken-branch
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.Pq Event 3AH, Tn Pentium MMX
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.Pq Event 3AH , Tn Pentium MMX
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The number of times the BTB predicted a not-taken branch as taken.
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This event is only allocated on counter 1.
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.It Li p5-bus-cycle-duration
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.Pq Event 18H
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The number of cycles while a bus cycle was in progress.
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.It Li p5-bus-ownership-latency
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.Pq Event 2AH, Tn Pentium MMX
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.Pq Event 2AH , Tn Pentium MMX
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The time from bus ownership being requested to ownership being granted.
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This event is only allocated on counter 0.
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.It Li p5-bus-ownership-transfers
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.Pq Event 2AH, Tn Pentium MMX
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.Pq Event 2AH , Tn Pentium MMX
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The number of bus ownership transfers.
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This event is only allocated on counter 1.
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.It Li p5-bus-utilization-due-to-processor-activity
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.Pq Event 2EH, Tn Pentium MMX
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.Pq Event 2EH , Tn Pentium MMX
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The number of clocks the bus is busy due to the processor's own
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activity.
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This event is only allocated on counter 0.
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.It Li p5-cache-line-sharing
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.Pq Event 2CH, Tn Pentium MMX
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.Pq Event 2CH , Tn Pentium MMX
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The number of shared data lines in L1 cache.
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This event is only allocated on counter 1.
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.It Li p5-cache-m-state-line-sharing
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.Pq Event 2CH, Tn Pentium MMX
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.Pq Event 2CH , Tn Pentium MMX
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The number of hits to an M- state line due to a memory access by
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another processor.
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This event is only allocated on counter 0.
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@ -165,12 +165,12 @@ The number of instruction reads to both cacheable and uncacheable regions.
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The number of instruction reads that miss the instruction TLB.
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Both cacheable and uncacheable unreads are counted.
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.It Li p5-d1-starvation-and-fifo-is-empty
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.Pq Event 33H, Tn Pentium MMX
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.Pq Event 33H , Tn Pentium MMX
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The number of times the D1 stage cannot issue any instructions because
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the FIFO was empty.
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This event is only allocated on counter 0.
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.It Li p5-d1-starvation-and-only-one-instruction-in-fifo
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.Pq Event 33H, Tn Pentium MMX
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.Pq Event 33H , Tn Pentium MMX
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The number of times the D1 stage could issue only one instruction
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because the FIFO had one instruction ready.
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This event is only allocated on counter 1.
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@ -179,7 +179,7 @@ This event is only allocated on counter 1.
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The number of data cache lines that are written back, including
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those caused by internal and external snoops.
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.It Li p5-data-cache-tlb-miss-stall-duration
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.Pq Event 30H, Tn Pentium MMX
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.Pq Event 30H , Tn Pentium MMX
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The number of clocks the pipeline is stalled due to a data cache
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TLB miss.
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This event is only allocated on counter 1.
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@ -220,7 +220,7 @@ The number of memory write accesses that miss the data cache, counting
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both cacheable and uncacheable accesses.
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I/O accesses are not counted.
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.It Li p5-emms-instructions-executed
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.Pq Event 2DH, Tn Pentium MMX
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.Pq Event 2DH , Tn Pentium MMX
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The number of EMMS instructions executed.
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This event is only allocated on counter 0.
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.It Li p5-external-data-cache-snoop-hits
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@ -232,7 +232,7 @@ or the data line fill buffer, or one of the write back buffers.
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The number of external snoop requests accepted, including snoops that
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hit in the code cache, the data cache and that hit in neither.
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.It Li p5-floating-point-stalls-duration
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.Pq Event 32H, Tn Pentium MMX
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.Pq Event 32H , Tn Pentium MMX
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The number of cycles the pipeline is stalled due to a floating point
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freeze.
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This event is only allocated on counter 0.
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@ -245,7 +245,7 @@ Instructions generating divide-by-zero, negative square root, special
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operand and stack exceptions are not counted.
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Integer multiply instructions that use the x87 FPU are counted.
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.It Li p5-full-write-buffer-stall-duration-while-executing-mmx-instructions
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.Pq Event 3BH, Tn Pentium MMX
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.Pq Event 3BH , Tn Pentium MMX
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The number of clocks the pipeline has stalled due to full write
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buffers when executing MMX instructions.
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This event is only allocated on counter 0.
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@ -281,46 +281,46 @@ natural boundaries.
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2- and 4-byte accesses are counted as misaligned if they cross a 4
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byte boundary.
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.It Li p5-misaligned-data-memory-reference-on-mmx-instructions
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.Pq Event 36H, Tn Pentium MMX
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.Pq Event 36H , Tn Pentium MMX
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The number of misaligned data memory references when executing MMX
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instructions.
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This event is only allocated on counter 0.
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.It Li p5-mispredicted-or-unpredicted-returns
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.Pq Event 37H, Tn Pentium MMX
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.Pq Event 37H , Tn Pentium MMX
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The number of returns predicted incorrectly or not at all, only
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counting RET instructions.
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This event is only allocated on counter 0.
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.It Li p5-mmx-instruction-data-read-misses
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.Pq Event 31H, Tn Pentium MMX
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.Pq Event 31H , Tn Pentium MMX
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The number of MMX instruction data read misses.
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This event is only allocated on counter 1.
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.It Li p5-mmx-instruction-data-reads
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.Pq Event 31H, Tn Pentium MMX
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.Pq Event 31H , Tn Pentium MMX
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The number of MMX instruction data reads.
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This event is only allocated on counter 0.
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.It Li p5-mmx-instruction-data-write-misses
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.Pq Event 34H, Tn Pentium MMX
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.Pq Event 34H , Tn Pentium MMX
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The number of data write misses caused by MMX instructions.
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This event is only allocated on counter 1.
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.It Li p5-mmx-instruction-data-writes
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.Pq Event 34H, Tn Pentium MMX
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.Pq Event 34H , Tn Pentium MMX
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The number of data writes caused by MMX instructions.
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This event is only allocated on counter 0.
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.It Li p5-mmx-instructions-executed-u-pipe
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.Pq Event 2BH, Tn Pentium MMX
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.Pq Event 2BH , Tn Pentium MMX
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The number of MMX instructions executed in the U pipe.
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This event is only allocated on counter 0.
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.It Li p5-mmx-instructions-executed-v-pipe
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.Pq Event 2BH, Tn Pentium MMX
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.Pq Event 2BH , Tn Pentium MMX
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The number of MMX instructions executed in the V pipe.
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This event is only allocated on counter 1.
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.It Li p5-mmx-multiply-unit-interlock
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.Pq Event 38H, Tn Pentium MMX
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.Pq Event 38H , Tn Pentium MMX
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The number of clocks the pipeline is stalled because the destination
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of a prior MMX multiply is not ready.
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This event is only allocated on counter 0.
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.It Li p5-movd-movq-store-stall-due-to-previous-mmx-operation
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.Pq Event 38H, Tn Pentium MMX
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.Pq Event 38H , Tn Pentium MMX
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The number of clocks a MOVD/MOVQ instruction stalled in the D2 stage
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of the pipeline due to a previous MMX instruction.
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This event is only allocated on counter 1.
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@ -329,7 +329,7 @@ This event is only allocated on counter 1.
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The number of bus cycles for non-cacheable instruction or data reads,
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including cycles caused by TLB misses.
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.It Li p5-number-of-cycles-not-in-halt-state
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.Pq Event 30H, Tn Pentium MMX
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.Pq Event 30H , Tn Pentium MMX
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The number of cycles the processor is not idle due to the HLT
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instruction.
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This event is only allocated on counter 0.
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@ -346,40 +346,40 @@ interrupts, some segment register loads, and BTB misses.
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Prefetch queue flushes due to serializing instructions are not
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counted.
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.It Li p5-pipeline-flushes-due-to-wrong-branch-predictions
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.Pq Event 35H, Tn Pentium MMX
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.Pq Event 35H , Tn Pentium MMX
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The number of pipeline flushes due to wrong branch predictions
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resolved in either the E- or WB- stage of the pipeline.
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This event is only allocated on counter 0.
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.It Li p5-pipeline-flushes-due-to-wrong-branch-predictions-resolved-in-wb-stage
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.Pq Event 35H, Tn Pentium MMX
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.Pq Event 35H , Tn Pentium MMX
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The number of pipeline flushes due to wrong branch predictions
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resolved in the stage of the pipeline.
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This event is only allocated on counter 1.
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.It Li p5-pipeline-stall-for-mmx-instruction-data-memory-reads
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.Pq Event 36H, Tn Pentium MMX
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.Pq Event 36H , Tn Pentium MMX
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The number of clocks during pipeline stalls caused by waiting MMX data
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memory reads.
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This event is only allocated on counter 1.
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.It Li p5-predicted-returns
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.Pq Event 37H, Tn Pentium MMX
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.Pq Event 37H , Tn Pentium MMX
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The number of predicted returns, whether correct or incorrect.
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This counter only counts RET instructions.
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This event is only allocated on counter 1.
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.It Li p5-returns
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.Pq Event 39H, Tn Pentium MMX
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.Pq Event 39H , Tn Pentium MMX
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The number of RET instructions executed.
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This event is only allocated on counter 0.
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.It Li p5-saturating-mmx-instructions-executed
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.Pq Event 2FH, Tn Pentium MMX
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.Pq Event 2FH , Tn Pentium MMX
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The number of saturating MMX instructions executed.
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This event is only allocated on counter 0.
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.It Li p5-saturations-performed
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.Pq Event 2FH, Tn Pentium MMX
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.Pq Event 2FH , Tn Pentium MMX
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The number of saturating MMX instructions executed when at least one
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of its results were actually saturated.
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This event is only allocated on counter 1.
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.It Li p5-stall-on-mmx-instruction-write-to-e-o-m-state-line
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.Pq Event 3BH, Tn Pentium MMX
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.Pq Event 3BH , Tn Pentium MMX
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The number of clocks during stalls on MMX instructions writing to
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E- or M- state cache lines.
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This event is only allocated on counter 1.
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@ -392,11 +392,11 @@ line.
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The number of events that may cause a hit in the BTB, namely either
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taken branches or BTB hits.
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.It Li p5-taken-branches
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.Pq Event 32H, Tn Pentium MMX
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.Pq Event 32H , Tn Pentium MMX
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The number of taken branches.
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This event is only allocated on counter 1.
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.It Li p5-transitions-between-mmx-and-fp-instructions
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.Pq Event 2DH, Tn Pentium MMX
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.Pq Event 2DH , Tn Pentium MMX
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The number of transitions between MMX and floating-point instructions
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and vice-versa.
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This event is only allocated on counter 1.
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@ -414,7 +414,7 @@ buffers being full.
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The number of writes that hit exclusive or modified lines in the data
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cache.
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.It Li p5-writes-to-noncacheable-memory
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.Pq Event 2EH, Tn Pentium MMX
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.Pq Event 2EH , Tn Pentium MMX
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The number of writes to non-cacheable memory, including write cycles
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caused by TLB misses and I/O writes.
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This event is only allocated on counter 1.
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